diff --git a/boards/nucleo-wl55jc/Makefile.include b/boards/nucleo-wl55jc/Makefile.include
index 8db8eaed90..822847ce1f 100644
--- a/boards/nucleo-wl55jc/Makefile.include
+++ b/boards/nucleo-wl55jc/Makefile.include
@@ -1,2 +1,18 @@
+# CPU2 defines a restricted memory region. This is not available for
+# CPU1 linking or general access, for now we define it by its default
+# value.
+# The value is descrbed in section 4.10.19 FLASH secure Flash start address
+# register (FLASH_SFR) in SFSA[6:0] register of reference manual.
+# 0x0003 F800 -> 254K -> 2K left for CPU2.
+CPU2_ROM_LEN = 2K
+
+# CPU2 can define restricted SRAM within SRAM2a and SRAM2b. These subregions
+# will generate busfaults if accessed by CPU1. For now we will assume that both
+# SRAM2a regions are completely dedicated to CPU2.
+# The value is described in section 4.10.20 FLASH secure SRAM start address and CPU2
+# reset vector register(FLASH_SRRVR) in SBRSA[4:0] of reference manual.
+# Section 4.6.4 CPU2 security (ESE) provides detailed information on the same.
+CPU2_RAM_LEN = 1K
+
 # load the common Makefile.include for Nucleo boards
 include $(RIOTBOARD)/common/nucleo64/Makefile.include
diff --git a/cpu/stm32/Makefile.features b/cpu/stm32/Makefile.features
index ac635c9b11..2dae21cef1 100644
--- a/cpu/stm32/Makefile.features
+++ b/cpu/stm32/Makefile.features
@@ -11,7 +11,7 @@ FEATURES_PROVIDED += periph_timer_periodic
 FEATURES_PROVIDED += periph_uart_modecfg
 FEATURES_PROVIDED += periph_uart_nonblocking
 
-ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb))
+ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 wb wl))
   FEATURES_PROVIDED += periph_flashpage
   FEATURES_PROVIDED += periph_flashpage_pagewise
 endif
diff --git a/cpu/stm32/Makefile.include b/cpu/stm32/Makefile.include
index 613edb9633..7259e63ba2 100644
--- a/cpu/stm32/Makefile.include
+++ b/cpu/stm32/Makefile.include
@@ -12,7 +12,7 @@ KB := 1024
 ROM_LEN_K := $(shell echo $(ROM_LEN) | sed 's/K//')
 RAM_LEN_K := $(shell echo $(RAM_LEN) | sed 's/K//')
 
-ifeq (stm32wb55rg,$(CPU_MODEL))
+ifneq (,$(filter w%,$(CPU_FAM)))
   # adjust RAM_LEN and ROM_LEN according to CPU2 RAM_LEN and ROM_LEN
   CPU2_RAM_LEN_K := $(shell echo $(CPU2_RAM_LEN) | sed 's/K//')
   RAM_LEN := $(shell echo $$(( ($(RAM_LEN_K) - $(CPU2_RAM_LEN_K) ) * $(KB) )))
diff --git a/cpu/stm32/include/cpu_conf.h b/cpu/stm32/include/cpu_conf.h
index 8483d6debd..d5605df907 100644
--- a/cpu/stm32/include/cpu_conf.h
+++ b/cpu/stm32/include/cpu_conf.h
@@ -106,7 +106,7 @@ extern "C" {
    || defined(CPU_LINE_STM32F030xC) || defined(CPU_LINE_STM32F103xE) \
    || defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L4) \
    || defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) \
-   || defined(CPU_FAM_STM32L5)
+   || defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
 #define FLASHPAGE_SIZE                  (2048U)
 #elif defined(CPU_LINE_STM32F051x8) || defined(CPU_LINE_STM32F042x6) \
    || defined(CPU_LINE_STM32F070xB) || defined(CPU_LINE_STM32F030x8) \
@@ -195,7 +195,7 @@ extern "C" {
  */
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
-    defined(CPU_FAM_STM32L5)
+    defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
 #define FLASHPAGE_WRITE_BLOCK_SIZE            (8U)
 typedef uint64_t stm32_flashpage_block_t;
 #elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
@@ -210,7 +210,7 @@ typedef uint16_t stm32_flashpage_block_t;
 
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
-    defined(CPU_FAM_STM32L5)
+    defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32WL)
 #define FLASHPAGE_WRITE_BLOCK_ALIGNMENT       (8U)
 #else
 /* Writing should be always 4 bytes aligned */
diff --git a/cpu/stm32/periph/flash_common.c b/cpu/stm32/periph/flash_common.c
index ca6faf5748..6e5265830d 100644
--- a/cpu/stm32/periph/flash_common.c
+++ b/cpu/stm32/periph/flash_common.c
@@ -42,7 +42,7 @@
 #if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
     defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32F7)
+    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
 #define FLASH_KEY1             ((uint32_t)0x45670123)
 #define FLASH_KEY2             ((uint32_t)0xCDEF89AB)
 #endif
diff --git a/cpu/stm32/periph/flashpage.c b/cpu/stm32/periph/flashpage.c
index 7afa590ac0..08a3ee36e4 100644
--- a/cpu/stm32/periph/flashpage.c
+++ b/cpu/stm32/periph/flashpage.c
@@ -110,10 +110,12 @@ static void _erase_page(void *page_addr)
 #elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
       defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
       defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32F2) || \
-      defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7)
+      defined(CPU_FAM_STM32F4) || defined(CPU_FAM_STM32F7) || \
+      defined(CPU_FAM_STM32WL)
     DEBUG("[flashpage] erase: setting the page address\n");
     uint8_t pn;
-#if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB)
+#if (FLASHPAGE_NUMOF <= MAX_PAGES_PER_BANK) || defined(CPU_FAM_STM32WB) || \
+    defined(CPU_FAM_STM32WL)
     pn = (uint8_t)flashpage_page(page_addr);
 #else
     uint16_t page = flashpage_page(page_addr);
@@ -188,7 +190,7 @@ void flashpage_erase(unsigned page)
     assert(page < (int)FLASHPAGE_NUMOF);
 
     /* ensure there is no attempt to write to CPU2 protected area */
-#if defined(CPU_FAM_STM32WB)
+#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
     assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
 #endif
 
@@ -253,7 +255,7 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
     defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32F7)
+    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
     /* set PG bit and program page to flash */
     CNTRL_REG |= FLASH_CR_PG;
 #endif
@@ -273,7 +275,7 @@ void flashpage_write(void *target_addr, const void *data, size_t len)
     defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
     defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
     defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
-    defined(CPU_FAM_STM32F7)
+    defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL)
     CNTRL_REG &= ~(FLASH_CR_PG);
 #endif
     DEBUG("[flashpage_raw] write: done writing data\n");
diff --git a/drivers/periph_common/flashpage.c b/drivers/periph_common/flashpage.c
index 8d0f4a4640..17db28eb47 100644
--- a/drivers/periph_common/flashpage.c
+++ b/drivers/periph_common/flashpage.c
@@ -33,7 +33,7 @@ void flashpage_read(unsigned page, void *data)
 {
     assert(page < FLASHPAGE_NUMOF);
 
-#if defined(CPU_FAM_STM32WB)
+#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
     assert(page < (FLASH->SFR & FLASH_SFR_SFSA));
 #endif
 
@@ -44,7 +44,7 @@ int flashpage_verify(unsigned page, const void *data)
 {
     assert(page < (int)FLASHPAGE_NUMOF);
 
-#if defined(CPU_FAM_STM32WB)
+#if defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32WL)
     assert(page < (int)(FLASH->SFR & FLASH_SFR_SFSA));
 #endif