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cpu/samd21: handle silicon errata

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- The `periph_flashpage` driver expects the manual write bit to be set
   This should be set by default, but the SAM D20/SAM D21 errata sheets
   correct that this is indeed *not* set by default, which may cause
   spurious writes.

 - SAM D20 may not wake up from any sleep mode if sleep power reduction
   is enabled for the NVM block.
This commit is contained in:
Benjamin Valentin 2022-06-09 18:27:30 +02:00
parent f4691db39d
commit 2c04d6cefe
1 changed files with 8 additions and 1 deletions
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9
cpu/samd21/cpu.c
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@ -117,7 +117,14 @@ static void clk_init(void)
/* adjust NVM wait states */
PM->APBBMASK.reg |= PM_APBBMASK_NVMCTRL;
NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(WAITSTATES);
NVMCTRL->CTRLB.reg = NVMCTRL_CTRLB_RWS(WAITSTATES)
#ifdef CPU_SAMD20
/* errata: In Standby, Idle1 and Idle2 Sleep modes,
the device might not wake up from sleep. */
| NVMCTRL_CTRLB_SLEEPPRM_DISABLED
#endif
/* errata: Default value of MANW in NVM.CTRLB is 0. */
| NVMCTRL_CTRLB_MANW;
PM->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL;
#if CLOCK_8MHZ