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Merge pull request #5537 from kYc0o/reworked_uart_wfix
cpu/atmega2560: reworked UART (from #5026)
This commit is contained in:
kYc0o
GitHub
commit
2adf76c977
@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
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* Copyright (C) 2014-2016 Freie Universität Berlin
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* 2014 Hinnerk van Bruinehsen
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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@ -14,6 +15,7 @@
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* @brief Peripheral MCU configuration for the Arduino Mega 2560 board
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*
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* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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@ -57,109 +59,26 @@ extern "C" {
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/**
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* @brief UART configuration
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*
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* The UART devices have fixed pin mappings, so all we need to do, is to specify
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* which devices we would like to use and their corresponding RX interrupts. See
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* the reference manual for the fixed pin mapping.
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*
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* @{
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*/
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#define UART_NUMOF (4U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 1
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#define UART_3_EN 1
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/* UART 0 registers */
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#define UART0_CTRL_STAT_A UCSR0A
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#define UART0_CTRL_STAT_B UCSR0B
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#define UART0_CTRL_STAT_C UCSR0C
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#define UART0_BAUD_RATE_L UBRR0L
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#define UART0_BAUD_RATE_H UBRR0H
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#define UART0_DATA_REGISTER UDR0
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#define UART_0 MEGA_UART0
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#define UART_0_ISR USART0_RX_vect
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/* Flags */
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#define UART0_RX_COMPLETE RXC0
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#define UART0_DATA_EMPTY UDRE0
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#define UART0_RX_EN RXEN0
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#define UART0_TX_EN TXEN0
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#define UART0_RXC_IRQ_EN RXCIE0
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#define UART0_TXC_IRQ_EN TXCIE0
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#define UART0_8BIT_SIZE (1 << UCSZ00) | (1 << UCSZ01)
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#define UART_1 MEGA_UART1
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#define UART_1_ISR USART1_RX_vect
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/* UART0 helper macros */
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#define UART0_RX_TX_EN UART0_CTRL_STAT_B |= (1 << UART0_RX_EN) | (1 << UART0_TX_EN)
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#define UART0_RX_IRQ_EN UART0_CTRL_STAT_B |= (1 << UART0_RXC_IRQ_EN)
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#define UART0_SET_8BIT_SIZE UART0_CTRL_STAT_C |= UART0_8BIT_SIZE
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#define UART0_RECEIVED_DATA (UART0_CTRL_STAT_A & (1 << UART0_RX_COMPLETE))
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#define UART0_DTREG_EMPTY (UART0_CTRL_STAT_A & (1 << UART0_DATA_EMPTY))
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#define UART_2 MEGA_UART2
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#define UART_2_ISR USART2_RX_vect
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/* UART 1 registers */
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#define UART1_CTRL_STAT_A UCSR1A
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#define UART1_CTRL_STAT_B UCSR1B
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#define UART1_CTRL_STAT_C UCSR1C
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#define UART1_BAUD_RATE_L UBRR1L
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#define UART1_BAUD_RATE_H UBRR1H
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#define UART1_DATA_REGISTER UDR1
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/* Flags */
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#define UART1_RX_COMPLETE RXC1
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#define UART1_DATA_EMPTY UDRE1
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#define UART1_RX_EN RXEN1
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#define UART1_TX_EN TXEN1
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#define UART1_RXC_IRQ_EN RXCIE1
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#define UART1_TXC_IRQ_EN TXCIE1
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#define UART1_8BIT_SIZE (1 << UCSZ10) | (1 << UCSZ11)
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/* UART1 helper macros */
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#define UART1_RX_TX_EN UART1_CTRL_STAT_B |= (1 << UART1_RX_EN) | (1 << UART1_TX_EN)
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#define UART1_RX_IRQ_EN UART1_CTRL_STAT_B |= (1 << UART1_RXC_IRQ_EN)
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#define UART1_SET_8BIT_SIZE UART1_CTRL_STAT_C |= UART1_8BIT_SIZE
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#define UART1_RECEIVED_DATA (UART1_CTRL_STAT_A & (1 << UART1_RX_COMPLETE))
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#define UART1_DTREG_EMPTY (UART1_CTRL_STAT_A & (1 << UART1_DATA_EMPTY))
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/* UART 2 registers */
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#define UART2_CTRL_STAT_A UCSR2A
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#define UART2_CTRL_STAT_B UCSR2B
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#define UART2_CTRL_STAT_C UCSR2C
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#define UART2_BAUD_RATE_L UBRR2L
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#define UART2_BAUD_RATE_H UBRR2H
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#define UART2_DATA_REGISTER UDR2
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/* Flags */
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#define UART2_RX_COMPLETE RXC2
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#define UART2_DATA_EMPTY UDRE2
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#define UART2_RX_EN RXEN2
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#define UART2_TX_EN TXEN2
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#define UART2_RXC_IRQ_EN RXCIE2
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#define UART2_TXC_IRQ_EN TXCIE2
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#define UART2_8BIT_SIZE (1 << UCSZ20) | (1 << UCSZ21)
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/* UART2 helper macros */
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#define UART2_RX_TX_EN UART2_CTRL_STAT_B |= (1 << UART2_RX_EN) | (1 << UART2_TX_EN)
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#define UART2_RX_IRQ_EN UART2_CTRL_STAT_B |= (1 << UART2_RXC_IRQ_EN)
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#define UART2_SET_8BIT_SIZE UART2_CTRL_STAT_C |= UART2_8BIT_SIZE
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#define UART2_RECEIVED_DATA (UART2_CTRL_STAT_A & (1 << UART2_RX_COMPLETE))
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#define UART2_DTREG_EMPTY (UART2_CTRL_STAT_A & (1 << UART2_DATA_EMPTY))
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/* UART 2 registers */
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#define UART3_CTRL_STAT_A UCSR3A
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#define UART3_CTRL_STAT_B UCSR3B
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#define UART3_CTRL_STAT_C UCSR3C
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#define UART3_BAUD_RATE_L UBRR3L
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#define UART3_BAUD_RATE_H UBRR3H
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#define UART3_DATA_REGISTER UDR3
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/* Flags */
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#define UART3_RX_COMPLETE RXC3
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#define UART3_DATA_EMPTY UDRE3
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#define UART3_RX_EN RXEN3
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#define UART3_TX_EN TXEN3
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#define UART3_RXC_IRQ_EN RXCIE3
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#define UART3_TXC_IRQ_EN TXCIE3
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#define UART3_8BIT_SIZE (1 << UCSZ30) | (1 << UCSZ31)
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/* UART3 helper macros */
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#define UART3_RX_TX_EN UART3_CTRL_STAT_B |= (1 << UART3_RX_EN) | (1 << UART3_TX_EN)
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#define UART3_RX_IRQ_EN UART3_CTRL_STAT_B |= (1 << UART3_RXC_IRQ_EN)
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#define UART3_SET_8BIT_SIZE UART3_CTRL_STAT_C |= UART3_8BIT_SIZE
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#define UART3_RECEIVED_DATA (UART3_CTRL_STAT_A & (1 << UART3_RX_COMPLETE))
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#define UART3_DTREG_EMPTY (UART3_CTRL_STAT_A & (1 << UART3_DATA_EMPTY))
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#define UART_3 MEGA_UART3
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#define UART_3_ISR USART3_RX_vect
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/** @} */
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/**
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@ -46,6 +46,18 @@ typedef struct {
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REG16 OCR[3]; /**< output compare */
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} mega_timer_t;
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/**
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* @brief UART register map
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*/
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typedef struct {
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REG8 CSRA; /**< control and status register A */
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REG8 CSRB; /**< control and status register B */
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REG8 CSRC; /**< control and status register C */
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REG8 reserved; /**< reserved */
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REG16 BRR; /**< baud rate register */
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REG8 DR; /**< data register */
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} mega_uart_t;
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/**
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* @brief Base register address definitions
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* @{
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@ -54,6 +66,11 @@ typedef struct {
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#define MEGA_TIMER3_BASE (uint16_t *)(&TCCR3A)
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#define MEGA_TIMER4_BASE (uint16_t *)(&TCCR4A)
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#define MEGA_TIMER5_BASE (uint16_t *)(&TCCR5A)
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#define MEGA_UART0_BASE ((uint16_t *)(&UCSR0A))
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#define MEGA_UART1_BASE ((uint16_t *)(&UCSR1A))
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#define MEGA_UART2_BASE ((uint16_t *)(&UCSR2A))
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#define MEGA_UART3_BASE ((uint16_t *)(&UCSR3A))
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/** @} */
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/**
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@ -64,6 +81,11 @@ typedef struct {
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#define MEGA_TIMER3 ((mega_timer_t *)MEGA_TIMER3_BASE)
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#define MEGA_TIMER4 ((mega_timer_t *)MEGA_TIMER4_BASE)
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#define MEGA_TIMER5 ((mega_timer_t *)MEGA_TIMER5_BASE)
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#define MEGA_UART0 ((mega_uart_t *)MEGA_UART0_BASE)
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#define MEGA_UART1 ((mega_uart_t *)MEGA_UART1_BASE)
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#define MEGA_UART2 ((mega_uart_t *)MEGA_UART2_BASE)
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#define MEGA_UART3 ((mega_uart_t *)MEGA_UART3_BASE)
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/** @} */
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#ifdef __cplusplus
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@ -19,216 +19,115 @@
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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#include "thread.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph/uart.h"
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#include "periph_conf.h"
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/**
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* @brief Allocate memory to store the callback functions.
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* @brief Configured device map
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* @{
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*/
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static uart_isr_ctx_t config[UART_NUMOF];
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#if UART_NUMOF
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static mega_uart_t *dev[] = {
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#ifdef UART_0
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UART_0,
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#endif
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#ifdef UART_1
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UART_1,
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#endif
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#ifdef UART_2
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UART_2,
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#endif
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#ifdef UART_3
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UART_3
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#endif
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};
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#else
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/* fallback if no UART is defined */
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static const mega_uart_t *dev[] = { NULL };
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#endif
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static int init_base(uart_t uart, uint32_t baudrate);
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/**
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* @brief Allocate memory to store the callback functions.
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*/
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static uart_isr_ctx_t isr_ctx[UART_NUMOF];
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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/* initialize basic functionality */
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int res = init_base(uart, baudrate);
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if (res != 0) {
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return res;
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/* make sure the given device is valid */
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if (uart >= UART_NUMOF) {
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return -1;
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}
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/* register callbacks */
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config[uart].rx_cb = rx_cb;
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config[uart].arg = arg;
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/* register interrupt context */
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isr_ctx[uart].rx_cb = rx_cb;
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isr_ctx[uart].arg = arg;
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/* configure interrupts and enable RX interrupt */
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switch (uart) {
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#if UART_0_EN
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/* disable and reset UART */
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dev[uart]->CSRB = 0;
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dev[uart]->CSRA = 0;
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case UART_0:
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UART0_RX_IRQ_EN;
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break;
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#endif /* UART_0_EN */
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#if UART_1_EN
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case UART_1:
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UART1_RX_IRQ_EN;
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break;
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#endif /* UART_1_EN */
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#if UART_2_EN
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case UART_2:
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UART2_RX_IRQ_EN;
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break;
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#endif /* UART_2_EN */
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#if UART_3_EN
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case UART_3:
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UART3_RX_IRQ_EN;
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break;
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#endif /* UART_3_EN */
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}
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return 0;
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}
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static int init_base(uart_t uart, uint32_t baudrate)
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{
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uint16_t clock_divider = CLOCK_CORECLOCK / (16 * baudrate);
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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/* enable RX and TX */
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UART0_RX_TX_EN;
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/* use 8 Bit characters */
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UART0_SET_8BIT_SIZE;
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/* set clock divider */
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UART0_BAUD_RATE_L = clock_divider;
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UART0_BAUD_RATE_H = (clock_divider >> 8);
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break;
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#endif /* UART_0 */
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#if UART_1_EN
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case UART_1:
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/* enable RX and TX */
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UART1_RX_TX_EN;
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/* use 8 Bit characters */
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UART1_SET_8BIT_SIZE;
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/* set clock divider */
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UART1_BAUD_RATE_L = clock_divider;
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UART1_BAUD_RATE_H = (clock_divider >> 8);
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break;
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#endif /* UART_1 */
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#if UART_2_EN
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case UART_2:
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/* enable RX and TX */
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UART2_RX_TX_EN;
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/* use 8 Bit characters */
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UART2_SET_8BIT_SIZE;
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/* set clock divider */
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UART2_BAUD_RATE_L = clock_divider;
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UART2_BAUD_RATE_H = (clock_divider >> 8);
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break;
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#endif /* UART_2 */
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#if UART_3_EN
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case UART_3:
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/* enable RX and TX */
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UART3_RX_TX_EN;
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/* use 8 Bit characters */
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UART3_SET_8BIT_SIZE;
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/* set clock divider */
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UART3_BAUD_RATE_L = clock_divider;
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UART3_BAUD_RATE_H = (clock_divider >> 8);
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break;
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#endif /* UART_3 */
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default:
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(void)clock_divider; /* this makes cppcheck happy */
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}
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/* configure UART to 8N1 mode */
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dev[uart]->CSRC = (1 << UCSZ00) | (1 << UCSZ01);
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/* set clock divider */
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dev[uart]->BRR = CLOCK_CORECLOCK / (16 * baudrate);
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/* enable RX and TX and the RX interrupt */
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dev[uart]->CSRB = ((1 << RXCIE0) | (1 << RXEN0) | (1 << TXEN0));
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return 0;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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switch (uart) {
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#if UART_0_EN
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case UART_0:
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for (unsigned i = 0; i < len; i++) {
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while (!UART0_DTREG_EMPTY);
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UART0_DATA_REGISTER = data[i];
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}
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break;
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#endif /* UART_0_EN */
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#if UART_1_EN
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case UART_1:
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for (unsigned i = 0; i < len; i++) {
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while (!UART1_DTREG_EMPTY);
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UART1_DATA_REGISTER = data[i];
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}
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break;
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#endif /* UART_1_EN */
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#if UART_2_EN
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case UART_2:
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for (unsigned i = 0; i < len; i++) {
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while (!UART2_DTREG_EMPTY);
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UART2_DATA_REGISTER = data[i];
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}
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break;
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#endif /* UART_2_EN */
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#if UART_3_EN
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case UART_3:
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for (unsigned i = 0; i < len; i++) {
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while (!UART3_DTREG_EMPTY);
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UART3_DATA_REGISTER = data[i];
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}
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break;
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#endif /* UART_3_EN */
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for (size_t i = 0; i < len; i++) {
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while (!(dev[uart]->CSRA & (1 << UDRE0)));
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dev[uart]->DR = data[i];
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}
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}
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#if UART_0_EN
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ISR(USART0_RX_vect, ISR_BLOCK)
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static inline void isr_handler(int num)
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{
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__enter_isr();
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config[UART_0].rx_cb(config[UART_0].arg, UART0_DATA_REGISTER);
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isr_ctx[num].rx_cb(isr_ctx[num].arg, dev[num]->DR);
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if (sched_context_switch_request) {
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thread_yield();
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}
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__exit_isr();
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}
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#endif /* UART_0_EN */
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#if UART_1_EN
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ISR(USART1_RX_vect, ISR_BLOCK)
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#ifdef UART_0_ISR
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ISR(UART_0_ISR, ISR_BLOCK)
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{
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__enter_isr();
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config[UART_1].rx_cb(config[UART_1].arg, UART1_DATA_REGISTER);
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if (sched_context_switch_request) {
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thread_yield();
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}
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isr_handler(0);
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__exit_isr();
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}
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#endif /* UART_1_EN */
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#endif /* UART_0_ISR */
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#if UART_2_EN
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ISR(USART2_RX_vect, ISR_BLOCK)
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#ifdef UART_1_ISR
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ISR(UART_1_ISR, ISR_BLOCK)
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{
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__enter_isr();
|
||||
config[UART_2].rx_cb(config[UART_2].arg, UART2_DATA_REGISTER);
|
||||
|
||||
if (sched_context_switch_request) {
|
||||
thread_yield();
|
||||
}
|
||||
isr_handler(1);
|
||||
__exit_isr();
|
||||
}
|
||||
#endif /* UART_2_EN */
|
||||
#endif /* UART_1_ISR */
|
||||
|
||||
#if UART_3_EN
|
||||
ISR(USART3_RX_vect, ISR_BLOCK)
|
||||
#ifdef UART_2_ISR
|
||||
ISR(UART_2_ISR, ISR_BLOCK)
|
||||
{
|
||||
__enter_isr();
|
||||
config[UART_3].rx_cb(config[UART_3].arg, UART3_DATA_REGISTER);
|
||||
|
||||
if (sched_context_switch_request) {
|
||||
thread_yield();
|
||||
}
|
||||
isr_handler(2);
|
||||
__exit_isr();
|
||||
}
|
||||
#endif /* UART_3_EN */
|
||||
#endif /* UART_2_ISR */
|
||||
|
||||
#ifdef UART_3_ISR
|
||||
ISR(UART_3_ISR, ISR_BLOCK)
|
||||
{
|
||||
__enter_isr();
|
||||
isr_handler(3);
|
||||
__exit_isr();
|
||||
}
|
||||
#endif /* UART_3_ISR */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user