From 2a3033b3ca40bf327007fbb56b0c390eef396f7f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?K=C3=A9vin=20Roussel?= Date: Thu, 27 Feb 2014 12:48:30 +0100 Subject: [PATCH] boards/z1: initial import --- boards/z1/Makefile | 3 + boards/z1/Makefile.dep | 2 + boards/z1/Makefile.include | 38 +++++ boards/z1/board.c | 222 +++++++++++++++++++++++++ boards/z1/driver_cc2420.c | 267 ++++++++++++++++++++++++++++++ boards/z1/include/board-conf.h | 29 ++++ boards/z1/include/board.h | 77 +++++++++ boards/z1/uart.c | 134 +++++++++++++++ examples/ccn-lite-client/Makefile | 7 +- examples/ccn-lite-relay/Makefile | 7 +- examples/rpl_udp/Makefile | 7 +- tests/test_bloom/Makefile | 3 +- tests/test_bloom_bytes/Makefile | 3 +- tests/test_pnet/Makefile | 5 +- 14 files changed, 791 insertions(+), 13 deletions(-) create mode 100644 boards/z1/Makefile create mode 100644 boards/z1/Makefile.dep create mode 100644 boards/z1/Makefile.include create mode 100644 boards/z1/board.c create mode 100644 boards/z1/driver_cc2420.c create mode 100644 boards/z1/include/board-conf.h create mode 100644 boards/z1/include/board.h create mode 100644 boards/z1/uart.c diff --git a/boards/z1/Makefile b/boards/z1/Makefile new file mode 100644 index 0000000000..aa1b315c5d --- /dev/null +++ b/boards/z1/Makefile @@ -0,0 +1,3 @@ +MODULE = $(BOARD)_base + +include $(RIOTBASE)/Makefile.base diff --git a/boards/z1/Makefile.dep b/boards/z1/Makefile.dep new file mode 100644 index 0000000000..4392a18adb --- /dev/null +++ b/boards/z1/Makefile.dep @@ -0,0 +1,2 @@ +USEMODULE += msp430_common + diff --git a/boards/z1/Makefile.include b/boards/z1/Makefile.include new file mode 100644 index 0000000000..be085a42fb --- /dev/null +++ b/boards/z1/Makefile.include @@ -0,0 +1,38 @@ +include $(RIOTBOARD)/$(BOARD)/Makefile.dep +## the cpu to build for +export CPU = msp430x16x +export MCU = msp430f2617 + +# toolchain config +export PREFIX = msp430- +export CC = $(PREFIX)gcc +export AR = $(PREFIX)ar +export CFLAGS += -std=c99 -Wstrict-prototypes -gdwarf-2 -Os -Wall -mmcu=$(MCU) +export ASFLAGS += -mmcu=$(MCU) --defsym $(MCU)=1 --gdwarf-2 +export AS = $(PREFIX)as +export LINK = $(PREFIX)gcc +export SIZE = $(PREFIX)size +export OBJCOPY = $(PREFIX)objcopy +export LINKFLAGS = -mmcu=$(MCU) -lgcc $(BINDIR)msp430_common/startup.o +export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm.py +export FLASHER = goodfet.bsl +ifeq ($(strip $(PORT)),) + export PORT = /dev/ttyUSB0 +endif +export HEXFILE = $(BINDIR)$(PROJECT).hex +export FFLAGS = --z1 -I -c $(PORT) -r -e -p $(HEXFILE) +export OFLAGS = -O ihex + +export INCLUDES += -I $(RIOTCPU)/msp430-common/include -I$(RIOTBOARD)/$(BOARD)/include -I$(RIOTBASE)/drivers/cc2420/include -I$(RIOTBASE)/sys/net/include + +ifneq (,$(filter defaulttransceiver,$(USEMODULE))) + ifeq (,$(filter cc2240,$(USEMODULE))) + USEMODULE += cc2420 + endif + ifeq (,$(filter transceiver,$(USEMODULE))) + USEMODULE += transceiver + endif +endif + +export UNDEF += $(BINDIR)msp430_common/startup.o + diff --git a/boards/z1/board.c b/boards/z1/board.c new file mode 100644 index 0000000000..3a78d0a0b1 --- /dev/null +++ b/boards/z1/board.c @@ -0,0 +1,222 @@ +/* + * board.c - Board initialization for the Zolertia Z1 + * Copyright (C) 2014 INRIA + * + * Author : Kévin Roussel + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License. See the file LICENSE in the top level directory for more + * details. */ + +/** + * @ingroup board_z1 + * @{ + * + * @file board.c + * @brief Board specific implementations for the Zolertia Z1 + * + * @author Kévin Roussel + * + * @} + */ + + +#include "cpu.h" +#include "board.h" + +void uart_init(void); + + +static void z1_ports_init(void) +{ + /* Port 1: + * P1.0 is not assigned by default + * P1.1 is the bootstrap-loader (BSL) TX pin -> input, special function, default to GND + * THIS PIN MUST *NEVER* BE USED IN NORMAL EXECUTION, SINCE IT INTERFERES WITH UART0 !!! + * P1.2 receives the FIFOP interrupt from CC2420 -> input, GPIO, default to GND + * P1.3 receives the FIFO/GIO0 interrupt from CC2420 -> input, GPIO, default to GND + * P1.4 receives the CCA/GIO1 signal from CC2420 -> input, GPIO, default to GND + * P1.5 is wired to Vcc -> input, GPIO, default to Vcc + * P1.6 receives interrupt INT1 from accelerometer -> input, GPIO, default to GND + * P1.7 receives interrupt INT2 from accelerometer -> input, GPIO, default to GND + */ + P1SEL = 0x02; /* Port1 Select: 00000010 = 0x02 */ + P1OUT = 0x20; /* Port1 Output: 00100000 = 0x20 */ + P1DIR = 0x00; /* Port1 Direction: 00000000 = 0x00 */ + + /* Port 2: + * P2.0 is not assigned by default + * P2.1 is not assigned by default + * P2.2 is the bootstrap-loader (BSL) RX pin -> input, special function, default to GND + * THIS PIN MUST *NEVER* BE USED IN NORMAL EXECUTION, SINCE IT INTERFERES WITH UART0 !!! + * P2.3 is not assigned by default + * P2.4 is used as an active-low output to the BSL and USB interface -> output, GPIO, default to Vcc + * P2.5 is connected to the active-low "user interrupt" button -> input, GPIO, default to Vcc + * P2.6 is not assigned by default + * P2.7 receives the ALERT interrupt from TMP102 -> input, GPIO, default to Vcc + */ + P2SEL = 0x04; /* Port2 Select: 00000100 = 0x04 */ + P2OUT = 0xB0; /* Port2 Output: 10110000 = 0xB0 */ + P2DIR = 0xD0; /* Port2 Direction: 11010000 = 0xD0 */ + + /* Port 3: + * P3.0 is the radio (CC2420) active-low chip select -> output, GPIO, default to Vcc + * P3.1 is SPI's MOSI pin -> output, special function, default to GND + * P3.2 is SPI's MISO pin -> input, special function, default to GND + * P3.3 is SPI's CLK pin -> output, special function, default to GND + * P3.4 is USCI0 UART TX pin -> output, special function, default to Vcc + * P3.5 is USCI0 UART RX pin -> input, special function, default to Vcc + * P3.6 is USCI1 UART TX pin -> output, special function, default to GND + * P3.7 is USCI1 UART RX pin -> input, special function, default to GND + * NOTES : + * - Z1 only uses the USCI0 SPI channel + * - UART0 is connected to the micro-USB port (via the CP2102 chip) + */ + P3SEL = 0xFE; /* Port3 Select: 11111110 = 0xFE */ + P3OUT = 0x31; /* Port3 Output: 00110001 = 0x31 */ + P3DIR = 0x5B; /* Port3 Direction: 01011011 = 0x5B */ + + /* Port 4: + * P4.0 is not assigned by default (but controls a LED in Z1 "starter pack") -> output, GPIO, default to Vcc + * P4.1 receives the SFD interrupt from CC2420, that can be captured by TimerB -> input, special function, default to GND + * P4.2 is not assigned by default (but controls a LED in Z1 "starter pack") -> output, GPIO, default to Vcc + * P4.3 is not assigned by default (but controls a buzzer in Z1 "starter pack") -> output, GPIO, default to GND + * P4.4 is the Flash chip (M25P16) active-low chip select -> output, GPIO, default to Vcc + * P4.5 is the radio (CC2420) active-high VREG enable line -> output, GPIO, default to GND + * P4.6 is the radio (CC2420) active-low RESET line -> output, GPIO, default to Vcc + * P4.7 is not assigned by default (but controls a LED in Z1 "starter pack") -> output, GPIO, default to Vcc + */ + P4SEL = 0x02; /* Port4 Select: 00000010 = 0x02 */ + P4OUT = 0xD5; /* Port4 Output: 11010101 = 0xD5 */ + P4DIR = 0xFD; /* Port4 Direction: 11111101 = 0xFD */ + + /* Port 5: + * I2C, and GPIO (LEDs, flash) + * P5.0 controls TMP102 power (active high) -> output, GPIO, default to GND + * P5.1 is I2C's SDA (data) pin -> input (by default/changeable), special function, default to GND + * P5.2 is I2C's SCL (clock) pin -> output, special function, default to GND + * P5.3 is not assigned by default + * P5.4 controls one of Z1's LEDs (active low) -> output, GPIO, default to Vcc + * P5.5 controls one of Z1's LEDs (active low) -> output, GPIO, default to Vcc + * P5.6 controls one of Z1's LEDs (active low) -> output, GPIO, default to Vcc + * P5.7 is the Flash chip (M25P16) active-low HOLD line -> output, GPIO, default to Vcc + * NOTES : + * - Z1 only uses the USCI1 I2C channel + * - P5.3 controls the +5V aux. power regulator in Z1 "starter pack" + */ + P5SEL = 0x06; /* Port5 Select: 00000110 = 0x06 */ + P5OUT = 0xF0; /* Port5 Output: 11110000 = 0xF0 */ + P5DIR = 0xF5; /* Port5 Direction: 11110101 = 0xF5 */ + + /* Port 6: + * All of the 8 lines are ADC inputs, none of them is assigned by default + * (but P6.4/AD4 is connected to a wheel potentiometer in Z1 "starter pack") + * -> put all lines to input, special function, default to GND + */ + P6SEL = 0xFF; /* Port6 Select: 11111111 = 0xFF */ + P6OUT = 0x00; /* Port6 Output: 00000000 = 0x00 */ + P6DIR = 0x00; /* Port6 Direction: 00000000 = 0xFF */ + +} + +/*---------------------------------------------------------------------------*/ +/* taken from Contiki code */ +void msp430_init_dco(void) +{ +#ifdef CALIBRATE_MSP430_DCO +#define DELTA (F_CPU / (F_RC_OSCILLATOR / 8)) + /* This code taken from the FU Berlin sources and reformatted. */ + unsigned int compare, oldcapture = 0; + unsigned int i; + + /* 10100100 = XT2 is off, ACLK divided by 4, RSELx=4 */ + BCSCTL1 = XT2OFF | DIVA_3 | RSEL2; + + /* Init undivided DCO with internal resistor for MCLK and SMCLK + * DCO = 32762Hz -> FLL = 2,4576 MHz */ + BCSCTL2 = 0x00; + + BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */ + + for (i = 0xFFFF; i > 0; i--) { /* Delay for XTAL to settle */ + __nop(); + } + + CCTL2 = CCIS0 + CM0 + CAP; /* Define CCR2, CAP, ACLK */ + TACTL = TASSEL1 + TACLR + MC1; /* SMCLK, continous mode */ + + while (1) { + while ((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured!*/ + + CCTL2 &= ~CCIFG; /* Capture occured, clear flag */ + compare = CCR2; /* Get current captured SMCLK */ + compare = compare - oldcapture; /* SMCLK difference */ + oldcapture = CCR2; /* Save current captured SMCLK */ + + if (DELTA == compare) { + break; /* if equal, leave "while (1)" */ + } + else if (DELTA < compare) { /* DCO is too fast, slow it down */ + DCOCTL--; + + if (DCOCTL == 0xFF) { /* Did DCO role under? */ + BCSCTL1--; + } + } + else { /* -> Select next lower RSEL */ + DCOCTL++; + + if (DCOCTL == 0x00) { /* Did DCO role over? */ + BCSCTL1++; + } /* -> Select next higher RSEL */ + } + } + + CCTL2 = 0; /* Stop CCR2 function */ + TACTL = 0; /* Stop Timer_A */ + + BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove divisor from ACLK again */ + + /* + * On a MSP430F2617 (as on a Z1), for a 8 MHz target frequency, + * we normally obtain these values: + * DCOCTL == 0x9a (i.e.: DCOx == 4 && MODx == 26) + * [the MODx field is the most prone to variation] + * BCSCTL1 == 0x0d (i.e.: RSELx == 13) + */ +#else + /* default values for quick start-up */ + DCOCTL = 0x00; /* avoid possible temporary overclocking... */ + BCSCTL1 = 0x0d; + DCOCTL = 0x9a; +#endif + + /* Other clock configuration */ + BCSCTL1 |= XT2OFF; /* XT2 not connected on Z1 */ + BCSCTL2 = 0; /* get MCLK and SMCLK from DCO, without divisor */ + BCSCTL3 = XCAP_1; /* default value for LFXT1 capacitor and frequency */ +} + + +/* "public" specific initialization function for the Zolertia Z1 hardware */ + +void board_init(void) +{ + /* init CPU core */ + msp430_cpu_init(); + + /* disable watchdog timer */ + WDTCTL = WDTPW + WDTHOLD; + + /* init MCU pins as adequate for Z1 hardware */ + z1_ports_init(); + + /* initializes DCO */ + msp430_init_dco(); + + /* initialize UART/USB module */ + uart_init(); + + /* enable interrupts */ + __bis_SR_register(GIE); +} diff --git a/boards/z1/driver_cc2420.c b/boards/z1/driver_cc2420.c new file mode 100644 index 0000000000..fc0f550c7a --- /dev/null +++ b/boards/z1/driver_cc2420.c @@ -0,0 +1,267 @@ +/* + * driver_cc2420.c - Implementation of the board dependent cc2420 functions + * for Zolertia Z1. + * Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will + * Copyright (C) 2013 Oliver Hahm + * Copyright (C) 2014 Kévin Roussel + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup board_z1 + * @{ + * + * @file driver_cc2420.c + * @brief Board specific CC2420 driver HAL for the Zolertia Z1 + * + * @author Kévin Roussel + * + * @} + */ + +#include + +#include "board.h" +#include "cpu.h" +#include "irq.h" +#include "hwtimer.h" +#include "crash.h" + +#include "cc2420.h" +#include "cc2420_arch.h" + +#define ENABLE_DEBUG (1) +#include "debug.h" + +#define CC2420_RESETn_PIN 0x40 /* RADIO_RESET <-> P4.6 */ +#define CC2420_VREGEN_PIN 0x20 /* RADIO_VREG_EN <-> P4.5 */ + +#define CC2420_FIFOP_PIN 0x04 +#define CC2420_GIO0_PIN 0x08 +#define CC2420_GIO1_PIN 0x10 + +#define CC2420_SFD_PIN 0x02 + +#define CC2420_FIFOP (P1IN & CC2420_FIFOP_PIN) /* FIFOP <-> packet interrupt (P1.2) */ +#define CC2420_GIO0 (P1IN & CC2420_GIO0_PIN) /* FIFO <-> GIO0 - RX data available (P1.3) */ +#define CC2420_GIO1 (P1IN & CC2420_GIO1_PIN) /* CCA <-> GIO1 - clear channel (P1.4) */ +#define CC2420_SFD (P4IN & CC2420_SFD_PIN) /* SFD <-> TBL - start frame delimiter (P4.1) */ + +#define CC2420_CS_LOW (P3OUT &= ~0x01) /* RADIO_CS <-> P3.0 */ +#define CC2420_CS_HIGH (P3OUT |= 0x01) + +volatile int abort_count; +volatile int retry_count = 0; + +void cc2420_reset(void) +{ + P4OUT |= CC2420_VREGEN_PIN; + P4OUT &= ~CC2420_RESETn_PIN; + hwtimer_wait(500); + P4OUT |= CC2420_RESETn_PIN; +} + +void cc2420_gio0_enable(void) +{ + P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */ + P1IE |= CC2420_GIO0_PIN; /* Enable interrupt for GIO0 */ +} + +void cc2420_gio0_disable(void) +{ + P1IE &= ~CC2420_GIO0_PIN; /* Disable interrupt for GIO0 */ + P1IFG &= ~CC2420_GIO0_PIN; /* Clear IFG for GIO0 */ +} + +void cc2420_gio1_enable(void) +{ + P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */ + P1IE |= CC2420_GIO1_PIN; /* Enable interrupt for GIO1 */ +} + +void cc2420_gio1_disable(void) +{ + P1IE &= ~CC2420_GIO1_PIN; /* Disable interrupt for GIO1 */ + P1IFG &= ~CC2420_GIO1_PIN; /* Clear IFG for GIO1 */ +} + +void cc2420_before_send(void) +{ + /* Disable SFD interrupt before sending packet */ + /* However there is no interrupt on MSP430F2617 port 4 */ +} + +void cc2420_after_send(void) +{ + /* Enable SFD interrupt after sending packet */ + /* However there is no interrupt on MSP430F2617 port 4 */ +} + + +int cc2420_get_gio0(void) +{ + return CC2420_GIO0; +} + +int cc2420_get_gio1(void) +{ + return CC2420_GIO1; +} + +int cc2420_get_fifop(void) +{ + return CC2420_FIFOP; +} + +uint8_t cc2420_get_sfd(void) +{ + return CC2420_SFD; +} + +#define MAX_RSSI_WAIT 1000 + +uint8_t cc2420_get_cca(void) +{ + uint8_t status; + long count = 0; + do { + status = cc2420_txrx(NOBYTE); + count++; + if (count >= MAX_RSSI_WAIT) { + core_panic(0x2420, "cc2420_get_cca(): RSSI never valid!"); + } + } while (!(status & CC2420_STATUS_RSSI_VALID)); + return CC2420_GIO1; +} + +void cc2420_spi_cs(void) +{ + CC2420_CS_LOW; /* Chip Select line is active-low */ +} + +#define MAX_SPI_WAIT 1000 + +uint8_t cc2420_txrx(uint8_t data) +{ + /* Wait for SPI to be ready for transmission */ + long count = 0; + do { + count++; + if (count >= MAX_SPI_WAIT) { + core_panic(0x2420, "cc2420_txrx(): SPI never ready for TX!"); + } + } while (!(IFG2 & UCB0TXIFG)); + /* Transmit data byte to CC2420, and wait for end of transmission */ + IFG2 &= ~UCB0RXIFG; + UCB0TXBUF = data; + count = 0; + do { + count++; + if (count >= MAX_SPI_WAIT) { + core_panic(0x2420, "cc2420_txrx(): couldn't send byte!"); + } + } while(!(UCB0STAT & UCBUSY)); + /* Read the byte that CC2420 has (normally, during TX) returned */ + count = 0; + do { + count++; + if (count >= MAX_SPI_WAIT) { + core_panic(0x2420, "cc2420_txrx(): couldn't receive byte!"); + } + } while(!(IFG2 & UCB0RXIFG)); + /* Return received byte */ + return UCB0RXBUF; +} + + +void cc2420_spi_select(void) +{ + CC2420_CS_LOW; +} + +void cc2420_spi_unselect(void) { + CC2420_CS_HIGH; +} + +void cc2420_init_interrupts(void) +{ + unsigned int state = disableIRQ(); /* Disable all interrupts */ + + /* done in board.c : function z1_ports_init() + P1SEL &= ~CC2420_FIFOP_PIN; // must be <> 1 to use interrupts + P1SEL &= ~CC2420_GIO0_PIN; // must be <> 1 to use interrupts + */ + + /* FIFO <-> GIO0 interrupt */ + P1IES |= CC2420_GIO0_PIN; /* Enable external interrupt on falling edge for GIO0/FIFO */ + P1IE |= CC2420_GIO0_PIN; + P1IFG &= ~CC2420_GIO0_PIN; /* Clear the interrupt flag */ + + /* FIFOP <-> Packet interrupt */ + P1IES &= ~CC2420_FIFOP_PIN; /* Enable external interrupt on rising edge for FIFOP */ + P1IE |= CC2420_FIFOP_PIN; + P1IFG &= ~CC2420_FIFOP_PIN; /* Clear IFG for FIFOP */ + + restoreIRQ(state); /* Enable all interrupts */ +} + +void cc2420_spi_init(void) +{ + /* + * NOTES : + * - we will use SPI mode using block B of the USCI0, + * so as to avoid disturbing UART0 which is managed by USCI0 block A + * - MCU pin (GPIO port) initialisation is done in board.c, + * function z1_ports_init(). + */ + + /* Keep peripheral in reset state during configuration */ + UCB0CTL1 = UCSWRST; + + /* 8-bit SPI Master 3-pin mode, MSB first, + with SMCLK as clock source */ + UCB0CTL0 = UCSYNC + UCMST + UCMODE_0 + UCMSB; + UCB0CTL1 |= UCSSEL_3; + + UCB0CTL0 |= UCCKPH; /* Data captured on rising edge, changed on falling */ + UCB0CTL0 &= ~UCCKPL; /* SPI data lines are active-high/inactive-low */ + + /* Ignore clockrate argument for now, just use clock source/2 */ + UCB0BR0 = 0x02; /* Ensure baud rate <= SMCLK/2 */ + UCB0BR1 = 0x00; + + /* Release for operation */ + UCB0CTL1 &= ~UCSWRST; +} + +/* + * CC2400 receive interrupt + */ +interrupt (PORT1_VECTOR) __attribute__ ((naked)) cc2420_isr(void) +{ + __enter_isr(); + + /* Check if FIFOP signal is raising => RX interrupt */ + if ((P1IFG & CC2420_FIFOP_PIN) != 0) { + P1IFG &= ~CC2420_FIFOP_PIN; + cc2420_rx_irq(); + DEBUG("rx interrupt"); + } + /* GIO0 is falling => check if FIFOP is high, indicating an RXFIFO overflow */ + else if ((P1IFG & CC2420_GIO0_PIN) != 0) { + P1IFG &= ~CC2420_GIO0_PIN; + if (cc2420_get_fifop()) { + cc2420_rxoverflow_irq(); + DEBUG("[CC2420] rxfifo overflow"); + } + } + else { + puts("cc2420_isr(): unexpected IFG!"); + /* Should not occur - only FIFOP and GIO0 interrupts are enabled */ + } + + __exit_isr(); +} diff --git a/boards/z1/include/board-conf.h b/boards/z1/include/board-conf.h new file mode 100644 index 0000000000..0ca7b7110d --- /dev/null +++ b/boards/z1/include/board-conf.h @@ -0,0 +1,29 @@ +/* + * board-conf.h. + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License. See the file LICENSE in the top level directory for more + * details. + */ + +#ifndef BOARD_CONF_H +#define BOARD_CONF_H + +/** + * @ingroup board_z1 + * + * @{ + */ + +/** + * @file + * @brief Zolertia Z1 board configuration macros + * + * @author Kévin Roussel + * + */ + +#define INFOMEM (0x1000) + +/** @} */ +#endif /* BOARD-CONF_H */ diff --git a/boards/z1/include/board.h b/boards/z1/include/board.h new file mode 100644 index 0000000000..53fe9f43f0 --- /dev/null +++ b/boards/z1/include/board.h @@ -0,0 +1,77 @@ +/* + * board.h - Zolertia Z1 Board. + * Copyright (C) 2014 INRIA + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License. See the file LICENSE in the top level directory for more + * details. + */ + +#ifndef _Z1_BOARD_H +#define _Z1_BOARD_H + +/** + * @defgroup board_z1 + * @ingroup board_z1 + * +

Components

+\li MSP430F2617 +\li CC2420 + +* @{ +*/ + +/** + * @file + * @brief Zolertia Z1 board configuration + * + * @author Kévin Roussel + * + */ + +#include + +#ifndef __MSP430F2617__ +#define __MSP430F2617__ +#endif + +// MSP430 core +#define MSP430_INITIAL_CPU_SPEED 8000000uL +#ifndef F_CPU +#define F_CPU MSP430_INITIAL_CPU_SPEED +#endif +#define F_RC_OSCILLATOR 32768 +#define MSP430_HAS_DCOR 0 +#define MSP430_HAS_EXTERNAL_CRYSTAL 1 + +// LEDs ports +#define LEDS_PxDIR P5DIR +#define LEDS_PxOUT P5OUT +#define LEDS_CONF_RED 0x10 +#define LEDS_CONF_BLUE 0x20 +#define LEDS_CONF_GREEN 0x40 + +#define LED_RED_ON LEDS_PxOUT &=~LEDS_CONF_RED +#define LED_RED_OFF LEDS_PxOUT |= LEDS_CONF_RED +#define LED_RED_TOGGLE LEDS_PxOUT ^= LEDS_CONF_RED + +#define LED_GREEN_ON LEDS_PxOUT &=~LEDS_CONF_GREEN +#define LED_GREEN_OFF LEDS_PxOUT |= LEDS_CONF_GREEN +#define LED_GREEN_TOGGLE LEDS_PxOUT ^= LEDS_CONF_GREEN + +#define LED_BLUE_ON LEDS_PxOUT &=~LEDS_CONF_BLUE +#define LED_BLUE_OFF LEDS_PxOUT |= LEDS_CONF_BLUE +#define LED_BLUE_TOGGLE LEDS_PxOUT ^= LEDS_CONF_BLUE + + +// User-button port +#define USER_BTN_PxIN P2IN +#define USER_BTN_MASK 0x20 + +#define USER_BTN_PRESSED ((USER_BTN_PxIN & USER_BTN_MASK) == 0) +#define USER_BTN_RELEASED ((USER_BTN_PxIN & USER_BTN_MASK) != 0) + +typedef uint8_t radio_packet_length_t; + +/** @} */ +#endif // _Z1_BOARD_H diff --git a/boards/z1/uart.c b/boards/z1/uart.c new file mode 100644 index 0000000000..e84aff893d --- /dev/null +++ b/boards/z1/uart.c @@ -0,0 +1,134 @@ +/* + * uart.c - Implementation for the Zolertia Z1 UART + * Copyright (C) 2014 INRIA + * + * Author : Kevin Roussel + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup board_z1 + * @{ + * + * @file uart.c + * @brief Board specific UART/USB driver HAL for the Zolertia Z1 + * + * @author Kévin Roussel + * + * @} + */ + +#include +#include +#include "cpu.h" +#include "board.h" +#include "kernel.h" +#include "irq.h" +#include "board_uart0.h" + + +#define BAUDRATE (115200ul) + +#define BAUD_RATE_MAJOR (int)(MSP430_INITIAL_CPU_SPEED / BAUDRATE) +#define BAUD_RATE_MINOR (int)(((MSP430_INITIAL_CPU_SPEED / BAUDRATE) - BAUD_RATE_MAJOR) * 8) + + +void uart_init(void) +{ + /* + * NOTE : MCU pin (GPIO port) initialisation is done + * in board.c, function z1_ports_init(). + */ + UCA0CTL1 = UCSWRST; /* hold UART module in reset state + while we configure it */ + + UCA0CTL1 |= UCSSEL_2; /* source UART's BRCLK from 8 MHz SMCLK */ + UCA0MCTL = UCBRS1 + UCBRS0; /* low-frequency baud rate generation, + modulation type 4 */ + + /* 115200 baud, divided from 8 MHz == 69 */ + UCA0BR0 = BAUD_RATE_MAJOR; + UCA0BR1 = BAUD_RATE_MINOR; + + /* remaining registers : set to default */ + UCA0CTL0 = 0x00; /* put in asynchronous (== UART) mode, LSB first */ + UCA0STAT = 0x00; /* reset status flags */ + + /* clear UART-related interrupt flags */ + IFG2 &= ~(UCA0RXIFG | UCA0TXIFG); + + /* configuration done, release reset bit => start UART */ + UCA0CTL1 &= ~UCSWRST; + + /* enable UART0 RX interrupt, disable UART0 TX interrupt */ + IE2 |= UCA0RXIE; + IE2 &= ~UCA0TXIE; +} + +int putchar(int c) +{ + unsigned sr = disableIRQ(); + + /* the LF endline character needs to be "doubled" into CR+LF */ + if (c == '\n') { + putchar('\r'); + } + /* wait for a previous transmission to end */ + while ((IFG2 & UCA0TXIFG) == 0) { + __asm__("nop"); + } + /* load TX byte buffer */ + UCA0TXBUF = (uint8_t) c; + + restoreIRQ(sr); + return c; +} + +uint8_t uart_readByte(void) +{ + return UCA0RXBUF; +} + +/** + * \brief the interrupt handler for UART reception + */ +interrupt(USCIAB0RX_VECTOR) __attribute__ ((naked)) usart1irq(void) +{ + __enter_isr(); + +#ifndef MODULE_UART0 + int __attribute__ ((unused)) c; +#else + int c; +#endif + + /* Check status register for receive errors. */ + if (UCA0STAT & UCRXERR) { + if (UCA0STAT & UCFE) { + puts("UART RX framing error"); + } + if (UCA0STAT & UCOE) { + puts("UART RX overrun error"); + } + if (UCA0STAT & UCPE) { + puts("UART RX parity error"); + } + if (UCA0STAT & UCBRK) { + puts("UART RX break condition -> error"); + } + /* Clear error flags by forcing a dummy read. */ + c = UCA0RXBUF; +#ifdef MODULE_UART0 + } else if (uart0_handler_pid) { + /* All went well -> let's signal the reception to adequate callbacks */ + c = UCA0RXBUF; + uart0_handle_incoming(c); + uart0_notify_thread(); +#endif + } + + __exit_isr(); +} diff --git a/examples/ccn-lite-client/Makefile b/examples/ccn-lite-client/Makefile index 72807e7f60..af7720508a 100644 --- a/examples/ccn-lite-client/Makefile +++ b/examples/ccn-lite-client/Makefile @@ -27,17 +27,18 @@ export RIOTBASE ?= $(CURDIR)/../.. # Change this to 0 show compiler invocation lines by default: export QUIET ?= 1 -BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ - telosb wsn430-v1_3b wsn430-v1_4 pttu arduino-due udoo +BOARD_BLACKLIST := arduino-due chronos mbed_lpc1768 msb-430 msb-430h pttu \ + redbee-econotag telosb udoo wsn430-v1_3b wsn430-v1_4 z1 # chronos: not enough RAM # mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675 # msb-430: see https://github.com/RIOT-OS/RIOT/issues/658 # msb-430h: not enough RAM +# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 # redbee-econotag: see https://github.com/RIOT-OS/RIOT/issues/676 # telosb: not enough RAM # wsn430-v1_3b: not enough RAM # wsn430-v1_4: not enough RAM -# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 +# z1: lacks RTC features # Modules to include: diff --git a/examples/ccn-lite-relay/Makefile b/examples/ccn-lite-relay/Makefile index ef547b9a7a..2a26611304 100644 --- a/examples/ccn-lite-relay/Makefile +++ b/examples/ccn-lite-relay/Makefile @@ -27,17 +27,18 @@ export RIOTBASE ?= $(CURDIR)/../.. # Change this to 0 show compiler invocation lines by default: export QUIET ?= 1 -BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ - telosb wsn430-v1_3b wsn430-v1_4 pttu arduino-due udoo +BOARD_BLACKLIST := arduino-due chronos mbed_lpc1768 msb-430 msb-430h \ + pttu redbee-econotag telosb udoo wsn430-v1_3b wsn430-v1_4 z1 # chronos: not enough RAM # mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675 # msb-430: see https://github.com/RIOT-OS/RIOT/issues/658 # msb-430h: not enough RAM +# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 # redbee-econotag: see https://github.com/RIOT-OS/RIOT/issues/676 # telosb: not enough RAM # wsn430-v1_3b: not enough RAM # wsn430-v1_4: not enough RAM -# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 +# z1: lacks RTC features # Modules to include: diff --git a/examples/rpl_udp/Makefile b/examples/rpl_udp/Makefile index 203f9fa2a0..90ece78634 100644 --- a/examples/rpl_udp/Makefile +++ b/examples/rpl_udp/Makefile @@ -34,17 +34,18 @@ ifeq ($(shell $(CC) -Wno-cpp -E - 2>/dev/null >/dev/null dev/null ; echo $$?),0) endif endif -BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ - telosb wsn430-v1_3b wsn430-v1_4 pttu arduino-due udoo +BOARD_BLACKLIST := arduino-due chronos mbed_lpc1768 msb-430 msb-430h \ + pttu redbee-econotag telosb udoo wsn430-v1_3b wsn430-v1_4 z1 # chronos: not enough RAM # mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675 # msb-430: see https://github.com/RIOT-OS/RIOT/issues/658 # msb-430h: not enough RAM +# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 # redbee-econotag: not enough RAM # telosb: not enough RAM # wsn430-v1_3b: not enough RAM # wsn430-v1_4: not enough RAM -# pttu: see https://github.com/RIOT-OS/RIOT/issues/659 +# z1: not enough RAM # Modules to include: diff --git a/tests/test_bloom/Makefile b/tests/test_bloom/Makefile index c686ae2615..3ee58e7e94 100644 --- a/tests/test_bloom/Makefile +++ b/tests/test_bloom/Makefile @@ -2,7 +2,7 @@ export PROJECT = test_bloom include ../Makefile.tests_common BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ - telosb wsn430-v1_3b wsn430-v1_4 + telosb wsn430-v1_3b wsn430-v1_4 z1 # chronos: not enough RAM # mbed_lpc1768: not enough RAM # msb-430: not enough RAM @@ -11,6 +11,7 @@ BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ # telosb: not enough RAM # wsn430-v1_3b: not enough RAM # wsn430-v1_4: not enough RAM +# z1: not enough RAM USEMODULE += hashes USEMODULE += bloom diff --git a/tests/test_bloom_bytes/Makefile b/tests/test_bloom_bytes/Makefile index 2b23b59c05..2bec299397 100644 --- a/tests/test_bloom_bytes/Makefile +++ b/tests/test_bloom_bytes/Makefile @@ -2,13 +2,14 @@ export PROJECT = test_bloom include ../Makefile.tests_common BOARD_BLACKLIST := chronos msb-430 msb-430h \ - telosb wsn430-v1_3b wsn430-v1_4 + telosb wsn430-v1_3b wsn430-v1_4 z1 # chronos: https://github.com/RIOT-OS/RIOT/issues/1061 # msb-430: https://github.com/RIOT-OS/RIOT/issues/1061 # msb-430h: https://github.com/RIOT-OS/RIOT/issues/1061 # telosb: https://github.com/RIOT-OS/RIOT/issues/1061 # wsn430-v1_3b: https://github.com/RIOT-OS/RIOT/issues/1061 # wsn430-v1_4: https://github.com/RIOT-OS/RIOT/issues/1061 +# z1: https://github.com/RIOT-OS/RIOT/issues/1061 USEMODULE += hashes USEMODULE += bloom diff --git a/tests/test_pnet/Makefile b/tests/test_pnet/Makefile index c94edb7f68..d30e961db3 100644 --- a/tests/test_pnet/Makefile +++ b/tests/test_pnet/Makefile @@ -1,8 +1,8 @@ export PROJECT = test_pnet include ../Makefile.tests_common -BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ - telosb wsn430-v1_3b wsn430-v1_4 arduino-due udoo +BOARD_BLACKLIST := arduino-due chronos mbed_lpc1768 msb-430 msb-430h \ + redbee-econotag telosb udoo wsn430-v1_3b wsn430-v1_4 z1 # chronos: not enough RAM # mbed_lpc1768: see https://github.com/RIOT-OS/RIOT/issues/675 # msb-430: see https://github.com/RIOT-OS/RIOT/issues/658 @@ -11,6 +11,7 @@ BOARD_BLACKLIST := chronos mbed_lpc1768 msb-430 msb-430h redbee-econotag \ # telosb: not enough RAM # wsn430-v1_3b: not enough RAM # wsn430-v1_4: not enough RAM +# z1: not enough RAM USEMODULE += posix USEMODULE += pnet