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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #5499 from kaspar030/minor_compile_fixes
cpu: samd21: misc compile fixes
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commit
274ab1cd66
@ -46,7 +46,7 @@ void cortexm_init(void)
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/* set SVC interrupt to same priority as the rest */
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NVIC_SetPriority(SVCall_IRQn, CPU_DEFAULT_IRQ_PRIO);
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/* initialize all vendor specific interrupts with the same value */
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for (int i = 0; i < (int)CPU_IRQ_NUMOF; i++) {
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for (unsigned i = 0; i < CPU_IRQ_NUMOF; i++) {
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NVIC_SetPriority((IRQn_Type) i, CPU_DEFAULT_IRQ_PRIO);
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}
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@ -34,6 +34,14 @@ extern "C" {
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*/
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#define ISR_VECTORS __attribute__((used,section(".vectors")))
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/**
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* @brief Number of Cortex-M non-ISR exceptions
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*
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* This means those that are no hardware interrupts, or the ones with a
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* negative interrupt number.
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*/
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#define CPU_NONISR_EXCEPTIONS (15)
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/**
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* @brief This function is the default entry point after a system reset
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*
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@ -212,7 +212,7 @@ void gpio_write(gpio_t pin, int value)
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void isr_eic(void)
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{
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for (int i = 0; i < NUMOF_IRQS; i++) {
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for (unsigned i = 0; i < NUMOF_IRQS; i++) {
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if (EIC->INTFLAG.reg & (1 << i)) {
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EIC->INTFLAG.reg = (1 << i);
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if(EIC->INTENSET.reg & (1 << i)) {
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@ -208,13 +208,20 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
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int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
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{
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(void)dev;
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(void)conf;
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(void)cb;
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/* TODO */
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assert(false);
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return -1;
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}
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void spi_transmission_begin(spi_t dev, char reset_val)
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{
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/* TODO*/
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(void)dev;
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(void)reset_val;
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/* TODO */
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assert(false);
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}
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int spi_acquire(spi_t dev)
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@ -20,6 +20,8 @@
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*/
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#include <stdint.h>
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#include "cpu_conf.h"
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#include "vectors_cortexm.h"
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/* get the start of the ISR stack as defined in the linkerscript */
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@ -66,54 +68,59 @@ WEAK_DEFAULT void isr_ptc(void);
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WEAK_DEFAULT void isr_i2c(void);
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/* interrupt vector table */
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ISR_VECTORS const void *interrupt_vector[] = {
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ISR_VECTORS struct {
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void* _estack;
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void(*vectors[CPU_IRQ_NUMOF + CPU_NONISR_EXCEPTIONS])(void);
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} interrupt_vector = {
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/* Exception stack pointer */
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(void*) (&_estack), /* pointer to the top of the stack */
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&_estack, /* pointer to the top of the stack */
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{
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/* Cortex-M0+ handlers */
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(void*) reset_handler_default, /* entry point of the program */
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(void*) nmi_default, /* non maskable interrupt handler */
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(void*) hard_fault_default, /* hard fault exception */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) isr_svc, /* system call interrupt, in RIOT used for
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reset_handler_default, /* entry point of the program */
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nmi_default, /* non maskable interrupt handler */
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hard_fault_default, /* hard fault exception */
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(0UL), /* reserved */
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(0UL), /* reserved */
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(0UL), /* reserved */
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(0UL), /* reserved */
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(0UL), /* reserved */
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(0UL), /* reserved */
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(0UL), /* reserved */
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isr_svc, /* system call interrupt, in RIOT used for
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* switching into thread context on boot */
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(void*) (0UL), /* reserved */
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(void*) (0UL), /* reserved */
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(void*) isr_pendsv, /* pendSV interrupt, in RIOT the actual
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(0UL), /* reserved */
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(0UL), /* reserved */
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isr_pendsv, /* pendSV interrupt, in RIOT the actual
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* context switching is happening here */
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(void*) isr_systick, /* SysTick interrupt, not used in RIOT */
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isr_systick, /* SysTick interrupt, not used in RIOT */
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/* Atmel specific peripheral handlers */
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(void*) isr_pm, /* 0 Power Manager */
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(void*) isr_sysctrl, /* 1 System Control */
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(void*) isr_wdt, /* 2 Watchdog Timer */
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(void*) isr_rtc, /* 3 Real-Time Counter */
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(void*) isr_eic, /* 4 External Interrupt Controller */
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(void*) isr_nvmctrl, /* 5 Non-Volatile Memory Controller */
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(void*) isr_dmac, /* 6 Direct Memory Access Controller */
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(void*) isr_usb, /* 7 Universal Serial Bus */
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(void*) isr_evsys, /* 8 Event System Interface */
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(void*) isr_sercom0, /* 9 Serial Communication Interface 0 */
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(void*) isr_sercom1, /* 10 Serial Communication Interface 1 */
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(void*) isr_sercom2, /* 11 Serial Communication Interface 2 */
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(void*) isr_sercom3, /* 12 Serial Communication Interface 3 */
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(void*) isr_sercom4, /* 13 Serial Communication Interface 4 */
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(void*) isr_sercom5, /* 14 Serial Communication Interface 5 */
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(void*) isr_tcc0, /* 15 Timer Counter Control 0 */
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(void*) isr_tcc1, /* 16 Timer Counter Control 1 */
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(void*) isr_tcc2, /* 17 Timer Counter Control 2 */
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(void*) isr_tc3, /* 18 Basic Timer Counter 0 */
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(void*) isr_tc4, /* 19 Basic Timer Counter 1 */
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(void*) isr_tc5, /* 20 Basic Timer Counter 2 */
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(void*) isr_tc6, /* 21 Basic Timer Counter 3 */
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(void*) isr_tc7, /* 22 Basic Timer Counter 4 */
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(void*) isr_adc, /* 23 Analog Digital Converter */
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(void*) isr_ac, /* 24 Analog Comparators */
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(void*) isr_dac, /* 25 Digital Analog Converter */
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(void*) isr_ptc, /* 26 Peripheral Touch Controller */
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(void*) isr_i2c /* 27 Inter-IC Sound Interface */
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isr_pm, /* 0 Power Manager */
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isr_sysctrl, /* 1 System Control */
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isr_wdt, /* 2 Watchdog Timer */
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isr_rtc, /* 3 Real-Time Counter */
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isr_eic, /* 4 External Interrupt Controller */
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isr_nvmctrl, /* 5 Non-Volatile Memory Controller */
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isr_dmac, /* 6 Direct Memory Access Controller */
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isr_usb, /* 7 Universal Serial Bus */
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isr_evsys, /* 8 Event System Interface */
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isr_sercom0, /* 9 Serial Communication Interface 0 */
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isr_sercom1, /* 10 Serial Communication Interface 1 */
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isr_sercom2, /* 11 Serial Communication Interface 2 */
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isr_sercom3, /* 12 Serial Communication Interface 3 */
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isr_sercom4, /* 13 Serial Communication Interface 4 */
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isr_sercom5, /* 14 Serial Communication Interface 5 */
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isr_tcc0, /* 15 Timer Counter Control 0 */
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isr_tcc1, /* 16 Timer Counter Control 1 */
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isr_tcc2, /* 17 Timer Counter Control 2 */
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isr_tc3, /* 18 Basic Timer Counter 0 */
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isr_tc4, /* 19 Basic Timer Counter 1 */
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isr_tc5, /* 20 Basic Timer Counter 2 */
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isr_tc6, /* 21 Basic Timer Counter 3 */
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isr_tc7, /* 22 Basic Timer Counter 4 */
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isr_adc, /* 23 Analog Digital Converter */
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isr_ac, /* 24 Analog Comparators */
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isr_dac, /* 25 Digital Analog Converter */
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isr_ptc, /* 26 Peripheral Touch Controller */
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isr_i2c /* 27 Inter-IC Sound Interface */
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}
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};
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