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nvram_spi: Implement generic SPI NVRAM driver.
This commit is contained in:
Joakim Gebart
parent
db9d3ddf48
commit
2738e9f9a8
3
drivers/nvram_spi/Makefile
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drivers/nvram_spi/Makefile
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MODULE = nvram_spi
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include $(RIOTBASE)/Makefile.base
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283
drivers/nvram_spi/nvram-spi.c
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283
drivers/nvram_spi/nvram-spi.c
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/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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#include <stdint.h>
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#include <stddef.h>
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#include "nvram.h"
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#include "nvram-spi.h"
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#include "byteorder.h"
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#include "periph/spi.h"
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#include "periph/gpio.h"
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#include "hwtimer.h"
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/**
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* @ingroup nvram
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* @{
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*
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* @file
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*
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* @brief Device interface for various SPI connected NVRAM.
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*
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* Tested on:
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* - Cypress/Ramtron FM25L04B.
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*
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*/
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typedef enum {
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/** WRITE command byte, 0b0000 0010 */
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NVRAM_SPI_CMD_WRITE = 0x02,
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/** READ command byte, 0b0000 0011 */
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NVRAM_SPI_CMD_READ = 0x03,
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/** WREN command byte, 0b0000 0110 */
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NVRAM_SPI_CMD_WREN = 0x06,
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} nvram_spi_commands_t;
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/** @brief Delay to wait between toggling CS pin, on most chips this can probably be
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* removed. */
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#define NVRAM_SPI_CS_TOGGLE_TICKS 1
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/**
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* @brief Copy data from system memory to NVRAM.
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*
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* @param[in] dev Pointer to NVRAM device descriptor
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* @param[in] src Pointer to the first byte in the system memory address space
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* @param[in] dst Starting address in the NVRAM device address space
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* @param[in] len Number of bytes to copy
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*
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* @return Number of bytes written on success
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* @return <0 on errors
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*/
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static int nvram_spi_write(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len);
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/**
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* @brief Copy data from NVRAM to system memory.
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*
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* @param[in] dev Pointer to NVRAM device descriptor
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* @param[out] dst Pointer to the first byte in the system memory address space
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* @param[in] src Starting address in the NVRAM device address space
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* @param[in] len Number of bytes to copy
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*
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* @return Number of bytes read on success
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* @return <0 on errors
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*/
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static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len);
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/**
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* @brief Copy data from system memory to NVRAM.
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*
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* This is a special form of the WRITE command used by some Ramtron/Cypress
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* 4Kbit FRAM devices which puts the 9th address bit inside the command byte to
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* be able to use one byte for addressing instead of two.
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*
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* @param[in] dev Pointer to NVRAM device descriptor
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* @param[in] src Pointer to the first byte in the system memory address space
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* @param[in] dst Starting address in the NVRAM device address space
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* @param[in] len Number of bytes to copy
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*
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* @return Number of bytes written on success
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* @return <0 on errors
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*/
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static int nvram_spi_write_9bit_addr(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len);
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/**
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* @brief Copy data from NVRAM to system memory.
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*
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* This is a special form of the READ command used by some Ramtron/Cypress 4Kbit
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* FRAM devices which puts the 9th address bit inside the command byte to be
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* able to use one byte for addressing instead of two.
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*
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* @param[in] dev Pointer to NVRAM device descriptor
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* @param[out] dst Pointer to the first byte in the system memory address space
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* @param[in] src Starting address in the NVRAM device address space
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* @param[in] len Number of bytes to copy
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*
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* @return Number of bytes read on success
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* @return <0 on errors
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*/
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static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len);
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int nvram_spi_init(nvram_t *dev, nvram_spi_params_t *spi_params, size_t size)
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{
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dev->size = size;
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if (size > 0x100 && spi_params->address_count == 1) {
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dev->write = nvram_spi_write_9bit_addr;
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dev->read = nvram_spi_read_9bit_addr;
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} else {
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dev->write = nvram_spi_write;
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dev->read = nvram_spi_read;
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}
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dev->extra = spi_params;
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gpio_init_out(spi_params->cs, GPIO_NOPULL);
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gpio_set(spi_params->cs);
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return 0;
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}
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static int nvram_spi_write(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
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{
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nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
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int status;
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union {
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uint32_t u32;
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char c[4];
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} addr;
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/* Address is expected by the device as big-endian, i.e. network byte order,
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* we utilize the network byte order macros here. */
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addr.u32 = HTONL(dst);
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/* Acquire exclusive bus access */
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spi_acquire(spi_dev->spi);
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/* Assert CS */
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gpio_clear(spi_dev->cs);
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/* Enable writes */
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status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
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if (status < 0)
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{
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return status;
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}
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/* Release CS */
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gpio_set(spi_dev->cs);
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hwtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
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/* Re-assert CS */
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gpio_clear(spi_dev->cs);
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/* Write command and address */
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status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_WRITE,
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&addr.c[sizeof(addr.c) - spi_dev->address_count], NULL,
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spi_dev->address_count);
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if (status < 0)
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{
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return status;
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}
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/* Keep holding CS and write data */
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status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
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if (status < 0)
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{
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return status;
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}
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/* Release CS */
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gpio_set(spi_dev->cs);
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/* Release exclusive bus access */
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spi_release(spi_dev->spi);
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return status;
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}
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static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
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{
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nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
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int status;
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union {
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uint32_t u32;
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char c[4];
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} addr;
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/* Address is expected by the device as big-endian, i.e. network byte order,
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* we utilize the network byte order macros here. */
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addr.u32 = HTONL(src);
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/* Acquire exclusive bus access */
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spi_acquire(spi_dev->spi);
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/* Assert CS */
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gpio_clear(spi_dev->cs);
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/* Write command and address */
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status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_READ,
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&addr.c[sizeof(addr.c) - spi_dev->address_count],
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NULL, spi_dev->address_count);
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if (status < 0)
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{
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return status;
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}
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/* Keep holding CS and read data */
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status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
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if (status < 0)
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{
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return status;
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}
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/* Release CS */
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gpio_set(spi_dev->cs);
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/* Release exclusive bus access */
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spi_release(spi_dev->spi);
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/* status contains the number of bytes actually read from the SPI bus. */
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return status;
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}
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static int nvram_spi_write_9bit_addr(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
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{
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nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
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int status;
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uint8_t cmd;
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uint8_t addr;
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cmd = NVRAM_SPI_CMD_WRITE;
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/* The upper address bit is mixed into the command byte on certain devices,
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* probably just to save a byte in the SPI transfer protocol. */
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if (dst > 0xff) {
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cmd |= 0x08;
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}
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/* LSB of address */
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addr = (dst & 0xff);
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spi_acquire(spi_dev->spi);
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gpio_clear(spi_dev->cs);
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/* Enable writes */
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status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
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if (status < 0)
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{
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return status;
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}
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gpio_set(spi_dev->cs);
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hwtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
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gpio_clear(spi_dev->cs);
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/* Write command and address */
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status = spi_transfer_reg(spi_dev->spi, cmd, addr, NULL);
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if (status < 0)
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{
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return status;
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}
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/* Keep holding CS and write data */
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status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
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if (status < 0)
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{
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return status;
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}
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gpio_set(spi_dev->cs);
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spi_release(spi_dev->spi);
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/* status contains the number of bytes actually written to the SPI bus. */
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return status;
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}
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static int nvram_spi_read_9bit_addr(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
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{
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nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
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int status;
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uint8_t cmd;
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uint8_t addr;
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cmd = NVRAM_SPI_CMD_READ;
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/* The upper address bit is mixed into the command byte on certain devices,
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* probably just to save a byte in the SPI transfer protocol. */
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if (src > 0xff) {
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cmd |= 0x08;
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}
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/* LSB of address */
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addr = (src & 0xff);
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spi_acquire(spi_dev->spi);
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gpio_clear(spi_dev->cs);
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/* Write command and address */
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status = spi_transfer_reg(spi_dev->spi, (char)cmd, addr, NULL);
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if (status < 0)
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{
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return status;
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}
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/* Keep holding CS and read data */
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status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
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if (status < 0)
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{
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return status;
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}
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gpio_set(spi_dev->cs);
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spi_release(spi_dev->spi);
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/* status contains the number of bytes actually read from the SPI bus. */
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return status;
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}
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