mirror of
https://github.com/RIOT-OS/RIOT.git
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boards/weact-f411ce: add WeAct-f411ce
This commit is contained in:
Benjamin Valentin
parent
e200d009ad
commit
26a907576c
@ -1,4 +1,4 @@
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# Copyright (c) 2020 Inria
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# Copyright (c) 2020 Benjamin Valentin
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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@ -11,17 +11,7 @@ config BOARD
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config BOARD_WEACT_F411CE
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bool
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default y
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select BOARD_COMMON_WEACT_F41XCX
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select CPU_MODEL_STM32F411CE
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# Put defined MCU peripherals here (in alphabetical order)
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select HAS_PERIPH_ADC
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select HAS_PERIPH_I2C
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select HAS_PERIPH_PWM
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select HAS_PERIPH_RTC
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select HAS_PERIPH_SPI
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_UART
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select HAS_PERIPH_USBDEV
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# Put other features for this board (in alphabetical order)
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select HAS_HIGHLEVEL_STDIO
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source "$(RIOTBOARD)/common/weact-f4x1cx/Kconfig"
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@ -1,3 +1,5 @@
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MODULE = board
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DIRS = $(RIOTBOARD)/common/weact-f4x1cx
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include $(RIOTBASE)/Makefile.base
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@ -1,15 +1,3 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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USEMODULE += boards_common_weact-f4x1cx
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include $(RIOTBOARD)/common/makefiles/stdio_cdc_acm.dep.mk
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ifneq (,$(filter stdio_cdc_acm,$(USEMODULE)))
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# The Mask-ROM bootloader provides USB-DFU capability
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FEATURES_REQUIRED += bootloader_stm32
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USEMODULE += usb_board_reset
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endif
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ifneq (,$(filter mtd,$(USEMODULE)))
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USEMODULE += mtd_spi_nor
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endif
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.dep
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@ -1,14 +1,3 @@
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CPU = stm32
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CPU_MODEL = stm32f411ce
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_usbdev
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FEATURES_PROVIDED += highlevel_stdio
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.features
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@ -1,14 +1,5 @@
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INCLUDES += -I$(RIOTBOARD)/common/stm32/include
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# Product & Vendor ID taken from example firmware that the board was shipped with.
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CFLAGS += -DINTERNAL_PERIPHERAL_VID=0x0483
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CFLAGS += -DINTERNAL_PERIPHERAL_PID=0x5740
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# default to flashing over USB
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PROGRAMMER ?= dfu-util
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DFU_USB_ID ?= 0483:df11
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DFU_FLAGS ?= -a 0 -s 0x08000000:leave
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ROM_OFFSET ?= 0x0
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# CDC ACM is available faster on STM32
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TERM_DELAY ?= 1
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# Setup of programmer and serial is shared between STM32 based boards
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include $(RIOTMAKE)/boards/stm32.inc.mk
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include $(RIOTMAKE)/tools/usb_board_reset.mk
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include $(RIOTBOARD)/common/weact-f4x1cx/Makefile.include
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@ -1,64 +0,0 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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* @{
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*
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* @file
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* @brief Board initialization code for the WeAct-F411CE board.
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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#include "mtd.h"
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#include "timex.h"
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#include "mtd_spi_nor.h"
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#include "periph/gpio.h"
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#ifdef MODULE_MTD
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/* AT25SF041 */
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static const mtd_spi_nor_params_t _weact_nor_params = {
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.opcode = &mtd_spi_nor_opcode_default,
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.wait_chip_erase = 4800LU * US_PER_MS,
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.wait_32k_erase = 300LU * US_PER_MS,
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.wait_sector_erase = 70LU * US_PER_MS,
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.wait_chip_wake_up = 1LU * US_PER_MS,
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.clk = WEACT_411CE_NOR_SPI_CLK,
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.flag = WEACT_411CE_NOR_FLAGS,
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.spi = WEACT_411CE_NOR_SPI_DEV,
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.mode = WEACT_411CE_NOR_SPI_MODE,
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.cs = WEACT_411CE_NOR_SPI_CS,
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.wp = GPIO_UNDEF,
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.hold = GPIO_UNDEF,
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.addr_width = 3,
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};
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static mtd_spi_nor_t weact_nor_dev = {
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.base = {
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.driver = &mtd_spi_nor_driver,
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.page_size = WEACT_411CE_NOR_PAGE_SIZE,
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.pages_per_sector = WEACT_411CE_NOR_PAGES_PER_SECTOR,
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},
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.params = &_weact_nor_params,
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};
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mtd_dev_t *mtd0 = (mtd_dev_t *)&weact_nor_dev;
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#endif /* MODULE_MTD */
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void board_init(void)
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{
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cpu_init();
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gpio_init(LED0_PIN, GPIO_OUT);
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LED0_OFF;
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}
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@ -1,103 +0,0 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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*
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* @brief Support for the WeAct-F411CE Board
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* @{
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*
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* @file
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* @brief Pin definitions and board configuration options
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "mtd.h"
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#include "periph_cpu.h"
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/**
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* @name Xtimer configuration
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* @{
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*/
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#define XTIMER_BACKOFF (8)
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#define XTIMER_OVERHEAD (6)
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/** @} */
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/**
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* @brief Product & Vendor ID taken from example firmware
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* that the board was shipped with.
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* @{
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*/
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#define INTERNAL_PERIPHERAL_VID (0x0483)
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#define INTERNAL_PERIPHERAL_PID (0x5740)
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/** @} */
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/**
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* @name LED pin definition and handlers
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* @{
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*/
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#define LED0_PORT GPIOC
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#define LED0_PIN GPIO_PIN(PORT_C, 13)
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#define LED0_MASK (1 << 13)
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#define LED0_ON (LED0_PORT->BSRR = (LED0_MASK << 16))
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#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 0))
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#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
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/** @} */
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/**
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* @name User button pin definition
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* @{
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*/
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#define BTN0_PIN GPIO_PIN(PORT_A, 0)
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#define BTN0_MODE GPIO_IN_PU
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/** @} */
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/**
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* @name WeAct-F411CE NOR flash hardware configuration
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*
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* The pad for the NOR Flash (U3) is not populated.
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* You have to solder a serial flash yourself and adjust the parameters.
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* @{
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*/
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#define WEACT_411CE_NOR_PAGE_SIZE (256)
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#define WEACT_411CE_NOR_PAGES_PER_SECTOR (16)
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#define WEACT_411CE_NOR_FLAGS (SPI_NOR_F_SECT_4K | SPI_NOR_F_SECT_32K)
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#define WEACT_411CE_NOR_SPI_DEV SPI_DEV(0)
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#define WEACT_411CE_NOR_SPI_CLK SPI_CLK_10MHZ
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#define WEACT_411CE_NOR_SPI_CS GPIO_PIN(PORT_A, 4)
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#define WEACT_411CE_NOR_SPI_MODE SPI_MODE_0
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/** @} */
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/**
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* @name MTD configuration
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* @{
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*/
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extern mtd_dev_t *mtd0;
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#define MTD_0 mtd0
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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@ -1,53 +0,0 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED",
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.pin = LED0_PIN,
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.mode = GPIO_OUT,
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.flags = (SAUL_GPIO_INVERTED | SAUL_GPIO_INIT_CLEAR)
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},
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{
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.name = "KEY",
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.pin = BTN0_PIN,
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.mode = BTN0_MODE,
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.flags = SAUL_GPIO_INVERTED
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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@ -1,193 +0,0 @@
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_weact-f411ce
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the WeAct-F411CE Board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author José Ignacio Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* This board provides an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* This board provides an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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/* The HSE provides a 25MHz clock */
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#define CLOCK_HSE MHZ(25)
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#include "cfg_i2c1_pb8_pb9.h"
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#include "cfg_timer_tim5.h"
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#include "cfg_usb_otg_fs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = DMA_STREAM_UNDEF,
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.dma_chan = UINT8_MAX,
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = DMA_STREAM_UNDEF,
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.dma_chan = UINT8_MAX,
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#endif
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},
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};
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/* assign ISR vector names */
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#define UART_0_ISR isr_usart2
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#define UART_1_ISR isr_usart1
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/* deduct number of defined UART interfaces */
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/** @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM2,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 3), /* D3 */ .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_B, 10), /* D6 */ .cc_chan = 2 },
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{ .pin = GPIO_UNDEF, .cc_chan = 0 } },
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.af = GPIO_AF1,
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.bus = APB1
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},
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4), /* D5 */ .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_C, 7), /* D9 */ .cc_chan = 1 },
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{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
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.af = GPIO_AF2,
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.bus = APB1
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},
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{ /* U3 - SPI flash */
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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},
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{
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.dev = SPI3,
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.mosi_pin = GPIO_PIN(PORT_B, 5),
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.miso_pin = GPIO_PIN(PORT_B, 4),
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.sclk_pin = GPIO_PIN(PORT_B, 3),
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.cs_pin = GPIO_PIN(PORT_A, 15),
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.mosi_af = GPIO_AF6,
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.miso_af = GPIO_AF6,
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.sclk_af = GPIO_AF6,
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.cs_af = GPIO_AF6,
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.rccmask = RCC_APB1ENR_SPI3EN,
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.apbbus = APB1
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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||||
|
||||
/**
|
||||
* @name ADC configuration
|
||||
*
|
||||
* Note that we do not configure all ADC channels,
|
||||
* and not in the STM32F411 order.
|
||||
* Feel free to add more if needed.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
static const adc_conf_t adc_config[] = {
|
||||
{GPIO_PIN(PORT_A, 0), 0, 0},
|
||||
{GPIO_PIN(PORT_A, 1), 0, 1},
|
||||
{GPIO_PIN(PORT_A, 4), 0, 4},
|
||||
{GPIO_PIN(PORT_B, 0), 0, 8},
|
||||
};
|
||||
|
||||
#define ADC_NUMOF ARRAY_SIZE(adc_config)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PERIPH_CONF_H */
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue
Block a user