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Merge pull request #10621 from aabadie/pr/cpu/nrf_uart_rework

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cpu/nrf5x: rework periph_uart driver to allow use of multiple UARTs with nrf52840
This commit is contained in:
Hauke Petersen 2019-01-25 16:27:06 +01:00 committed by GitHub
commit 250b7cbbbf
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 314 additions and 70 deletions
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15
boards/common/nrf52xxxdk/include/periph_conf.h → boards/common/nrf52xxxdk/include/periph_conf_common.h
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@ -18,8 +18,8 @@
*
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#ifndef PERIPH_CONF_COMMON_H
#define PERIPH_CONF_COMMON_H
#include "periph_cpu.h"
#include "cfg_clock_32_1.h"
@ -30,15 +30,6 @@
extern "C" {
#endif
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_PIN_RX GPIO_PIN(0,8)
#define UART_PIN_TX GPIO_PIN(0,6)
/** @} */
/**
* @name SPI configuration
* @{
@ -84,5 +75,5 @@ static const pwm_conf_t pwm_config[] = {
}
#endif
#endif /* PERIPH_CONF_H */
#endif /* PERIPH_CONF_COMMON_H */
/** @} */

63
boards/nrf52840dk/include/periph_conf.h Normal file
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@ -0,0 +1,63 @@
/*
* Copyright (C) 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nrf52840dk
* @{
*
* @file
* @brief Peripheral configuration for the nRF52840 DK
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_conf_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{ /* Mapped to USB virtual COM port */
.dev = NRF_UARTE0,
.rx_pin = GPIO_PIN(0,8),
.tx_pin = GPIO_PIN(0,6),
.rts_pin = GPIO_PIN(0,5),
.cts_pin = GPIO_PIN(0,7),
.irqn = UARTE0_UART0_IRQn,
},
{ /* Mapped to Arduino D0/D1 pins */
.dev = NRF_UARTE1,
.rx_pin = GPIO_PIN(1,1),
.tx_pin = GPIO_PIN(1,2),
.rts_pin = (uint8_t)GPIO_UNDEF,
.cts_pin = (uint8_t)GPIO_UNDEF,
.irqn = UARTE1_IRQn,
},
};
#define UART_0_ISR (isr_uart0)
#define UART_1_ISR (isr_uarte1)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

45
boards/nrf52dk/include/periph_conf.h Normal file
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@ -0,0 +1,45 @@
/*
* Copyright (C) 2016-2018 Freie Universität Berlin
* 2018 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nrf52dk
* @{
*
* @file
* @brief Peripheral configuration for the nRF52 DK
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_conf_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name UART configuration
* @{
*/
#define UART_NUMOF (1U)
#define UART_PIN_RX GPIO_PIN(0,8)
#define UART_PIN_TX GPIO_PIN(0,6)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

17
cpu/nrf52/include/periph_cpu.h
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@ -39,10 +39,12 @@ extern "C" {
* @brief Redefine some peripheral names to unify them between nRF51 and 52
* @{
*/
#define UART_IRQN (UARTE0_UART0_IRQn)
#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
#ifndef CPU_MODEL_NRF52840XXAA
#define UART_IRQN (UARTE0_UART0_IRQn)
#endif
/** @} */
/**
@ -155,6 +157,19 @@ typedef struct {
uint32_t pin[PWM_CHANNELS]; /**< PWM out pins */
} pwm_conf_t;
#ifdef CPU_MODEL_NRF52840XXAA
/**
* @brief Structure for UART configuration data
*/
typedef struct {
NRF_UARTE_Type *dev; /**< UART with EasyDMA device base register address */
uint8_t rx_pin; /**< RX pin */
uint8_t tx_pin; /**< TX pin */
uint8_t rts_pin; /**< RTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */
uint8_t irqn; /**< IRQ channel */
} uart_conf_t;
#endif
#ifdef __cplusplus
}

244
cpu/nrf5x_common/periph/uart.c
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@ -1,6 +1,7 @@
/*
* Copyright (C) 2014-2017 Freie Universität Berlin
* 2015 Jan Wagner <mail@jwagner.eu>
* 2018 Inria
*
*
* This file is subject to the terms and conditions of the GNU Lesser
@ -20,6 +21,7 @@
* @author Timo Ziegler <timo.ziegler@fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
* @author Jan Wagner <mail@jwagner.eu>
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
@ -31,31 +33,58 @@
#include "periph/gpio.h"
#ifdef CPU_MODEL_NRF52840XXAA
#define PSEL_RXD NRF_UART0->PSEL.RXD
#define PSEL_TXD NRF_UART0->PSEL.TXD
#define PSEL_RTS NRF_UART0->PSEL.RTS
#define PSEL_CTS NRF_UART0->PSEL.CTS
#else
#define PSEL_RXD NRF_UART0->PSELRXD
#define PSEL_TXD NRF_UART0->PSELTXD
#define PSEL_RTS NRF_UART0->PSELRTS
#define PSEL_CTS NRF_UART0->PSELCTS
#endif
#define UART_INVALID (uart >= UART_NUMOF)
#define REG_BAUDRATE dev(uart)->BAUDRATE
#define REG_CONFIG dev(uart)->CONFIG
#define PSEL_RXD dev(uart)->PSEL.RXD
#define PSEL_TXD dev(uart)->PSEL.TXD
#define UART_IRQN uart_config[uart].irqn
#define UART_PIN_RX uart_config[uart].rx_pin
#define UART_PIN_TX uart_config[uart].tx_pin
#define UART_PIN_RTS uart_config[uart].rts_pin
#define UART_PIN_CTS uart_config[uart].cts_pin
#define UART_HWFLOWCTRL (uart_config[uart].rts_pin != (uint8_t)GPIO_UNDEF && \
uart_config[uart].cts_pin != (uint8_t)GPIO_UNDEF)
#define ISR_CTX isr_ctx[uart]
/**
* @brief Allocate memory for the interrupt context
*/
static uart_isr_ctx_t uart_config;
static uart_isr_ctx_t isr_ctx[UART_NUMOF];
static uint8_t rx_buf[UART_NUMOF];
static inline NRF_UARTE_Type *dev(uart_t uart)
{
return uart_config[uart].dev;
}
#else /* nrf51 and nrf52832 etc */
#define UART_INVALID (uart != 0)
#define REG_BAUDRATE NRF_UART0->BAUDRATE
#define REG_CONFIG NRF_UART0->CONFIG
#define PSEL_RXD NRF_UART0->PSELRXD
#define PSEL_TXD NRF_UART0->PSELTXD
#define UART_0_ISR isr_uart0
#define ISR_CTX isr_ctx
/**
* @brief Allocate memory for the interrupt context
*/
static uart_isr_ctx_t isr_ctx;
#endif /* CPU_MODEL_NRF52840XXAA */
int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
if (uart != 0) {
if (UART_INVALID) {
return UART_NODEV;
}
/* remember callback addresses and argument */
uart_config.rx_cb = rx_cb;
uart_config.arg = arg;
ISR_CTX.rx_cb = rx_cb;
ISR_CTX.arg = arg;
#ifdef CPU_FAM_NRF51
/* power on the UART device */
@ -63,7 +92,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
#endif
/* reset configuration registers */
NRF_UART0->CONFIG = 0;
REG_CONFIG = 0;
/* configure RX pin */
if (rx_cb) {
@ -75,129 +104,230 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
gpio_init(UART_PIN_TX, GPIO_OUT);
PSEL_TXD = UART_PIN_TX;
#ifdef CPU_MODEL_NRF52840XXAA
/* enable HW-flow control if defined */
if (UART_HWFLOWCTRL) {
/* set pin mode for RTS and CTS pins */
gpio_init(UART_PIN_RTS, GPIO_OUT);
gpio_init(UART_PIN_CTS, GPIO_IN);
/* configure RTS and CTS pins to use */
dev(uart)->PSEL.RTS = UART_PIN_RTS;
dev(uart)->PSEL.CTS = UART_PIN_CTS;
REG_CONFIG |= UART_CONFIG_HWFC_Msk; /* enable HW flow control */
} else {
dev(uart)->PSEL.RTS = 0xffffffff; /* pin disconnected */
dev(uart)->PSEL.CTS = 0xffffffff; /* pin disconnected */
}
#else
#if UART_HWFLOWCTRL
/* set pin mode for RTS and CTS pins */
gpio_init(UART_PIN_RTS, GPIO_OUT);
gpio_init(UART_PIN_CTS, GPIO_IN);
/* configure RTS and CTS pins to use */
PSEL_RTS = UART_PIN_RTS;
PSEL_CTS = UART_PIN_CTS;
NRF_UART0->CONFIG |= UART_CONFIG_HWFC_Msk; /* enable HW flow control */
NRF_UART0->PSELRTS = UART_PIN_RTS;
NRF_UART0->PSELCTS = UART_PIN_CTS;
REG_CONFIG |= UART_CONFIG_HWFC_Msk; /* enable HW flow control */
#else
PSEL_RTS = 0xffffffff; /* pin disconnected */
PSEL_CTS = 0xffffffff; /* pin disconnected */
NRF_UART0->PSELRTS = 0xffffffff; /* pin disconnected */
NRF_UART0->PSELCTS = 0xffffffff; /* pin disconnected */
#endif
#endif
/* select baudrate */
switch (baudrate) {
case 1200:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200;
break;
case 2400:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud2400;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud2400;
break;
case 4800:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud4800;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud4800;
break;
case 9600:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud9600;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud9600;
break;
case 14400:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud14400;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud14400;
break;
case 19200:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud19200;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud19200;
break;
case 28800:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud28800;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud28800;
break;
case 38400:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud38400;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud38400;
break;
case 57600:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud57600;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud57600;
break;
case 76800:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud76800;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud76800;
break;
case 115200:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud115200;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud115200;
break;
case 230400:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud230400;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud230400;
break;
case 250000:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud250000;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud250000;
break;
case 460800:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud460800;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud460800;
break;
case 921600:
NRF_UART0->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud921600;
REG_BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud921600;
break;
default:
return UART_NOBAUD;
}
/* enable the UART device */
#ifdef CPU_MODEL_NRF52840XXAA
dev(uart)->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
#else
NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Enabled;
/* enable TX and RX */
NRF_UART0->TASKS_STARTTX = 1;
#endif
if (rx_cb) {
#ifdef CPU_MODEL_NRF52840XXAA
dev(uart)->RXD.MAXCNT = 1;
dev(uart)->RXD.PTR = (uint32_t)&rx_buf[uart];
dev(uart)->INTENSET = UARTE_INTENSET_ENDRX_Msk;
dev(uart)->SHORTS |= UARTE_SHORTS_ENDRX_STARTRX_Msk;
dev(uart)->TASKS_STARTRX = 1;
#else
NRF_UART0->INTENSET = UART_INTENSET_RXDRDY_Msk;
NRF_UART0->TASKS_STARTRX = 1;
#endif
/* enable global and receiving interrupt */
NVIC_EnableIRQ(UART_IRQN);
NRF_UART0->INTENSET = UART_INTENSET_RXDRDY_Msk;
}
return UART_OK;
}
#ifdef CPU_MODEL_NRF52840XXAA /* nrf52840 (using EasyDMA) */
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
if (uart == 0) {
for (size_t i = 0; i < len; i++) {
/* This section of the function is not thread safe:
- another thread may mess up with the uart at the same time.
In order to avoid an infinite loop in the interrupted thread,
the TXRDY flag must be cleared before writing the data to be
sent and not after. This way, the higher priority thread will
exit this function with the TXRDY flag set, then the interrupted
thread may have not transmitted his data but will still exit the
while loop.
*/
assert(uart < UART_NUMOF);
/* reset ready flag */
NRF_UART0->EVENTS_TXDRDY = 0;
/* write data into transmit register */
NRF_UART0->TXD = data[i];
/* wait for any transmission to be done */
while (NRF_UART0->EVENTS_TXDRDY == 0) {}
/* reset endtx flag */
dev(uart)->EVENTS_ENDTX = 0;
/* set data to transfer to DMA TX pointer */
dev(uart)->TXD.PTR = (uint32_t)data;
dev(uart)->TXD.MAXCNT = len;
/* start transmission */
dev(uart)->TASKS_STARTTX = 1;
/* wait for the end of transmission */
while (dev(uart)->EVENTS_ENDTX == 0) {}
}
void uart_poweron(uart_t uart)
{
assert(uart < UART_NUMOF);
if (isr_ctx[uart].rx_cb) {
NRF_UART0->TASKS_STARTRX = 1;
}
}
void uart_poweroff(uart_t uart)
{
assert(uart < UART_NUMOF);
dev(uart)->TASKS_STOPRX = 1;
}
static inline void irq_handler(uart_t uart)
{
if (dev(uart)->EVENTS_ENDRX == 1) {
dev(uart)->EVENTS_ENDRX = 0;
/* make sure we actually received new data */
if (dev(uart)->RXD.AMOUNT == 0) {
return;
}
/* Process received byte */
isr_ctx[uart].rx_cb(isr_ctx[uart].arg, rx_buf[uart]);
}
cortexm_isr_end();
}
#else /* nrf51 and nrf52832 etc */
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
(void)uart;
for (size_t i = 0; i < len; i++) {
/* This section of the function is not thread safe:
- another thread may mess up with the uart at the same time.
In order to avoid an infinite loop in the interrupted thread,
the TXRDY flag must be cleared before writing the data to be
sent and not after. This way, the higher priority thread will
exit this function with the TXRDY flag set, then the interrupted
thread may have not transmitted his data but will still exit the
while loop.
*/
/* reset ready flag */
NRF_UART0->EVENTS_TXDRDY = 0;
/* write data into transmit register */
NRF_UART0->TXD = data[i];
/* wait for any transmission to be done */
while (NRF_UART0->EVENTS_TXDRDY == 0) {}
}
}
void uart_poweron(uart_t uart)
{
(void)uart;
NRF_UART0->TASKS_STARTRX = 1;
NRF_UART0->TASKS_STARTTX = 1;
if (isr_ctx.rx_cb) {
NRF_UART0->TASKS_STARTRX = 1;
}
}
void uart_poweroff(uart_t uart)
{
(void)uart;
NRF_UART0->TASKS_SUSPEND;
}
void isr_uart0(void)
static inline void irq_handler(uart_t uart)
{
(void)uart;
if (NRF_UART0->EVENTS_RXDRDY == 1) {
NRF_UART0->EVENTS_RXDRDY = 0;
uint8_t byte = (uint8_t)(NRF_UART0->RXD & 0xff);
uart_config.rx_cb(uart_config.arg, byte);
isr_ctx.rx_cb(isr_ctx.arg, byte);
}
cortexm_isr_end();
}
#endif /* CPU_MODEL_NRF52840XXAA */
#ifdef UART_0_ISR
void UART_0_ISR(void)
{
irq_handler(UART_DEV(0));
}
#endif
#ifdef UART_1_ISR
void UART_1_ISR(void)
{
irq_handler(UART_DEV(1));
}
#endif