mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2025-01-17 06:12:43 +01:00
cpu/atmega2560: reworked timer driver
This commit is contained in:
Hauke Petersen
parent
9e4c08d89c
commit
23b75c421f
@ -19,9 +19,6 @@
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* @}
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <avr/interrupt.h>
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#include "board.h"
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@ -31,449 +28,231 @@
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#include "periph/timer.h"
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#include "periph_conf.h"
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#define IRQ_DISABLED 0x00
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/**
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* @brief All timers have three channels
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*/
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#define CHANNELS (3)
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/**
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* @brief Timer state memory
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* @brief We have 5 possible prescaler values
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*/
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static timer_isr_ctx_t config[TIMER_NUMOF];
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#define PRESCALE_NUMOF (5U)
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/**
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* @brief Possible prescaler values, encoded as 2 ^ val
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*/
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static const uint8_t prescalers[] = { 0, 3, 6, 8, 10 };
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/**
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* @brief Timer state context
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*/
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typedef struct {
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mega_timer_t *dev; /**< timer device */
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volatile uint8_t *mask; /**< address of interrupt mask register */
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volatile uint8_t *flag; /**< address of interrupt flag register */
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timer_cb_t cb; /**< interrupt callback */
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void *arg; /**< interrupt callback argument */
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uint8_t mode; /**< remember the configured mode */
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uint8_t isrs; /**< remember the interrupt state */
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} ctx_t;
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/**
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* @brief Allocate memory for saving the device states
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* @{
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*/
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#if TIMER_NUMOF
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static ctx_t ctx[] = {
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#ifdef TIMER_0
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{ TIMER_0, TIMER_0_MASK, TIMER_0_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_1
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{ TIMER_1, TIMER_1_MASK, TIMER_1_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_2
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{ TIMER_2, TIMER_2_MASK, TIMER_2_FLAG, NULL, NULL, 0, 0 },
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#endif
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#ifdef TIMER_3
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{ TIMER_3, TIMER_3_MASK, TIMER_3_FLAG, NULL, NULL, 0, 0 },
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#endif
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};
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#else
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/* fallback if no timer is configured */
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static ctx_t *ctx[] = {{ NULL }};
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#endif
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/** @} */
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/**
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* @brief Setup the given timer
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*
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*/
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int timer_init(tim_t dev, unsigned long freq, timer_cb_t cb, void *arg)
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int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
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{
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/* reject impossible freq values
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* todo: Add support for 2 MHz and 16 MHz */
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if ((freq != 250000ul)) {
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uint8_t pre = 0;
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/* make sure given device is valid */
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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/* select the timer and enable the timer specific peripheral clocks */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER0_COUNTER = 0;
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TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
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/* figure out if freq is applicable */
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for (; pre < PRESCALE_NUMOF; pre++) {
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if ((CLOCK_CORECLOCK >> prescalers[pre]) == freq) {
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER1_COUNTER = 0;
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TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER2_COUNTER = 0;
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TIMER2_CONTROL_B |= TIMER2_FREQ_250KHZ;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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}
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if (pre == PRESCALE_NUMOF) {
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return -1;
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}
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/* save callback */
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config[dev].cb = cb;
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config[dev].arg = arg;
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/* stop and reset timer */
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ctx[tim].dev->CRA = 0;
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ctx[tim].dev->CRB = 0;
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ctx[tim].dev->CRC = 0;
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ctx[tim].dev->CNT = 0;
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/* save interrupt context and timer mode */
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ctx[tim].cb = cb;
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ctx[tim].arg = arg;
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ctx[tim].mode = (pre + 1);
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/* enable timer with calculated prescaler */
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ctx[tim].dev->CRB = (pre + 1);
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return 0;
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}
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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int timer_set(tim_t tim, int channel, unsigned int timeout)
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{
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return timer_set_absolute(dev, channel, timer_read(dev) + timeout);
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return timer_set_absolute(tim, channel, timer_read(tim) + timeout);
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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unsigned state = irq_disable();
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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switch (channel) {
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case 0:
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TIMER0_COMP_A = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_A_EN);
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break;
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case 1:
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TIMER0_COMP_B = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_B_EN);
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break;
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case 2:
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TIMER0_COMP_C = (uint16_t) value;
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
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TIMER0_IRQ_MASK_REG |= (1 << TIMER0_COMP_C_EN);
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break;
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default:
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irq_restore(state);
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return -1;
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}
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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switch (channel) {
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case 0:
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TIMER1_COMP_A = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_A_EN);
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break;
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case 1:
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TIMER1_COMP_B = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_B_EN);
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break;
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case 2:
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TIMER1_COMP_C = (uint16_t) value;
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
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TIMER1_IRQ_MASK_REG |= (1 << TIMER1_COMP_C_EN);
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break;
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default:
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irq_restore(state);
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return -1;
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}
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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switch (channel) {
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case 0:
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TIMER2_COMP_A = (uint16_t) value;
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
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TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_A_EN);
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break;
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case 1:
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TIMER2_COMP_B = (uint16_t) value;
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
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TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_B_EN);
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break;
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case 2:
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TIMER2_COMP_C = (uint16_t) value;
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
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TIMER2_IRQ_MASK_REG |= (1 << TIMER2_COMP_C_EN);
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break;
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default:
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irq_restore(state);
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return -1;
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}
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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irq_restore(state);
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return -1;
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if (channel >= CHANNELS) {
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return -1;
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}
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/* enable interrupts for given timer */
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timer_irq_enable(dev);
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irq_restore(state);
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ctx[tim].dev->OCR[channel] = (uint16_t)value;
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*ctx[tim].flag &= ~(1 << (channel + OCF1A));
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*ctx[tim].mask |= (1 << (channel + OCIE1A));
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return 1;
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return 0;
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}
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int timer_clear(tim_t dev, int channel)
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int timer_clear(tim_t tim, int channel)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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switch (channel) {
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case 0:
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_A_FLAG);
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break;
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case 1:
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_B_FLAG);
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break;
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case 2:
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TIMER0_IRQ_FLAG_REG &= ~(1 << TIMER0_COMP_C_FLAG);
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break;
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default:
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return -1;
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}
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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switch (channel) {
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case 0:
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_A_FLAG);
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break;
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case 1:
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_B_FLAG);
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break;
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case 2:
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TIMER1_IRQ_FLAG_REG &= ~(1 << TIMER1_COMP_C_FLAG);
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break;
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default:
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return -1;
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break;
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}
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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switch (channel) {
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case 0:
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_A_FLAG);
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break;
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case 1:
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_B_FLAG);
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break;
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case 2:
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TIMER2_IRQ_FLAG_REG &= ~(1 << TIMER2_COMP_C_FLAG);
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break;
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default:
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return -1;
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break;
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}
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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if (channel >= CHANNELS) {
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return -1;
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}
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timer_irq_disable(dev);
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return 1;
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*ctx[tim].mask &= ~(1 << (channel + OCIE1A));
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return 0;
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}
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unsigned int timer_read(tim_t dev)
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unsigned int timer_read(tim_t tim)
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{
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uint16_t a;
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uint16_t b;
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/*
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* Disabling interrupts globally because read from 16 Bit register can
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* otherwise be messed up
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*/
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unsigned state = irq_disable();
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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do {
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a = TIMER0_COUNTER;
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b = TIMER0_COUNTER;
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} while (a != b);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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do {
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a = TIMER1_COUNTER;
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b = TIMER1_COUNTER;
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} while (a != b);
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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do {
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a = TIMER2_COUNTER;
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b = TIMER2_COUNTER;
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} while (a != b);
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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(void)b;
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a = 0;
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}
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irq_restore(state);
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return a;
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return (unsigned int)ctx[tim].dev->CNT;
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}
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void timer_stop(tim_t dev)
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void timer_stop(tim_t tim)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER0_CONTROL_B = TIMER0_FREQ_DISABLE;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER1_CONTROL_B = TIMER1_FREQ_DISABLE;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER2_CONTROL_B = TIMER2_FREQ_DISABLE;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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ctx[tim].dev->CRB = 0;
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}
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void timer_start(tim_t dev)
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void timer_start(tim_t tim)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER0_CONTROL_B |= TIMER0_FREQ_250KHZ;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER1_CONTROL_B |= TIMER1_FREQ_250KHZ;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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ctx[tim].dev->CRB = ctx[tim].mode;
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}
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void timer_irq_enable(tim_t dev)
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void timer_irq_enable(tim_t tim)
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{
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(void) dev;
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#ifdef DEVELHELP
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printf("timer_irq_enable not implemented\n");
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#endif
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*ctx[tim].mask = ctx[tim].isrs;
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}
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void timer_irq_disable(tim_t dev)
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void timer_irq_disable(tim_t tim)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_A_EN);
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TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_B_EN);
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TIMER0_IRQ_MASK_REG &= ~(1 << TIMER0_COMP_C_EN);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_A_EN);
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TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_B_EN);
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TIMER1_IRQ_MASK_REG &= ~(1 << TIMER1_COMP_C_EN);
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_A_EN);
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TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_B_EN);
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TIMER2_IRQ_MASK_REG &= ~(1 << TIMER2_COMP_C_EN);
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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ctx[tim].isrs = *(ctx[tim].mask);
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*ctx[tim].mask = 0;
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}
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static inline void _isr(int timer, int chan)
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static inline void _isr(int num, int chan)
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{
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__enter_isr();
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timer_clear(timer, chan);
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config[timer].cb(config[timer].arg, chan);
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*ctx[num].mask &= ~(1 << (chan + OCIE1A));
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ctx[num].cb(ctx[num].arg, chan);
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if (sched_context_switch_request) {
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thread_yield();
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}
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__exit_isr();
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}
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#if TIMER_0_EN
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ISR(TIMER0_COMPA_ISR, ISR_BLOCK)
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#ifdef TIMER_0
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ISR(TIMER_0_ISRA, ISR_BLOCK)
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{
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_isr(0, 0);
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}
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|
||||
ISR(TIMER0_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_0_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(0, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER0_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_0_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(0, 2);
|
||||
}
|
||||
#endif /* TIMER_0_EN */
|
||||
#endif /* TIMER_0 */
|
||||
|
||||
#if TIMER_1_EN
|
||||
ISR(TIMER1_COMPA_ISR, ISR_BLOCK)
|
||||
#ifdef TIMER_1
|
||||
ISR(TIMER_1_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER1_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_1_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER1_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_1_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(1, 2);
|
||||
}
|
||||
#endif /* TIMER_1_EN */
|
||||
#endif /* TIMER_1 */
|
||||
|
||||
#if TIMER_2_EN
|
||||
ISR(TIMER2_COMPA_ISR, ISR_BLOCK)
|
||||
#ifdef TIMER_2
|
||||
ISR(TIMER_2_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER2_COMPB_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_2_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER2_COMPC_ISR, ISR_BLOCK)
|
||||
ISR(TIMER_2_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 2);
|
||||
}
|
||||
#endif /* TIMER_2_EN */
|
||||
#endif /* TIMER_2 */
|
||||
|
||||
#ifdef TIMER_3
|
||||
ISR(TIMER_3_ISRA, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 0);
|
||||
}
|
||||
|
||||
ISR(TIMER_3_ISRB, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 1);
|
||||
}
|
||||
|
||||
ISR(TIMER_3_ISRC, ISR_BLOCK)
|
||||
{
|
||||
_isr(2, 2);
|
||||
}
|
||||
#endif /* TIMER_3 */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user