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cpu/samd5x/cpu.c: reformat code

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This formats the code to improve readability and apply the coding
convention. This is a whitespace only change that will not change
generated binaries.
This commit is contained in:
Marian Buschsieweke 2024-09-17 22:07:46 +02:00
parent 0cea359db6
commit 20e218680c
No known key found for this signature in database
GPG Key ID: 758BD52517F79C41
1 changed files with 65 additions and 48 deletions
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51
cpu/samd5x/cpu.c
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@ -24,7 +24,6 @@
#include "macros/units.h"
#include "periph_conf.h"
#include "periph/init.h"
#include "stdio_base.h"
/*
* An external inductor needs to be present on the board,
@ -50,7 +49,8 @@
# define XOSC1_FREQUENCY (0)
#endif
#define GCLK_SOURCE_ACTIVE_XOSC (XOSC0_FREQUENCY ? GCLK_SOURCE_XOSC0 : GCLK_SOURCE_XOSC1)
#define GCLK_SOURCE_ACTIVE_XOSC \
(XOSC0_FREQUENCY ? GCLK_SOURCE_XOSC0 : GCLK_SOURCE_XOSC1)
#if USE_XOSC_ONLY /* don't use fast internal oscillators */
@ -127,7 +127,8 @@ static void xosc_init(uint8_t idx)
if (idx == 0) {
freq = XOSC0_FREQUENCY;
} else if (idx == 1) {
}
else if (idx == 1) {
freq = XOSC1_FREQUENCY;
}
@ -143,17 +144,20 @@ static void xosc_init(uint8_t idx)
reg |= OSCCTRL_XOSCCTRL_STARTUP(9)
| OSCCTRL_XOSCCTRL_IMULT(3)
| OSCCTRL_XOSCCTRL_IPTAT(2);
} else if (freq <= MHZ(16)) {
}
else if (freq <= MHZ(16)) {
/* 62000 cycles @ 16MHz = 3875 µs */
reg |= OSCCTRL_XOSCCTRL_STARTUP(7)
| OSCCTRL_XOSCCTRL_IMULT(4)
| OSCCTRL_XOSCCTRL_IPTAT(3);
} else if (freq <= MHZ(24)) {
}
else if (freq <= MHZ(24)) {
/* 68500 cycles @ 24MHz = 2854 µs */
reg |= OSCCTRL_XOSCCTRL_STARTUP(7)
| OSCCTRL_XOSCCTRL_IMULT(5)
| OSCCTRL_XOSCCTRL_IPTAT(3);
} else {
}
else {
/* 38500 cycles @ 48MHz = 802 µs */
reg |= OSCCTRL_XOSCCTRL_STARTUP(5)
| OSCCTRL_XOSCCTRL_IMULT(6)
@ -217,13 +221,18 @@ static void fdpll_init_nolock(uint8_t idx, uint32_t f_cpu, uint8_t flags)
while (OSCCTRL->Dpll[idx].DPLLSYNCBUSY.reg) {}
}
static void fdpll_lock(uint8_t idx) {
static void fdpll_lock(uint8_t idx)
{
const uint32_t flags = (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK);
while (!((OSCCTRL->Dpll[idx].DPLLSTATUS.reg & flags) == flags)) {}
}
static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags) {
GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src) | GCLK_GENCTRL_GENEN | flags | GCLK_GENCTRL_IDC;
static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags)
{
GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src)
| GCLK_GENCTRL_GENEN
| flags
| GCLK_GENCTRL_IDC;
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(id)) {}
}
@ -238,11 +247,13 @@ void sam0_gclk_enable(uint8_t id)
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_DPLL0,
GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / GCLK_TIMER_HZ));
} else if (USE_DFLL) {
}
else if (USE_DFLL) {
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_DFLL,
GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / GCLK_TIMER_HZ));
} else if (USE_XOSC) {
}
else if (USE_XOSC) {
gclk_connect(SAM0_GCLK_TIMER,
GCLK_SOURCE_ACTIVE_XOSC,
GCLK_GENCTRL_DIV(SAM0_XOSC_FREQ_HZ / GCLK_TIMER_HZ));
@ -251,7 +262,8 @@ void sam0_gclk_enable(uint8_t id)
case SAM0_GCLK_PERIPH:
if (USE_DFLL) {
gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_DFLL, 0);
} else if (USE_XOSC) {
}
else if (USE_XOSC) {
gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
}
break;
@ -275,9 +287,11 @@ uint32_t sam0_gclk_freq(uint8_t id)
case SAM0_GCLK_PERIPH:
if (USE_DFLL) {
return SAM0_DFLL_FREQ_HZ;
} else if (USE_XOSC) {
}
else if (USE_XOSC) {
return SAM0_XOSC_FREQ_HZ;
} else {
}
else {
assert(0);
return 0;
}
@ -355,7 +369,8 @@ void cpu_init(void)
xosc32k_init();
if (EXTERNAL_OSC32_SOURCE) {
gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_XOSC32K, 0);
} else if (ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE) {
}
else if (ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE) {
gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_OSCULP32K, 0);
}
@ -368,10 +383,12 @@ void cpu_init(void)
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DPLL0,
GCLK_GENCTRL_DIV(DPLL_DIV));
fdpll_lock(0);
} else if (USE_DFLL) {
}
else if (USE_DFLL) {
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL,
GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
} else if (USE_XOSC) {
}
else if (USE_XOSC) {
gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_ACTIVE_XOSC,
GCLK_GENCTRL_DIV(SAM0_XOSC_FREQ_HZ / CLOCK_CORECLOCK));
}