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https://github.com/RIOT-OS/RIOT.git
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cpu/samd5x/cpu.c: reformat code
This formats the code to improve readability and apply the coding convention. This is a whitespace only change that will not change generated binaries.
This commit is contained in:
Marian Buschsieweke
parent
0cea359db6
commit
20e218680c
113
cpu/samd5x/cpu.c
113
cpu/samd5x/cpu.c
@ -24,75 +24,75 @@
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#include "macros/units.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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#include "stdio_base.h"
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/*
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* An external inductor needs to be present on the board,
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* so the feature can only be enabled by the board configuration.
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*/
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#ifndef USE_VREG_BUCK
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#define USE_VREG_BUCK (0)
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# define USE_VREG_BUCK (0)
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#endif
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#if CLOCK_CORECLOCK == 0
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#error Please select CLOCK_CORECLOCK
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# error Please select CLOCK_CORECLOCK
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#endif
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#if EXTERNAL_OSC32_SOURCE && ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE
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#error Select EITHER external 32kHz oscillator OR internal 32kHz Oscillator
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# error Select EITHER external 32kHz oscillator OR internal 32kHz Oscillator
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#endif
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#ifndef XOSC0_FREQUENCY
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#define XOSC0_FREQUENCY (0)
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# define XOSC0_FREQUENCY (0)
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#endif
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#ifndef XOSC1_FREQUENCY
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#define XOSC1_FREQUENCY (0)
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# define XOSC1_FREQUENCY (0)
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#endif
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#define GCLK_SOURCE_ACTIVE_XOSC (XOSC0_FREQUENCY ? GCLK_SOURCE_XOSC0 : GCLK_SOURCE_XOSC1)
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#define GCLK_SOURCE_ACTIVE_XOSC \
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(XOSC0_FREQUENCY ? GCLK_SOURCE_XOSC0 : GCLK_SOURCE_XOSC1)
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#if USE_XOSC_ONLY /* don't use fast internal oscillators */
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#if (XOSC0_FREQUENCY == 0) && (XOSC1_FREQUENCY == 0)
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#error Configuration error: no external oscillator frequency defined
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#endif
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# if (XOSC0_FREQUENCY == 0) && (XOSC1_FREQUENCY == 0)
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# error Configuration error: no external oscillator frequency defined
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# endif
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#if (CLOCK_CORECLOCK > SAM0_XOSC_FREQ_HZ)
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#error When using an external oscillator for the main clock, the CPU frequency can't exceed it's frequency.
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#endif
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# if (CLOCK_CORECLOCK > SAM0_XOSC_FREQ_HZ)
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# error When using an external oscillator for the main clock, the CPU frequency can't exceed it's frequency.
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# endif
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#define USE_DPLL 0
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#define USE_DFLL 0
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#define USE_XOSC 1
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# define USE_DPLL 0
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# define USE_DFLL 0
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# define USE_XOSC 1
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#ifndef GCLK_TIMER_HZ
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#define GCLK_TIMER_HZ MHZ(4)
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#endif
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# ifndef GCLK_TIMER_HZ
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# define GCLK_TIMER_HZ MHZ(4)
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# endif
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#else /* !USE_XOSC_ONLY */
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/* Main clock > 48 MHz -> use DPLL, otherwise use DFLL */
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#define USE_DPLL (CLOCK_CORECLOCK > SAM0_DFLL_FREQ_HZ)
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#define USE_DFLL 1
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#define USE_XOSC 0
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# define USE_DPLL (CLOCK_CORECLOCK > SAM0_DFLL_FREQ_HZ)
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# define USE_DFLL 1
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# define USE_XOSC 0
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#ifndef GCLK_TIMER_HZ
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#define GCLK_TIMER_HZ MHZ(8)
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#endif
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# ifndef GCLK_TIMER_HZ
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# define GCLK_TIMER_HZ MHZ(8)
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# endif
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#endif /* USE_XOSC_ONLY */
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#if (CLOCK_CORECLOCK <= SAM0_DFLL_FREQ_HZ) && (SAM0_DFLL_FREQ_HZ % CLOCK_CORECLOCK)
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#error For frequencies <= 48 MHz, CLOCK_CORECLOCK must be a divider of 48 MHz
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# error For frequencies <= 48 MHz, CLOCK_CORECLOCK must be a divider of 48 MHz
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#endif
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/* If the CPU clock is lower than the minimal DPLL Freq
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set fDPLL = 2 * CLOCK_CORECLOCK */
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#if USE_DPLL && (CLOCK_CORECLOCK < SAM0_DPLL_FREQ_MIN_HZ)
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#define DPLL_DIV 2
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# define DPLL_DIV 2
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#else
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#define DPLL_DIV 1
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# define DPLL_DIV 1
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#endif
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static void xosc32k_init(void)
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@ -117,8 +117,8 @@ static void xosc_init(uint8_t idx)
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uint32_t freq;
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if (!USE_XOSC ||
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(idx == 0 && XOSC0_FREQUENCY == 0) ||
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(idx == 1 && XOSC1_FREQUENCY == 0)) {
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(idx == 0 && XOSC0_FREQUENCY == 0) ||
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(idx == 1 && XOSC1_FREQUENCY == 0)) {
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OSCCTRL->XOSCCTRL[idx].reg = 0;
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return;
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}
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@ -127,7 +127,8 @@ static void xosc_init(uint8_t idx)
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if (idx == 0) {
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freq = XOSC0_FREQUENCY;
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} else if (idx == 1) {
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}
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else if (idx == 1) {
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freq = XOSC1_FREQUENCY;
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}
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@ -143,17 +144,20 @@ static void xosc_init(uint8_t idx)
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reg |= OSCCTRL_XOSCCTRL_STARTUP(9)
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| OSCCTRL_XOSCCTRL_IMULT(3)
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| OSCCTRL_XOSCCTRL_IPTAT(2);
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} else if (freq <= MHZ(16)) {
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}
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else if (freq <= MHZ(16)) {
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/* 62000 cycles @ 16MHz = 3875 µs */
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reg |= OSCCTRL_XOSCCTRL_STARTUP(7)
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| OSCCTRL_XOSCCTRL_IMULT(4)
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| OSCCTRL_XOSCCTRL_IPTAT(3);
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} else if (freq <= MHZ(24)) {
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}
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else if (freq <= MHZ(24)) {
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/* 68500 cycles @ 24MHz = 2854 µs */
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reg |= OSCCTRL_XOSCCTRL_STARTUP(7)
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| OSCCTRL_XOSCCTRL_IMULT(5)
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| OSCCTRL_XOSCCTRL_IPTAT(3);
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} else {
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}
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else {
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/* 38500 cycles @ 48MHz = 802 µs */
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reg |= OSCCTRL_XOSCCTRL_STARTUP(5)
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| OSCCTRL_XOSCCTRL_IMULT(6)
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@ -168,9 +172,9 @@ static void dfll_init(void)
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{
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uint32_t reg = OSCCTRL_DFLLCTRLB_QLDIS
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#ifdef OSCCTRL_DFLLCTRLB_WAITLOCK
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| OSCCTRL_DFLLCTRLB_WAITLOCK
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| OSCCTRL_DFLLCTRLB_WAITLOCK
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#endif
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;
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;
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/* workaround for Errata 2.8.3 DFLLVAL.FINE Value When DFLL48M Re-enabled */
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OSCCTRL->DFLLMUL.reg = 0; /* Write new DFLLMULL configuration */
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@ -217,13 +221,18 @@ static void fdpll_init_nolock(uint8_t idx, uint32_t f_cpu, uint8_t flags)
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while (OSCCTRL->Dpll[idx].DPLLSYNCBUSY.reg) {}
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}
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static void fdpll_lock(uint8_t idx) {
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static void fdpll_lock(uint8_t idx)
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{
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const uint32_t flags = (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK);
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while (!((OSCCTRL->Dpll[idx].DPLLSTATUS.reg & flags) == flags)) {}
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}
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static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags) {
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GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src) | GCLK_GENCTRL_GENEN | flags | GCLK_GENCTRL_IDC;
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static void gclk_connect(uint8_t id, uint8_t src, uint32_t flags)
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{
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GCLK->GENCTRL[id].reg = GCLK_GENCTRL_SRC(src)
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| GCLK_GENCTRL_GENEN
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| flags
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| GCLK_GENCTRL_IDC;
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while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL(id)) {}
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}
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@ -238,11 +247,13 @@ void sam0_gclk_enable(uint8_t id)
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gclk_connect(SAM0_GCLK_TIMER,
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GCLK_SOURCE_DPLL0,
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GCLK_GENCTRL_DIV(DPLL_DIV * CLOCK_CORECLOCK / GCLK_TIMER_HZ));
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} else if (USE_DFLL) {
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}
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else if (USE_DFLL) {
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gclk_connect(SAM0_GCLK_TIMER,
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GCLK_SOURCE_DFLL,
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GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / GCLK_TIMER_HZ));
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} else if (USE_XOSC) {
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}
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else if (USE_XOSC) {
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gclk_connect(SAM0_GCLK_TIMER,
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GCLK_SOURCE_ACTIVE_XOSC,
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GCLK_GENCTRL_DIV(SAM0_XOSC_FREQ_HZ / GCLK_TIMER_HZ));
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@ -251,7 +262,8 @@ void sam0_gclk_enable(uint8_t id)
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case SAM0_GCLK_PERIPH:
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if (USE_DFLL) {
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gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_DFLL, 0);
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} else if (USE_XOSC) {
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}
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else if (USE_XOSC) {
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gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
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}
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break;
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@ -275,9 +287,11 @@ uint32_t sam0_gclk_freq(uint8_t id)
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case SAM0_GCLK_PERIPH:
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if (USE_DFLL) {
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return SAM0_DFLL_FREQ_HZ;
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} else if (USE_XOSC) {
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}
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else if (USE_XOSC) {
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return SAM0_XOSC_FREQ_HZ;
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} else {
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}
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else {
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assert(0);
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return 0;
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}
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@ -290,7 +304,7 @@ uint32_t sam0_gclk_freq(uint8_t id)
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void cpu_pm_cb_enter(int deep)
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{
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(void) deep;
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(void)deep;
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/* will be called before entering sleep */
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}
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@ -355,7 +369,8 @@ void cpu_init(void)
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xosc32k_init();
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if (EXTERNAL_OSC32_SOURCE) {
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gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_XOSC32K, 0);
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} else if (ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE) {
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}
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else if (ULTRA_LOW_POWER_INTERNAL_OSC_SOURCE) {
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gclk_connect(SAM0_GCLK_32KHZ, GCLK_SOURCE_OSCULP32K, 0);
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}
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@ -368,10 +383,12 @@ void cpu_init(void)
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DPLL0,
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GCLK_GENCTRL_DIV(DPLL_DIV));
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fdpll_lock(0);
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} else if (USE_DFLL) {
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}
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else if (USE_DFLL) {
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_DFLL,
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GCLK_GENCTRL_DIV(SAM0_DFLL_FREQ_HZ / CLOCK_CORECLOCK));
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} else if (USE_XOSC) {
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}
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else if (USE_XOSC) {
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gclk_connect(SAM0_GCLK_MAIN, GCLK_SOURCE_ACTIVE_XOSC,
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GCLK_GENCTRL_DIV(SAM0_XOSC_FREQ_HZ / CLOCK_CORECLOCK));
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}
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