From 20894e47a6e2bb9c70e8a1e414e682ed1d01908c Mon Sep 17 00:00:00 2001 From: Alexandre Abadie Date: Tue, 1 Sep 2020 16:20:58 +0200 Subject: [PATCH] cpu: boards: stm32gx: use IS_ACTIVE macro for clock config --- .../stm32/include/g0/cfg_clock_default.h | 54 ++++++++++--------- .../stm32/include/g4/cfg_clock_default.h | 54 ++++++++++--------- boards/nucleo-g070rb/include/periph_conf.h | 2 +- boards/nucleo-g071rb/include/periph_conf.h | 2 +- boards/nucleo-g431rb/include/periph_conf.h | 4 +- boards/nucleo-g474re/include/periph_conf.h | 4 +- cpu/stm32/stmclk/stmclk_gx.c | 12 ++--- 7 files changed, 68 insertions(+), 64 deletions(-) diff --git a/boards/common/stm32/include/g0/cfg_clock_default.h b/boards/common/stm32/include/g0/cfg_clock_default.h index 1437b3c266..2ba58cf4dd 100644 --- a/boards/common/stm32/include/g0/cfg_clock_default.h +++ b/boards/common/stm32/include/g0/cfg_clock_default.h @@ -37,50 +37,50 @@ extern "C" { /* Select the desired system clock source between PLL, HSE or HSI */ #ifndef CONFIG_USE_CLOCK_PLL #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CONFIG_USE_CLOCK_PLL (0) +#define CONFIG_USE_CLOCK_PLL 0 #else -#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ #endif #endif /* CONFIG_USE_CLOCK_PLL */ #ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE (0) +#define CONFIG_USE_CLOCK_HSE 0 #endif /* CONFIG_USE_CLOCK_HSE */ #ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI (0) +#define CONFIG_USE_CLOCK_HSI 0 #endif /* CONFIG_USE_CLOCK_HSI */ -#if CONFIG_USE_CLOCK_PLL && \ - (CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use PLL as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSE && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use HSE as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) #error "Cannot use HSI as clock source with other clock configurations" #endif #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (0) +#define CONFIG_BOARD_HAS_HSE 0 #endif #ifndef CLOCK_HSE #define CLOCK_HSE MHZ(24) #endif -#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) #error "HSE clock frequency must be between 4MHz and 48MHz" #endif #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (0) +#define CONFIG_BOARD_HAS_LSE 0 #endif -#if CONFIG_BOARD_HAS_LSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE) #define CLOCK_LSE (1) #else #define CLOCK_LSE (0) @@ -92,16 +92,12 @@ extern "C" { #define CONFIG_CLOCK_HSISYS_DIV (1) #endif -#if CONFIG_USE_CLOCK_HSI -#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) - -#elif CONFIG_USE_CLOCK_HSE -#if CONFIG_BOARD_HAS_HSE == 0 -#error "The board doesn't provide an HSE oscillator" +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) -#elif CONFIG_USE_CLOCK_PLL /* The following parameters configure a 64MHz system clock with HSI as input clock */ #ifndef CONFIG_CLOCK_PLL_M #define CONFIG_CLOCK_PLL_M (1) @@ -112,11 +108,17 @@ extern "C" { #ifndef CONFIG_CLOCK_PLL_R #define CONFIG_CLOCK_PLL_R (5) #endif -#if CONFIG_BOARD_HAS_HSE -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" #endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK \ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R #if CLOCK_CORECLOCK > MHZ(64) diff --git a/boards/common/stm32/include/g4/cfg_clock_default.h b/boards/common/stm32/include/g4/cfg_clock_default.h index 5235afae39..479d27fbe1 100644 --- a/boards/common/stm32/include/g4/cfg_clock_default.h +++ b/boards/common/stm32/include/g4/cfg_clock_default.h @@ -31,49 +31,49 @@ extern "C" { */ #ifndef CONFIG_USE_CLOCK_PLL #if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI) -#define CONFIG_USE_CLOCK_PLL (0) +#define CONFIG_USE_CLOCK_PLL 0 #else -#define CONFIG_USE_CLOCK_PLL (1) /* Use PLL by default */ +#define CONFIG_USE_CLOCK_PLL 1 /* Use PLL by default */ #endif #endif /* CONFIG_USE_CLOCK_PLL */ #ifndef CONFIG_USE_CLOCK_HSE -#define CONFIG_USE_CLOCK_HSE (0) +#define CONFIG_USE_CLOCK_HSE 0 #endif /* CONFIG_USE_CLOCK_HSE */ #ifndef CONFIG_USE_CLOCK_HSI -#define CONFIG_USE_CLOCK_HSI (0) +#define CONFIG_USE_CLOCK_HSI 0 #endif /* CONFIG_USE_CLOCK_HSI */ -#if CONFIG_USE_CLOCK_PLL && \ - (CONFIG_USE_CLOCK_HSE || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_PLL) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_HSE) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use PLL as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSE && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSI) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSI)) #error "Cannot use HSE as clock source with other clock configurations" #endif -#if CONFIG_USE_CLOCK_HSI && \ - (CONFIG_USE_CLOCK_PLL || CONFIG_USE_CLOCK_HSE) +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && \ + (IS_ACTIVE(CONFIG_USE_CLOCK_PLL) || IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) #error "Cannot use HSI as clock source with other clock configurations" #endif #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (0) +#define CONFIG_BOARD_HAS_HSE 0 #endif #ifndef CLOCK_HSE #define CLOCK_HSE MHZ(24) #endif -#if CONFIG_BOARD_HAS_HSE && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48)) #error "HSE clock frequency must be between 4MHz and 48MHz" #endif #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (0) +#define CONFIG_BOARD_HAS_LSE 0 #endif -#if CONFIG_BOARD_HAS_LSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_LSE) #define CLOCK_LSE (1) #else #define CLOCK_LSE (0) @@ -81,16 +81,12 @@ extern "C" { #define CLOCK_HSI MHZ(16) -#if CONFIG_USE_CLOCK_HSI -#define CLOCK_CORECLOCK (CLOCK_HSI) - -#elif CONFIG_USE_CLOCK_HSE -#if CONFIG_BOARD_HAS_HSE == 0 -#error "The board doesn't provide an HSE oscillator" +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#define CLOCK_PLL_SRC (CLOCK_HSE) +#else /* CLOCK_HSI */ +#define CLOCK_PLL_SRC (CLOCK_HSI) #endif -#define CLOCK_CORECLOCK (CLOCK_HSE) -#elif CONFIG_USE_CLOCK_PLL /* The following parameters configure a 170MHz system clock with HSI16 as input clock */ #ifndef CONFIG_CLOCK_PLL_M #define CONFIG_CLOCK_PLL_M (4) @@ -101,11 +97,17 @@ extern "C" { #ifndef CONFIG_CLOCK_PLL_R #define CONFIG_CLOCK_PLL_R (2) #endif -#if CONFIG_BOARD_HAS_HSE -#define CLOCK_PLL_SRC (CLOCK_HSE) -#else /* CLOCK_HSI */ -#define CLOCK_PLL_SRC (CLOCK_HSI) + +#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI) +#define CLOCK_CORECLOCK (CLOCK_HSI) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE) +#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE) +#error "The board doesn't provide an HSE oscillator" #endif +#define CLOCK_CORECLOCK (CLOCK_HSE) + +#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL) #define CLOCK_CORECLOCK \ ((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R #if CLOCK_CORECLOCK > MHZ(170) diff --git a/boards/nucleo-g070rb/include/periph_conf.h b/boards/nucleo-g070rb/include/periph_conf.h index 064a8eb811..8b9a172a82 100644 --- a/boards/nucleo-g070rb/include/periph_conf.h +++ b/boards/nucleo-g070rb/include/periph_conf.h @@ -23,7 +23,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "g0/cfg_clock_default.h" diff --git a/boards/nucleo-g071rb/include/periph_conf.h b/boards/nucleo-g071rb/include/periph_conf.h index f75364aab3..b506564604 100644 --- a/boards/nucleo-g071rb/include/periph_conf.h +++ b/boards/nucleo-g071rb/include/periph_conf.h @@ -21,7 +21,7 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif #include "g0/cfg_clock_default.h" diff --git a/boards/nucleo-g431rb/include/periph_conf.h b/boards/nucleo-g431rb/include/periph_conf.h index 6f91a68d66..752d9f9fca 100644 --- a/boards/nucleo-g431rb/include/periph_conf.h +++ b/boards/nucleo-g431rb/include/periph_conf.h @@ -21,11 +21,11 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif /* This board provides a 24MHz HSE oscillator */ #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (1) +#define CONFIG_BOARD_HAS_HSE 1 #endif /* By default, configure a 170MHz SYSCLK with PLL using HSE as input clock */ #ifndef CONFIG_CLOCK_PLL_M diff --git a/boards/nucleo-g474re/include/periph_conf.h b/boards/nucleo-g474re/include/periph_conf.h index d82bc1ccc1..f291b9189e 100644 --- a/boards/nucleo-g474re/include/periph_conf.h +++ b/boards/nucleo-g474re/include/periph_conf.h @@ -21,11 +21,11 @@ /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE -#define CONFIG_BOARD_HAS_LSE (1) +#define CONFIG_BOARD_HAS_LSE 1 #endif /* This board provides a 24MHz HSE oscillator */ #ifndef CONFIG_BOARD_HAS_HSE -#define CONFIG_BOARD_HAS_HSE (1) +#define CONFIG_BOARD_HAS_HSE 1 #endif /* By default, configure a 80MHz SYSCLK with PLL using HSE as input clock */ #ifndef CONFIG_CLOCK_PLL_M diff --git a/cpu/stm32/stmclk/stmclk_gx.c b/cpu/stm32/stmclk/stmclk_gx.c index 2ea7ab8a45..ed7bfe8447 100644 --- a/cpu/stm32/stmclk/stmclk_gx.c +++ b/cpu/stm32/stmclk/stmclk_gx.c @@ -57,7 +57,7 @@ #define PLL_R (((CONFIG_CLOCK_PLL_R >> 1) - 1) << RCC_PLLCFGR_PLLR_Pos) #endif -#if CONFIG_BOARD_HAS_HSE +#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) #define PLL_IN CLOCK_HSE #define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE #else @@ -187,14 +187,14 @@ void stmclk_init_sysclk(void) RCC->CR = RCC_CR_HSION; #if defined(CPU_FAM_STM32G0) - if (CONFIG_USE_CLOCK_HSI && CONFIG_CLOCK_HSISYS_DIV != 1) { + if (IS_ACTIVE(CONFIG_USE_CLOCK_HSI) && CONFIG_CLOCK_HSISYS_DIV != 1) { /* configure HSISYS divider, only available on G0 */ RCC->CR |= CLOCK_HSI_DIV; while (!(RCC->CR & RCC_CR_HSIRDY)) {} } #endif - if (CONFIG_USE_CLOCK_HSE) { + if (IS_ACTIVE(CONFIG_USE_CLOCK_HSE)) { /* if configured, we need to enable the HSE clock now */ RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR & RCC_CR_HSERDY)) {} @@ -206,8 +206,8 @@ void stmclk_init_sysclk(void) #endif while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSE) {} } - else if (CONFIG_USE_CLOCK_PLL) { - if (CONFIG_BOARD_HAS_HSE) { + else if (IS_ACTIVE(CONFIG_USE_CLOCK_PLL)) { + if (IS_ACTIVE(CONFIG_BOARD_HAS_HSE)) { /* if configured, we need to enable the HSE clock now */ RCC->CR |= RCC_CR_HSEON; while (!(RCC->CR & RCC_CR_HSERDY)) {} @@ -252,7 +252,7 @@ void stmclk_init_sysclk(void) if (IS_USED(MODULE_PERIPH_RTT)) { /* Ensure LPTIM1 clock source (LSI or LSE) is correctly reset when initializing the clock, this is particularly useful after waking up from deep sleep */ - if (CONFIG_BOARD_HAS_LSE) { + if (IS_ACTIVE(CONFIG_BOARD_HAS_LSE)) { RCC->CCIPR |= RCC_CCIPR_LPTIM1SEL_0 | RCC_CCIPR_LPTIM1SEL_1; } else {