boards/lora-e5-dev: initial support

boards/lora-e5-dev/Kconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2021 Inria
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config BOARD
+    default "lora-e5-dev" if BOARD_LORA_E5_DEV
+
+config BOARD_LORA_E5_DEV
+    bool
+    default y
+    select CPU_MODEL_STM32WLE5JC
+
+    # Put defined MCU peripherals here (in alphabetical order)
+    select HAS_PERIPH_I2C
+    select HAS_PERIPH_LPUART
+    select HAS_PERIPH_RTT
+    select HAS_PERIPH_SPI
+    select HAS_PERIPH_TIMER
+    select HAS_PERIPH_UART
+
+    # Put other features for this board (in alphabetical order)
+    select HAS_RIOTBOOT

boards/lora-e5-dev/Makefile

@@ -0,0 +1,3 @@
+MODULE = board
+
+include $(RIOTBASE)/Makefile.base

boards/lora-e5-dev/Makefile.dep

@@ -0,0 +1,9 @@
+ifneq (,$(filter netdev_default,$(USEMODULE)))
+  USEMODULE += sx126x_stm32wl
+endif
+ifneq (,$(filter sx126x_stm32wl,$(USEMODULE)))
+  USEMODULE += sx126x_rf_switch
+endif
+ifneq (,$(filter saul_default,$(USEMODULE)))
+  USEMODULE += saul_gpio
+endif

boards/lora-e5-dev/Makefile.features

@@ -0,0 +1,13 @@
+CPU = stm32
+CPU_MODEL = stm32wle5jc
+
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_i2c
+FEATURES_PROVIDED += periph_lpuart
+FEATURES_PROVIDED += periph_rtt
+FEATURES_PROVIDED += periph_spi
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Put other features for this board (in alphabetical order)
+FEATURES_PROVIDED += riotboot

boards/lora-e5-dev/Makefile.include

@@ -0,0 +1,9 @@
+# we use shared STM32 configuration snippets
+INCLUDES += -I$(RIOTBOARD)/common/stm32/include
+
+# define the default port depending on the host OS
+PORT_LINUX ?= /dev/ttyUSB0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
+
+# Setup of programmer and serial is shared between STM32 based boards
+include $(RIOTMAKE)/boards/stm32.inc.mk

boards/lora-e5-dev/board.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2021 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_lora-e5-dev
+ * @{
+ *
+ * @file
+ * @brief       Board specific implementations for the LoRa-E5 Development Board - STM32WLE5JC board
+ *
+ * @author      Francisco Molina <francois-xavier.molina@inria/fr>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "board.h"
+#include "periph/gpio.h"
+
+#if IS_USED(MODULE_SX126X_STM32WL)
+#include "sx126x.h"
+#endif
+
+void board_init(void)
+{
+    /* initialize the CPU */
+    cpu_init();
+    /* initialization of on-board LEDs */
+#ifdef AUTO_INIT_LED0
+    gpio_init(LED0_PIN, GPIO_OUT);
+    LED0_OFF;
+#endif
+
+    if (IS_USED(MODULE_SX126X_STM32WL)) {
+        /* Initialize the GPIO control for RF 3-port switch (SP3T) */
+        gpio_init(FE_CTRL1, GPIO_OUT);
+        gpio_init(FE_CTRL2, GPIO_OUT);
+    }
+}
+
+#if IS_USED(MODULE_SX126X_STM32WL)
+/**
+ * @brief Callback to set RF switch mode
+ *
+ * This function sets the GPIO's wired to the SP3T RF Switch. LoRa-E5-dev
+ * supports two modes of operation.
+ */
+void lora_e5_dev_sx126x_set_rf_mode(sx126x_t *dev, sx126x_rf_mode_t rf_mode)
+{
+    (void) dev;
+    switch (rf_mode) {
+    case SX126X_RF_MODE_RX:
+        gpio_set(FE_CTRL1);
+        gpio_clear(FE_CTRL2);
+        break;
+    case SX126X_RF_MODE_TX_HPA:
+        gpio_clear(FE_CTRL1);
+        gpio_set(FE_CTRL2);
+        break;
+    default:
+        break;
+    }
+}
+#endif

boards/lora-e5-dev/dist/openocd.cfg

@@ -0,0 +1,3 @@
+source [find target/stm32wlx.cfg]
+reset_config trst_only
+$_TARGETNAME configure -rtos auto

boards/lora-e5-dev/doc.txt

@@ -0,0 +1,64 @@
+/**
+ * @defgroup    boards_lora-e5-dev LoRa-E5 Development Board - STM32WLE5JC
+ * @ingroup     boards
+ * @brief       Support for the LoRa-E5 Development Board - STM32WLE5JC board.
+ *
+ *
+ *  ### MCU
+ *
+ * | MCU        |   STM32WL5EJC                                             |
+ * |:---------- |:--------------------------------------------------------- |
+ * | Family     | ARM Cortex-M4                                             |
+ * | Vendor     | ST Microelectronics                                       |
+ * | RAM        | 64KiB                                                     |
+ * | Flash      | 256KiB                                                    |
+ * | Frequency  | up to 48MHz                                               |
+ * | FPU        | no                                                        |
+ * | Vcc        | 1.8 V - 3.6V                                              |
+ * | Datasheet  | [Datasheet](https://files.seeedstudio.com/products/317990687/res/STM32WLE5JC%20Datasheet.pdf) |
+ * | Reference Manual | [Reference Manual](https://www.st.com/resource/en/reference_manual/rm0461-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf) |
+ * | Board Manual   | [Board Manual](https://www.st.com/resource/en/data_brief/nucleo-wl55jc.pdf) |
+ * | Board Schematic | [Board Schematic](https://files.seeedstudio.com/products/113990934/LoRa-E5%20Dev%20Board%20v1.0.pdf) |
+ * | LoRa-E5 STM32WL5EJC Module wiki | https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/#2-develop-with-stm32cube-mcu-package |
+ *
+ *
+ * ### Pinout
+ *
+ * ![lora-e5-dev](https://files.seeedstudio.com/wiki/LoRa-E5_Development_Kit/hardware%20overview/4071615359366_.pic_hd.jpg)
+ *
+ * ### User Interface
+ *
+ * 3 Buttons:
+ *
+ * | NAME   | BOOT     | D0        | RESET |
+ * |:------ |:---------|:--------- |:----- |
+ * | Pin    | PA0 (IN) | PB13 (IN) | NRST  |
+ *
+ * 1 LED:
+ *
+ * | NAME   | D5    |
+ * | -----  | ----- |
+ * | Color  | red   |
+ * | Pin    | PB5   |
+ *
+ * ### Flash the board
+ *
+ * The BOARD comes pre-flashed with a Factory AT Firmware with RDP (Read Protection)
+ * level 1, this needs to be removed to enable subsequent flashing. The easiest
+ * way is with STM32CubeProgramer as described in [seedstudio wiki](https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/#2-develop-with-stm32cube-mcu-package).
+ *
+ * Once read protection is removed subsequent flashing can be performed with and
+ * attached ST-LINK on the SWD pins (do not connect RST but only GND, SWCLK and SWDIO).
+ *
+ * ```
+ * BOARD=lora-e5-dev make flash
+ * ```
+ *
+ * The default used programmer is OpenOCD.
+ *
+ * ### Serial connection
+ *
+ * The default serial connection is through the USB-C port mapping to PB7 (RX) and
+ * PB6 (TX) UART pins (a second UART and an LPUART interface is also exposed).
+ *
+ */

boards/lora-e5-dev/include/board.h

@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2021 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_lora-e5-dev
+ * @{
+ *
+ * @file
+ * @brief       Pin definitions and board configuration options for
+ *              LoRa-E5 Development Board
+ *
+ * @author      Francisco Molina <francois-xavier.molina@inria.yyfr>
+ */
+
+#ifndef BOARD_H
+#define BOARD_H
+
+#include "kernel_defines.h"
+#if IS_USED(MODULE_SX126X_STM32WL)
+#include "sx126x.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Sub-GHz radio (LoRa) configuration
+ * @{
+ */
+#define SX126X_PARAM_SPI                    (SPI_DEV(0))
+#if IS_USED(MODULE_SX126X_STM32WL)
+extern void lora_e5_dev_sx126x_set_rf_mode(sx126x_t *dev, sx126x_rf_mode_t rf_mode);
+#define SX126X_PARAM_SET_RF_MODE_CB         lora_e5_dev_sx126x_set_rf_mode
+#define SX126X_PARAM_TYPE                   SX126X_TYPE_STM32WL
+#endif
+/** @} */
+
+/**
+ * @name    LED pin definitions and handlers
+ * @{
+ */
+#define LED0_PORT           GPIOB
+#define LED0_PIN            GPIO_PIN(PORT_B, 5)
+#define LED0_MASK           (1 << 5)
+#define LED0_OFF            (LED0_PORT->BSRR = LED0_MASK)
+#define LED0_ON             (LED0_PORT->BSRR = (LED0_MASK << 5))
+#define LED0_TOGGLE         (LED0_PORT->ODR  ^= LED0_MASK)
+/** @} */
+
+/**
+ * @brief   Lora-E5-Dev always use LED0, as there is no dual use of its pin
+ * @{
+ */
+#ifndef AUTO_INIT_LED0
+#define AUTO_INIT_LED0
+#endif
+/** @} */
+
+/**
+ * @name    User button
+ * @{
+ */
+#define BTN0_PIN            GPIO_PIN(PORT_B, 13)
+#define BTN0_MODE           GPIO_IN_PU
+#define BTN1_PIN            GPIO_PIN(PORT_A, 0)
+#define BTN1_MODE           GPIO_IN_PU
+/** @} */
+
+/**
+ * @name    RF 3-port switch (SP3T) control
+ *
+ * Refer Section 6.6.3 RF Overview in User Manual (UM2592)
+ * @{
+ */
+#define FE_CTRL1            GPIO_PIN(PORT_A, 4)
+#define FE_CTRL2            GPIO_PIN(PORT_A, 5)
+/** @} */
+
+/**
+ * @brief   Board level initialization
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* BOARD_H */
+/** @} */

boards/lora-e5-dev/include/gpio_params.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2021 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_lora-e5-dev
+ * @{
+ *
+ * @file
+ * @brief       Board specific configuration of direct mapped GPIOs
+ *
+ * @author      Francisco Molina <francois-xavier.molina@inria.fr>
+ *
+ */
+
+#ifndef GPIO_PARAMS_H
+#define GPIO_PARAMS_H
+
+#include "board.h"
+#include "saul/periph.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief    GPIO pin configuration
+ */
+static const  saul_gpio_params_t saul_gpio_params[] =
+{
+#ifdef AUTO_INIT_LED0
+    {
+        .name = "LED(red)",
+        .pin = LED0_PIN,
+        .mode = GPIO_OUT
+    },
+#endif
+    {
+        .name = "Button(B1 Boot)",
+        .pin  = BTN0_PIN,
+        .mode = BTN0_MODE,
+        .flags = SAUL_GPIO_INVERTED,
+    },
+    {
+        .name = "Button(B2 D0)",
+        .pin  = BTN1_PIN,
+        .mode = BTN1_MODE,
+        .flags = SAUL_GPIO_INVERTED,
+    },
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO_PARAMS_H */
+/** @} */

boards/lora-e5-dev/include/periph_conf.h

@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2021 Inria
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_lora-e5-dev
+ * @{
+ *
+ * @file
+ * @brief       Peripheral MCU configuration for the LoRa-E5 Development Board
+ *
+ * @author      Francisco Molina <francois-xavier.molina@inria.fr>
+ *
+ */
+
+#ifndef PERIPH_CONF_H
+#define PERIPH_CONF_H
+
+/* Add specific clock configuration (HSE, LSE) for this board here */
+#ifndef CONFIG_BOARD_HAS_LSE
+#define CONFIG_BOARD_HAS_LSE            1
+#endif
+
+/* This board provides a 32MHz HSE oscillator  */
+#ifndef CONFIG_BOARD_HAS_HSE
+#define CONFIG_BOARD_HAS_HSE            1
+#endif
+
+#define CLOCK_HSE                       MHZ(32)
+
+#include "periph_cpu.h"
+#include "clk_conf.h"
+#include "cfg_rtt_default.h"
+#include "cfg_timer_tim2.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+   {
+        .dev        = USART1,
+        .rcc_mask   = RCC_APB2ENR_USART1EN,
+        .rx_pin     = GPIO_PIN(PORT_B, 7),
+        .tx_pin     = GPIO_PIN(PORT_B, 6),
+        .rx_af      = GPIO_AF7,
+        .tx_af      = GPIO_AF7,
+        .bus        = APB2,
+        .irqn       = USART1_IRQn,
+        .type       = STM32_USART,
+        .clk_src    = 0, /* Use APB clock */
+    },
+    {
+        .dev        = USART2,
+        .rcc_mask   = RCC_APB1ENR1_USART2EN,
+        .rx_pin     = GPIO_PIN(PORT_A, 3),
+        .tx_pin     = GPIO_PIN(PORT_A, 2),
+        .rx_af      = GPIO_AF7,
+        .tx_af      = GPIO_AF7,
+        .bus        = APB1,
+        .irqn       = USART2_IRQn,
+        .type       = STM32_USART,
+        .clk_src    = 0, /* Use APB clock */
+    },
+    {
+        .dev        = LPUART1,
+        .rcc_mask   = RCC_APB1ENR2_LPUART1EN,
+        .rx_pin     = GPIO_PIN(PORT_C, 1),
+        .tx_pin     = GPIO_PIN(PORT_C, 0),
+        .rx_af      = GPIO_AF8,
+        .tx_af      = GPIO_AF8,
+        .bus        = APB12,
+        .irqn       = LPUART1_IRQn,
+        .type       = STM32_LPUART,
+        .clk_src    = 0, /* Use APB clock */
+    },
+};
+
+#define UART_0_ISR          isr_usart1
+#define UART_1_ISR          isr_usart2
+#define UART_2_ISR          isr_lpuart1
+
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
+/** @} */
+/**
+ * @name    SPI configuration
+ * @{
+ */
+static const spi_conf_t spi_config[] = {
+    {
+        .dev      = SUBGHZSPI, /* Internally connected to Sub-GHz radio Modem  */
+        .mosi_pin = GPIO_UNDEF,
+        .miso_pin = GPIO_UNDEF,
+        .sclk_pin = GPIO_UNDEF,
+        .cs_pin   = GPIO_UNDEF,
+        .mosi_af  = GPIO_AF_UNDEF,
+        .miso_af  = GPIO_AF_UNDEF,
+        .sclk_af  = GPIO_AF_UNDEF,
+        .cs_af    = GPIO_AF_UNDEF,
+        .rccmask  = RCC_APB3ENR_SUBGHZSPIEN,
+        .apbbus   = APB3,
+    },
+/* SUBGHZ DEBUG PINS use the SPI1 pins */
+#if !IS_ACTIVE(CONFIG_STM32_WLX5XX)
+    {
+        .dev      = SPI2,
+        .mosi_pin = GPIO_PIN(PORT_A, 10),
+        .miso_pin = GPIO_PIN(PORT_B, 14),
+        .sclk_pin = GPIO_PIN(PORT_B, 13),
+        .cs_pin   = GPIO_UNDEF,
+        .mosi_af  = GPIO_AF5,
+        .miso_af  = GPIO_AF5,
+        .sclk_af  = GPIO_AF5,
+        .cs_af    = GPIO_AF5,
+        .rccmask  = RCC_APB1ENR1_SPI2EN,
+        .apbbus   = APB1,
+    }
+#endif
+};
+
+#define SPI_NUMOF           ARRAY_SIZE(spi_config)
+/** @} */
+
+/**
+ * @name    I2C configuration
+ * @{
+ */
+static const i2c_conf_t i2c_config[] = {
+    {
+        .dev            = I2C2,
+        .speed          = I2C_SPEED_NORMAL,
+        .scl_pin        = GPIO_PIN(PORT_B, 15),
+        .sda_pin        = GPIO_PIN(PORT_A, 15),
+        .scl_af         = GPIO_AF4,
+        .sda_af         = GPIO_AF4,
+        .bus            = APB1,
+        .rcc_mask       = RCC_APB1ENR1_I2C2EN,
+        .irqn           = I2C2_ER_IRQn,
+    }
+};
+
+#define I2C_1_ISR           isr_i2c2_er
+
+#define I2C_NUMOF           ARRAY_SIZE(i2c_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_CONF_H */
+/** @} */

tests/unittests/Makefile.ci

@@ -46,6 +46,7 @@ BOARD_INSUFFICIENT_MEMORY := \
     im880b \
     limifrog-v1 \
     lobaro-lorabox \
+    lora-e5-dev \
     lsn50 \
     maple-mini \
     mcb2388 \