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https://github.com/RIOT-OS/RIOT.git
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cpu/nrf9160: add TWI and SPI support
This commit is contained in:
dylad
parent
a59974cf69
commit
1beda0f1e4
@ -1,3 +1,17 @@
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MODULE = nrf5x_common_periph
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# Select the specific implementation for `periph_i2c`
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ifneq (,$(filter periph_i2c,$(USEMODULE)))
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ifneq (,$(filter $(CPU_FAM),nrf52 nrf9160))
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SRC += i2c_nrf52_nrf9160.c
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endif
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endif
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# Select the specific implementation for `periph_spi`
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ifneq (,$(filter periph_spi,$(USEMODULE)))
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ifneq (,$(filter $(CPU_FAM),nrf52 nrf9160))
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SRC += spi_nrf52_nrf9160.c
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endif
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endif
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include $(RIOTMAKE)/periph.mk
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@ -9,7 +9,7 @@
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*/
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/**
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* @ingroup cpu_nrf52
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* @ingroup cpu_nrf5x_common
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* @{
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*
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* @file
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@ -9,7 +9,7 @@
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*/
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/**
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* @ingroup cpu_nrf52
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* @ingroup cpu_nrf5x_common
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* @ingroup drivers_periph_spi
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* @{
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*
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@ -81,7 +81,133 @@ typedef struct {
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#define UART_BAUDRATE_BAUDRATE_Baud460800 UARTE_BAUDRATE_BAUDRATE_Baud460800
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#define UART_BAUDRATE_BAUDRATE_Baud921600 UARTE_BAUDRATE_BAUDRATE_Baud921600
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#define UART_BAUDRATE_BAUDRATE_Baud1M UARTE_BAUDRATE_BAUDRATE_Baud1M
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/**
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* @brief Override I2C speed settings
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 0xff, /**< not supported */
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I2C_SPEED_NORMAL = TWIM_FREQUENCY_FREQUENCY_K100, /**< 100kbit/s */
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I2C_SPEED_FAST = TWIM_FREQUENCY_FREQUENCY_K400, /**< 400kbit/s */
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I2C_SPEED_FAST_PLUS = 0xfe, /**< not supported */
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I2C_SPEED_HIGH = 0xfd, /**< not supported */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C (TWI) configuration options
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*/
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typedef struct {
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NRF_TWIM_Type *dev; /**< TWIM hardware device */
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gpio_t scl; /**< SCL pin */
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gpio_t sda; /**< SDA pin */
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i2c_speed_t speed; /**< Bus speed */
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} i2c_conf_t;
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/** @} */
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_WRITE_REG
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/** @} */
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/**
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* @name Define macros for sda and scl pin to be able to reinitialize them
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* @{
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*/
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#define i2c_pin_sda(dev) i2c_config[dev].sda
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#define i2c_pin_scl(dev) i2c_config[dev].scl
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/** @} */
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/**
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* @brief Defines macros for SPI pins initialization
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* @{
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*/
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#define SPI_SCKSEL (dev(bus)->PSEL.SCK)
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#define SPI_MOSISEL (dev(bus)->PSEL.MOSI)
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#define SPI_MISOSEL (dev(bus)->PSEL.MISO)
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/** @} */
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/**
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* @brief SPI temporary buffer size for storing const data in RAM before
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* initiating DMA transfer
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*/
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#ifndef CONFIG_SPI_MBUF_SIZE
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#define CONFIG_SPI_MBUF_SIZE 64
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#endif
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/**
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* @brief SPI configuration values
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*/
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typedef struct {
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NRF_SPIM_Type *dev; /**< SPI device used */
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gpio_t sclk; /**< CLK pin */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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} spi_conf_t;
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#ifndef DOXYGEN
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/**
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* @brief Override SPI mode values
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = 0, /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = SPIM_CONFIG_CPHA_Msk, /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = SPIM_CONFIG_CPOL_Msk, /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = (SPIM_CONFIG_CPOL_Msk | SPIM_CONFIG_CPHA_Msk) /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @} */
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/**
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* @brief Override SPI clock values
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = SPIM_FREQUENCY_FREQUENCY_K125, /**< 100KHz */
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SPI_CLK_400KHZ = SPIM_FREQUENCY_FREQUENCY_K500, /**< 400KHz */
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SPI_CLK_1MHZ = SPIM_FREQUENCY_FREQUENCY_M1, /**< 1MHz */
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SPI_CLK_5MHZ = SPIM_FREQUENCY_FREQUENCY_M4, /**< 5MHz */
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SPI_CLK_10MHZ = SPIM_FREQUENCY_FREQUENCY_M8 /**< 10MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Common SPI/I2C interrupt callback
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*
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* @param arg Opaque context pointer
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*/
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typedef void (*spi_twi_irq_cb_t)(void *arg);
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/**
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* @brief Reqister a SPI IRQ handler for a shared I2C/SPI irq vector
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*
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* @param bus bus to register the IRQ handler on
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* @param cb callback to call on IRQ
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* @param arg Argument to pass to the handler
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*/
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void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg);
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/**
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* @brief Reqister a I2C IRQ handler for a shared I2C/SPI irq vector
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*
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* @param bus bus to register the IRQ handler on
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* @param cb callback to call on IRQ
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* @param arg Argument to pass to the handler
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*/
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void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg);
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#ifdef __cplusplus
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}
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#endif
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122
cpu/nrf9160/spi_twi_irq.c
Normal file
122
cpu/nrf9160/spi_twi_irq.c
Normal file
@ -0,0 +1,122 @@
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/*
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* Copyright (C) 2021 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf9160
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* @{
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*
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* @file
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* @brief Shared IRQ handling between SPI and TWI peripherals on the nRF52
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* devices
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*
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* I2C is called TWI (Two Wire Interface) in the datasheets from Nordic
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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* @}
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*/
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#include <assert.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#include "periph_conf.h"
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static spi_twi_irq_cb_t _irq[TWIM_COUNT];
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static void *_irq_arg[TWIM_COUNT];
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#if TWIM_COUNT != SPIM_COUNT
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#error Possible configuration issue, please update this file
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#endif
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/* I2C and SPI share peripheral addresses */
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static size_t _spi_dev2num(void *dev)
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{
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if (dev == NRF_SPIM0_S) {
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return 0;
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}
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else if (dev == NRF_SPIM1_S) {
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return 1;
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}
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else if (dev == NRF_SPIM2_S) {
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return 2;
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}
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else if (dev == NRF_SPIM3_S) {
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return 3;
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}
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else {
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assert(false);
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return 0;
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}
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}
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static inline size_t _i2c_dev2num(void *dev)
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{
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return _spi_dev2num(dev);
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}
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static const IRQn_Type _isr[] = {
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UARTE0_SPIM0_SPIS0_TWIM0_TWIS0_IRQn,
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UARTE1_SPIM1_SPIS1_TWIM1_TWIS1_IRQn,
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UARTE2_SPIM2_SPIS2_TWIM2_TWIS2_IRQn,
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UARTE3_SPIM3_SPIS3_TWIM3_TWIS3_IRQn
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};
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void spi_twi_irq_register_spi(NRF_SPIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _spi_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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void spi_twi_irq_register_i2c(NRF_TWIM_Type *bus,
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spi_twi_irq_cb_t cb, void *arg)
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{
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size_t num = _i2c_dev2num(bus);
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_irq[num] = cb;
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_irq_arg[num] = arg;
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NVIC_EnableIRQ(_isr[num]);
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}
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/* Check if UART driver doesn't already use the same IRQ */
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#ifndef UART_0_ISR
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void isr_uarte0_spim0_spis0_twim0_twis0(void)
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{
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_irq[0](_irq_arg[0]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_0_ISR */
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#ifndef UART_1_ISR
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void isr_uarte1_spim1_spis1_twim1_twis1(void)
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{
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_irq[1](_irq_arg[1]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_1_ISR */
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#ifndef UART_2_ISR
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void isr_uarte2_spim2_spis2_twim2_twis2(void)
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{
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_irq[2](_irq_arg[2]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_2_ISR */
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#ifndef UART_3_ISR
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void isr_uarte3_spim3_spis3_twim3_twis3(void)
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{
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_irq[3](_irq_arg[3]);
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cortexm_isr_end();
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}
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#endif /* ndef UART_3_ISR */
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