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Merge pull request #2222 from haukepetersen/fix_lpc1768_uartclk

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cpu/lpc1768: fixed UART PCLK selection
This commit is contained in:
Hauke Petersen 2014-12-19 14:21:08 +01:00
commit 1bd63978a8
2 changed files with 6 additions and 7 deletions
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2
boards/mbed_lpc1768/include/periph_conf.h
View File

@ -54,6 +54,7 @@ extern "C" {
/* UART 0 device configuration */
#define UART_0_DEV LPC_UART0
#define UART_0_CLKSEL() (LPC_SC->PCLKSEL0 &= ~(0x3 << 6)) /* PCLK := CCLK / 4 */
#define UART_0_CLKEN() (LPC_SC->PCONP |= (1 << 3))
#define UART_0_CLKDIS() (LPC_SC->PCONP &= ~(1 << 3))
#define UART_0_IRQ UART0_IRQn
@ -69,6 +70,7 @@ extern "C" {
/* UART 1 device configuration */
#define UART_1_DEV LPC_UART3
#define UART_1_CLKSEL() (LPC_SC->PCLKSEL1 &= ~(0x3 << 18)) /* PCLK := CCLK / 4 */
#define UART_1_CLKEN() (LPC_SC->PCONP |= (1 << 25))
#define UART_1_CLKDIS() (LPC_SC->PCONP &= ~(1 << 25))
#define UART_1_IRQ UART3_IRQn

11
cpu/lpc1768/periph/uart.c
View File

@ -88,11 +88,9 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
return -2;
}
/* power on UART device */
/* power on UART device and select peripheral clock */
UART_0_CLKEN();
/* set peripheral clock to CCLK / 4 */
LPC_SC->PCLKSEL1 &= (0x3 << 18);
UART_0_CLKSEL();
/* set mode to 8N1 and enable access to divisor latch */
UART_0_DEV->LCR = ((0x3 << 0) | (1 << 7));
/* set baud rate registers (fixed for now) */
@ -121,10 +119,9 @@ int uart_init_blocking(uart_t uart, uint32_t baudrate)
return -2;
}
/* power on UART device */
/* power on UART device and select peripheral clock */
UART_1_CLKEN();
/* set peripheral clock to CCLK / 4 */
LPC_SC->PCLKSEL1 &= (0x3 << 18);
UART_1_CLKSEL();
/* set mode to 8N1 and enable access to divisor latch */
UART_1_DEV->LCR = ((0x3 << 0) | (1 << 7));
/* set baud rate registers (fixed for now) */