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Merge pull request #9724 from smlng/pr/cc2538/spi_clk

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cpu/cc2538: generalise SPI clock configuration
This commit is contained in:
Kevin Weiss 2018-08-07 14:33:05 +02:00 committed by GitHub
commit 1bbd7fcd62
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7 changed files with 17 additions and 89 deletions
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15
boards/cc2538dk/include/periph_conf.h
View File

@ -97,21 +97,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{

14
boards/openmote-b/include/periph_conf.h
View File

@ -124,20 +124,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq),
* where 1 < CPSR < 255 and 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{

15
boards/openmote-cc2538/include/periph_conf.h
View File

@ -120,21 +120,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{

15
boards/remote-pa/include/periph_conf.h
View File

@ -45,21 +45,6 @@ static const i2c_conf_t i2c_config[] = {
#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
/** @} */
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
/**
* @name SPI configuration
* @{

15
boards/remote-reva/include/periph_conf.h
View File

@ -49,21 +49,6 @@ static const i2c_conf_t i2c_config[] = {
* @name SPI configuration
* @{
*/
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,

15
boards/remote-revb/include/periph_conf.h
View File

@ -52,21 +52,6 @@ static const i2c_conf_t i2c_config[] = {
* @name SPI configuration
* @{
*/
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* Calculated with (CPSR * (SCR + 1)) = (CLOCK_CORECLOCK / bus_freq), where
* 1 < CPSR < 255 and
* 0 < SCR < 256
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 10, .scr = 31 }, /* 100khz */
{ .cpsr = 2, .scr = 39 }, /* 400khz */
{ .cpsr = 2, .scr = 15 }, /* 1MHz */
{ .cpsr = 2, .scr = 2 }, /* ~4.5MHz */
{ .cpsr = 2, .scr = 1 } /* ~10.7MHz */
};
static const spi_conf_t spi_config[] = {
{
.dev = SSI0,

17
cpu/cc2538/include/periph_cpu.h
View File

@ -195,6 +195,23 @@ typedef struct {
uint8_t scr; /**< SCR clock divider */
} spi_clk_conf_t;
#ifndef BOARD_HAS_SPI_CLK_CONF
/**
* @brief Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
*
* SPI bus frequency = CLOCK_CORECLOCK / (CPSR * (SCR + 1)), with
* CPSR = 2..254 and even,
* SCR = 0..255
*/
static const spi_clk_conf_t spi_clk_config[] = {
{ .cpsr = 64, .scr = 4 }, /* 100khz */
{ .cpsr = 16, .scr = 4 }, /* 400khz */
{ .cpsr = 32, .scr = 0 }, /* 1.0MHz */
{ .cpsr = 2, .scr = 2 }, /* 5.3MHz */
{ .cpsr = 2, .scr = 1 } /* 8.0MHz */
};
#endif /* BOARD_HAS_SPI_CLK_CONF */
/**
* @name SPI configuration data structure
* @{