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https://github.com/RIOT-OS/RIOT.git
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drivers: encx24j600: prefix constants
This commit is contained in:
parent
d9d5d88b26
commit
1ac0ab6905
@ -112,15 +112,15 @@ static void _isr(netdev2_t *netdev)
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uint16_t eir;
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lock(dev);
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cmd(dev, CLREIE);
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cmd(dev, ENC_CLREIE);
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eir = reg_get(dev, EIR);
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eir = reg_get(dev, ENC_EIR);
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/* check & handle link state change */
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if (eir & LINKIF) {
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uint16_t estat = reg_get(dev, ESTAT);
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if (eir & ENC_LINKIF) {
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uint16_t estat = reg_get(dev, ENC_ESTAT);
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netdev2_event_t event = (estat & PHYLNK) ?
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netdev2_event_t event = (estat & ENC_PHYLNK) ?
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NETDEV2_EVENT_LINK_DOWN :
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NETDEV2_EVENT_LINK_UP;
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@ -128,7 +128,7 @@ static void _isr(netdev2_t *netdev)
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}
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/* check & handle available packets */
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if (eir & PKTIF) {
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if (eir & ENC_PKTIF) {
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while (_packets_available(dev)) {
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unlock(dev);
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netdev->event_callback(netdev, NETDEV2_EVENT_RX_COMPLETE,
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@ -138,11 +138,11 @@ static void _isr(netdev2_t *netdev)
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}
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/* drop all flags */
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reg_clear_bits(dev, EIR, LINKIF);
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reg_clear_bits(dev, ENC_EIR, ENC_LINKIF);
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/* re-enable interrupt */
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gpio_irq_enable(dev->int_pin);
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cmd(dev, SETEIE);
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cmd(dev, ENC_SETEIE);
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unlock(dev);
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}
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@ -158,7 +158,7 @@ static inline void enc_spi_transfer(encx24j600_t *dev, char *out, char *in, int
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static inline uint16_t reg_get(encx24j600_t *dev, uint8_t reg)
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{
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char cmd[4] = { RCRU, reg, 0, 0 };
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char cmd[4] = { ENC_RCRU, reg, 0, 0 };
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char result[4];
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enc_spi_transfer(dev, cmd, result, 4);
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@ -167,8 +167,8 @@ static inline uint16_t reg_get(encx24j600_t *dev, uint8_t reg)
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}
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static void phy_reg_set(encx24j600_t *dev, uint8_t reg, uint16_t value) {
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reg_set(dev, MIREGADR, reg | (1<<8));
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reg_set(dev, MIWR, value);
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reg_set(dev, ENC_MIREGADR, reg | (1<<8));
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reg_set(dev, ENC_MIWR, value);
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}
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static void cmd(encx24j600_t *dev, char cmd) {
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@ -190,19 +190,19 @@ static void cmdn(encx24j600_t *dev, uint8_t cmd, char *out, char *in, int len) {
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static void reg_set(encx24j600_t *dev, uint8_t reg, uint16_t value)
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{
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char cmd[4] = { WCRU, reg, value, value >> 8 };
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char cmd[4] = { ENC_WCRU, reg, value, value >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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static void reg_set_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask)
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{
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char cmd[4] = { BFSU, reg, mask, mask >> 8 };
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char cmd[4] = { ENC_BFSU, reg, mask, mask >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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static void reg_clear_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask)
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{
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char cmd[4] = { BFCU, reg, mask, mask >> 8 };
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char cmd[4] = { ENC_BFCU, reg, mask, mask >> 8 };
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enc_spi_transfer(dev, cmd, NULL, 4);
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}
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@ -210,7 +210,7 @@ static void reg_clear_bits(encx24j600_t *dev, uint8_t reg, uint16_t mask)
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* @brief Read/Write to encx24j600's SRAM
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*
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* @param[in] dev ptr to encx24j600 device handle
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* @param[in] cmd either WGPDATA, RGPDATA, WRXDATA, RRXDATA, WUDADATA, RUDADATA
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* @param[in] cmd either ENC_WGPDATA, ENC_RGPDATA, ENC_WRXDATA, ENC_RRXDATA, ENC_WUDADATA, ENC_RUDADATA
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* @param[in] addr SRAM address to start reading. 0xFFFF means continue from old address
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* @param ptr pointer to buffer to read from / write to
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* @param[in] len nr of bytes to read/write
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@ -265,35 +265,35 @@ static int _init(netdev2_t *encdev)
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do {
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do {
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xtimer_usleep(ENCX24J600_INIT_DELAY);
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reg_set(dev, EUDAST, 0x1234);
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reg_set(dev, ENC_EUDAST, 0x1234);
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xtimer_usleep(ENCX24J600_INIT_DELAY);
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} while (reg_get(dev, EUDAST) != 0x1234);
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} while (reg_get(dev, ENC_EUDAST) != 0x1234);
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while (!(reg_get(dev, ESTAT) & CLKRDY));
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while (!(reg_get(dev, ENC_ESTAT) & ENC_CLKRDY));
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/* issue System Reset */
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cmd(dev, SETETHRST);
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cmd(dev, ENC_SETETHRST);
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/* make sure initialization finalizes */
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xtimer_usleep(1000);
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} while (!(reg_get(dev, EUDAST) == 0x0000));
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} while (!(reg_get(dev, ENC_EUDAST) == 0x0000));
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/* configure flow control */
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phy_reg_set(dev, PHANA, 0x05E1);
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reg_set_bits(dev, ECON2, AUTOFC);
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phy_reg_set(dev, ENC_PHANA, 0x05E1);
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reg_set_bits(dev, ENC_ECON2, ENC_AUTOFC);
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/* setup receive buffer */
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reg_set(dev, ERXST, RX_BUFFER_START);
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reg_set(dev, ERXTAIL, RX_BUFFER_END);
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reg_set(dev, ENC_ERXST, RX_BUFFER_START);
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reg_set(dev, ENC_ERXTAIL, RX_BUFFER_END);
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dev->rx_next_ptr = RX_BUFFER_START;
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/* configure receive filter to receive multicast frames */
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reg_set_bits(dev, ERXFCON, MCEN);
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reg_set_bits(dev, ENC_ERXFCON, ENC_MCEN);
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/* setup interrupts */
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reg_set_bits(dev, EIE, PKTIE | LINKIE);
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cmd(dev, ENABLERX);
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cmd(dev, SETEIE);
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reg_set_bits(dev, ENC_EIE, ENC_PKTIE | ENC_LINKIE);
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cmd(dev, ENC_ENABLERX);
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cmd(dev, ENC_SETEIE);
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DEBUG("encx24j600: initialization complete.\n");
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@ -314,26 +314,26 @@ static int _send(netdev2_t *netdev, const struct iovec *vector, int count) {
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#endif
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/* wait until previous packet has been sent */
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while ((reg_get(dev, ECON1) & TXRTS));
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while ((reg_get(dev, ENC_ECON1) & ENC_TXRTS));
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/* copy packet to SRAM */
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size_t len = 0;
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for (int i = 0; i < count; i++) {
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sram_op(dev, WGPDATA, (i ? 0xFFFF : TX_BUFFER_START), vector[i].iov_base, vector[i].iov_len);
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sram_op(dev, ENC_WGPDATA, (i ? 0xFFFF : TX_BUFFER_START), vector[i].iov_base, vector[i].iov_len);
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len += vector[i].iov_len;
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}
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/* set start of TX packet and length */
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reg_set(dev, ETXST, TX_BUFFER_START);
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reg_set(dev, ETXLEN, len);
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reg_set(dev, ENC_ETXST, TX_BUFFER_START);
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reg_set(dev, ENC_ETXLEN, len);
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/* initiate sending */
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cmd(dev, SETTXRTS);
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cmd(dev, ENC_SETTXRTS);
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/* wait for sending to complete */
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/* (not sure if it is needed, keeping the line uncommented) */
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/*while ((reg_get(dev, ECON1) & TXRTS));*/
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/*while ((reg_get(dev, ENC_ECON1) & ENC_TXRTS));*/
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unlock(dev);
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@ -342,8 +342,8 @@ static int _send(netdev2_t *netdev, const struct iovec *vector, int count) {
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static inline int _packets_available(encx24j600_t *dev)
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{
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/* return PKTCNT (low byte of ESTAT) */
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return reg_get(dev, ESTAT) & ~0xFF00;
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/* return ENC_PKTCNT (low byte of ENC_ESTAT) */
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return reg_get(dev, ENC_ESTAT) & ~0xFF00;
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}
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static void _get_mac_addr(netdev2_t *encdev, uint8_t* buf)
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@ -353,9 +353,9 @@ static void _get_mac_addr(netdev2_t *encdev, uint8_t* buf)
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lock(dev);
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addr[0] = reg_get(dev, MAADR1);
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addr[1] = reg_get(dev, MAADR2);
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addr[2] = reg_get(dev, MAADR3);
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addr[0] = reg_get(dev, ENC_MAADR1);
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addr[1] = reg_get(dev, ENC_MAADR2);
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addr[2] = reg_get(dev, ENC_MAADR3);
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unlock(dev);
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}
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@ -369,7 +369,7 @@ static int _recv(netdev2_t *netdev, char* buf, int len, void *info)
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lock(dev);
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/* read frame header */
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sram_op(dev, RRXDATA, dev->rx_next_ptr, (char*)&hdr, sizeof(hdr));
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sram_op(dev, ENC_RRXDATA, dev->rx_next_ptr, (char*)&hdr, sizeof(hdr));
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/* hdr.frame_len given by device contains 4 bytes checksum */
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size_t payload_len = hdr.frame_len - 4;
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@ -380,14 +380,14 @@ static int _recv(netdev2_t *netdev, char* buf, int len, void *info)
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netdev2->stats.rx_bytes += len;
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#endif
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/* read packet (without 4 bytes checksum) */
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sram_op(dev, RRXDATA, 0xFFFF, buf, payload_len);
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sram_op(dev, ENC_RRXDATA, 0xFFFF, buf, payload_len);
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/* decrement available packet count */
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cmd(dev, SETPKTDEC);
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cmd(dev, ENC_SETPKTDEC);
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dev->rx_next_ptr = hdr.rx_next_ptr;
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reg_set(dev, ERXTAIL, dev->rx_next_ptr - 2);
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reg_set(dev, ENC_ERXTAIL, dev->rx_next_ptr - 2);
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}
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unlock(dev);
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@ -28,80 +28,80 @@ extern "C" {
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* @name SPI instruction set
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* @{
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*/
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#define RCR 0x00 /* read control register */
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#define WCR 0x04 /* write control register */
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#define ENC_RCR 0x00 /* read control register */
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#define ENC_WCR 0x04 /* write control register */
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#define RCRU 0x20 /* read control register unbanked */
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#define WCRU 0x22 /* write control register unbanked */
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#define ENC_RCRU 0x20 /* read control register unbanked */
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#define ENC_WCRU 0x22 /* write control register unbanked */
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#define BFSU 0x24 /* set bits unbanked */
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#define BFCU 0x26 /* clear bits unbanked */
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#define ENC_BFSU 0x24 /* set bits unbanked */
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#define ENC_BFCU 0x26 /* clear bits unbanked */
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#define RGPDATA 0x28 /* Read EGPDATA */
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#define WGPDATA 0x2a /* Write EGPDATA */
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#define ENC_RGPDATA 0x28 /* Read EGPDATA */
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#define ENC_WGPDATA 0x2a /* Write EGPDATA */
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#define RRXDATA 0x2c /* Read ERXDATA */
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#define WRXDATA 0x2e /* Write ERXDATA */
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#define ENC_RRXDATA 0x2c /* Read ERXDATA */
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#define ENC_WRXDATA 0x2e /* Write ERXDATA */
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#define RUDADATA 0x30 /* Read EUDADATA */
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#define WUDADATA 0x32 /* Write EUDADATA */
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#define ENC_RUDADATA 0x30 /* Read EUDADATA */
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#define ENC_WUDADATA 0x32 /* Write EUDADATA */
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#define BFS 0x80 /* Bit Field Set */
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#define BFC 0xa0 /* Bit Field Clear */
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#define ENC_BFS 0x80 /* Bit Field Set */
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#define ENC_BFC 0xa0 /* Bit Field Clear */
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#define SETETHRST 0xca /* System Reset */
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#define SETPKTDEC 0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
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#define ENABLERX 0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
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#define DISABLERX 0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
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#define SETEIE 0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
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#define CLREIE 0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
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#define ENC_SETETHRST 0xca /* System Reset */
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#define ENC_SETPKTDEC 0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
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#define ENC_ENABLERX 0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
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#define ENC_DISABLERX 0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
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#define ENC_SETEIE 0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
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#define ENC_CLREIE 0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
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#define B0SEL 0xc0 /* select bank 0 */
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#define B1SEL 0xc2 /* select bank 0 */
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#define B2SEL 0xc4 /* select bank 0 */
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#define B3SEL 0xc6 /* select bank 0 */
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#define RBSEL 0xc8 /* Read Bank Select */
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#define ENC_B0SEL 0xc0 /* select bank 0 */
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#define ENC_B1SEL 0xc2 /* select bank 0 */
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#define ENC_B2SEL 0xc4 /* select bank 0 */
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#define ENC_B3SEL 0xc6 /* select bank 0 */
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#define ENC_RBSEL 0xc8 /* Read Bank Select */
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#define SETTXRTS 0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
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#define ENC_SETTXRTS 0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
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/** @} */
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/**
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* @name 16bit Registers
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* @{
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*/
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#define ETXST 0x00
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#define ETXLEN 0x02
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#define ERXST 0x04
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#define ERXTAIL 0x06
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#define ERXHEAD 0x08
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#define ETXSTAT 0x12
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#define ETXWIRE 0x14
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#define EUDAST 0x16
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#define ESTAT 0x1a
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#define EIR 0x1c /* Interrupt Flag Register */
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#define ECON1 0x1e
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#define ENC_ETXST 0x00
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#define ENC_ETXLEN 0x02
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#define ENC_ERXST 0x04
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#define ENC_ERXTAIL 0x06
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#define ENC_ERXHEAD 0x08
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#define ENC_ETXSTAT 0x12
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#define ENC_ETXWIRE 0x14
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#define ENC_EUDAST 0x16
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#define ENC_ESTAT 0x1a
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#define ENC_EIR 0x1c /* Interrupt Flag Register */
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#define ENC_ECON1 0x1e
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#define ERXFCON 0x34 /* Receive filter control register */
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#define ENC_ERXFCON 0x34 /* Receive filter control register */
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#define MACON2 0x42
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#define MAMXFL 0x4a /* MAC maximum frame length */
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#define ENC_MACON2 0x42
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#define ENC_MAMXFL 0x4a /* MAC maximum frame length */
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#define MAADR3 0x60 /* MAC address byte 5&6 */
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#define MAADR2 0x62 /* MAC address byte 3&4 */
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#define MAADR1 0x64 /* MAC address byte 1&2 */
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#define ENC_MAADR3 0x60 /* MAC address byte 5&6 */
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#define ENC_MAADR2 0x62 /* MAC address byte 3&4 */
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#define ENC_MAADR1 0x64 /* MAC address byte 1&2 */
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#define MIWR 0x66
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#define MIREGADR 0x54
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#define ENC_MIWR 0x66
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#define ENC_MIREGADR 0x54
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#define ECON2 0x6e
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#define ENC_ECON2 0x6e
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#define EIE 0x72 /* Interrupt Enable Register */
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#define ENC_EIE 0x72 /* Interrupt Enable Register */
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#define EGPRDPT 0x86 /* General Purpose SRAM read pointer */
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#define EGPWRPT 0x88 /* General Purpose SRAM write pointer */
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#define ENC_EGPRDPT 0x86 /* General Purpose SRAM read pointer */
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#define ENC_EGPWRPT 0x88 /* General Purpose SRAM write pointer */
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#define ERXRDPT 0x8a /* RX buffer read pointer */
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#define ERXWRPT 0x8c /* RX buffer write pointer */
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#define ENC_ERXRDPT 0x8a /* RX buffer read pointer */
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#define ENC_ERXWRPT 0x8c /* RX buffer write pointer */
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/** @} */
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/**
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@ -111,92 +111,92 @@ extern "C" {
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*
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* @{
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*/
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHANA 0x04
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#define PHANLPA 0x05
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#define PHANE 0x06
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#define PHCON2 0x11
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#define PHSTAT2 0x1b
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#define PHSTAT3 0x1f
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#define ENC_PHCON1 0x00
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#define ENC_PHSTAT1 0x01
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#define ENC_PHANA 0x04
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#define ENC_PHANLPA 0x05
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#define ENC_PHANE 0x06
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#define ENC_PHCON2 0x11
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#define ENC_PHSTAT2 0x1b
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#define ENC_PHSTAT3 0x1f
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/** @} */
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/**
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* @name ESTAT bits
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* @{
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*/
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#define PHYLNK (1<<8)
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#define CLKRDY (1<<12)
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#define ENC_PHYLNK (1<<8)
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#define ENC_CLKRDY (1<<12)
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/** @} */
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/**
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* @name ECON1 bits
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* @{
|
||||
*/
|
||||
#define RXEN (1<<0)
|
||||
#define TXRTS (1<<1)
|
||||
#define DMANOCS (1<<2)
|
||||
#define DMACSSD (1<<3)
|
||||
#define DMACPY (1<<4)
|
||||
#define DMAST (1<<5)
|
||||
#define FCOP0 (1<<6)
|
||||
#define FCOP1 (1<<7)
|
||||
#define PKTDEC (1<<8)
|
||||
#define AESOP0 (1<<9)
|
||||
#define AESOP1 (1<<10)
|
||||
#define AESST (1<<11)
|
||||
#define HASHLST (1<<12)
|
||||
#define HASHOP (1<<13)
|
||||
#define HASHEN (1<<14)
|
||||
#define MODEXST (1<<15)
|
||||
#define ENC_RXEN (1<<0)
|
||||
#define ENC_TXRTS (1<<1)
|
||||
#define ENC_DMANOCS (1<<2)
|
||||
#define ENC_DMACSSD (1<<3)
|
||||
#define ENC_DMACPY (1<<4)
|
||||
#define ENC_DMAST (1<<5)
|
||||
#define ENC_FCOP0 (1<<6)
|
||||
#define ENC_FCOP1 (1<<7)
|
||||
#define ENC_PKTDEC (1<<8)
|
||||
#define ENC_AESOP0 (1<<9)
|
||||
#define ENC_AESOP1 (1<<10)
|
||||
#define ENC_AESST (1<<11)
|
||||
#define ENC_HASHLST (1<<12)
|
||||
#define ENC_HASHOP (1<<13)
|
||||
#define ENC_HASHEN (1<<14)
|
||||
#define ENC_MODEXST (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ECON2 bits
|
||||
* @{
|
||||
*/
|
||||
#define ETHRST (1<<4)
|
||||
#define AUTOFC (1<<7) /* automatic flow control enable bit */
|
||||
#define ENC_ETHRST (1<<4)
|
||||
#define ENC_AUTOFC (1<<7) /* automatic flow control enable bit */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EIR bits
|
||||
* @{
|
||||
*/
|
||||
#define PCFULIE (1<<0)
|
||||
#define RXABTIE (1<<1)
|
||||
#define TXABTIE (1<<2)
|
||||
#define TXIE (1<<3)
|
||||
#define DMAIE (1<<5)
|
||||
#define PKTIE (1<<6)
|
||||
#define LINKIE (1<<11)
|
||||
#define AESIE (1<<12)
|
||||
#define HASHIE (1<<13)
|
||||
#define MODEXIE (1<<14)
|
||||
#define INTIE (1<<15)
|
||||
#define ENC_PCFULIE (1<<0)
|
||||
#define ENC_RXABTIE (1<<1)
|
||||
#define ENC_TXABTIE (1<<2)
|
||||
#define ENC_TXIE (1<<3)
|
||||
#define ENC_DMAIE (1<<5)
|
||||
#define ENC_PKTIE (1<<6)
|
||||
#define ENC_LINKIE (1<<11)
|
||||
#define ENC_AESIE (1<<12)
|
||||
#define ENC_HASHIE (1<<13)
|
||||
#define ENC_MODEXIE (1<<14)
|
||||
#define ENC_INTIE (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EIR bits
|
||||
* @{
|
||||
*/
|
||||
#define PCFULIF (1<<0)
|
||||
#define RXABTIF (1<<1)
|
||||
#define TXABTIF (1<<2)
|
||||
#define TXIF (1<<3)
|
||||
#define DMAIF (1<<5)
|
||||
#define PKTIF (1<<6)
|
||||
#define LINKIF (1<<11)
|
||||
#define AESIF (1<<12)
|
||||
#define HASHIF (1<<13)
|
||||
#define MODEXIF (1<<14)
|
||||
#define CRYPTEN (1<<15)
|
||||
#define ENC_PCFULIF (1<<0)
|
||||
#define ENC_RXABTIF (1<<1)
|
||||
#define ENC_TXABTIF (1<<2)
|
||||
#define ENC_TXIF (1<<3)
|
||||
#define ENC_DMAIF (1<<5)
|
||||
#define ENC_PKTIF (1<<6)
|
||||
#define ENC_LINKIF (1<<11)
|
||||
#define ENC_AESIF (1<<12)
|
||||
#define ENC_HASHIF (1<<13)
|
||||
#define ENC_MODEXIF (1<<14)
|
||||
#define ENC_CRYPTEN (1<<15)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name ERXFCON bits
|
||||
*/
|
||||
#define MCEN (1<<1)
|
||||
#define ENC_MCEN (1<<1)
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
Loading…
Reference in New Issue
Block a user