Merge pull request #6092 from neiljay/pr/add_mips_pic32mx

cpu: Add PIC32MX Support

boards/pic32-clicker/Makefile

@@ -0,0 +1,2 @@
+MODULE = board
+include $(RIOTBASE)/Makefile.base

boards/pic32-clicker/Makefile.features

@@ -0,0 +1,9 @@
+# Put defined MCU peripherals here (in alphabetical order)
+FEATURES_PROVIDED += periph_timer
+FEATURES_PROVIDED += periph_uart
+
+# Various other features (if any)
+FEATURES_PROVIDED += cpp
+
+# The board MPU family (used for grouping by the CI system)
+FEATURES_MCU_GROUP = mips32r2

boards/pic32-clicker/Makefile.include

@@ -0,0 +1,4 @@
+export CPU = mips_pic32mx
+export CPU_MODEL=p32mx470f512h
+export INCLUDES += -I$(RIOTBOARD)/$(BOARD)/include/
+export APPDEPS += $(RIOTCPU)/$(CPU)/$(CPU_MODEL)/$(CPU_MODEL).S

boards/pic32-clicker/clicker.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+#include <stdio.h>
+#include <stdint.h>
+#include "periph/uart.h"
+#include "bitarithm.h"
+#include "board.h"
+#include "periph_conf.h"
+
+extern void dummy(void);
+
+void board_init(void)
+{
+    /*
+     * Setup pin mux for UART3 this is the one connected
+     * to the mickroBUS
+     */
+    U3RXREG =  0x2;          /*connect pin RPF5 to UART3 RX*/
+    RPF4R =    0x1;          /*connect pin RPF4 to UART3 TX*/
+    PORTFCLR = BIT5 | BIT4;  /*set '0' on Porf F pins 4 and 5 */
+    TRISFCLR = BIT4;         /*set PortF pin 4 for output */
+    TRISFSET = BIT5;         /*set PortF pin 5 for input */
+    ODCFCLR =  BIT5 | BIT4;  /*set PortF pin 4 and 5 as not open-drain */
+
+    /* intialise UART used for debug (printf) */
+#ifdef DEBUG_VIA_UART
+    uart_init(DEBUG_VIA_UART, DEBUG_UART_BAUD, NULL, 0);
+#endif
+
+    /* Stop the linker from throwing away the PIC32 config register settings */
+    dummy();
+}
+
+void pm_reboot(void)
+{
+    /* TODO, note this is needed to get 'default' example to build */
+}

boards/pic32-clicker/include/board.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+/**
+ * @defgroup    boards_pic32-clicker MikroE PIC32 Clicker
+ * @ingroup     boards
+ * @brief       board configuration for the MikroE PIC32 Clicker
+ * @details
+ * see:
+ * http://www.mikroe.com/pic32/pic32mx-clicker/
+ * For more information on the board.
+ *
+ * @{
+ *
+ * @file
+ * @brief       board configuration for the MikroE PIC32 Clicker
+ *
+ * @author      Neil Jones <Neil.Jones@imgtec.com>
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vendor/p32mx470f512h.h"
+
+/**
+ * @brief Set how many increments of the count register per uS
+ *        needed by the timer code.
+ */
+#define TICKS_PER_US (48)
+
+/**
+ * @brief We are using an External Interrupt Controller (all pic32 devices use this mode)
+ */
+#define EIC_IRQ (1)
+
+/**
+ * @brief   Board level initialisation
+ */
+void board_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _BOARD_H_ */
+/** @} */

boards/pic32-clicker/include/periph_conf.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+/**
+ * @defgroup    boards_pic32-clicker MikroE PIC32 Clicker
+ * @ingroup     boards
+ * @brief       peripheral configuration for the MikroE PIC32 Clicker
+ * @{
+ *
+ * @file
+ * @brief       peripheral configuration for the MikroE PIC32 Clicker
+ *
+ * @author       Neil Jones <Neil.Jones@imgtec.com>
+ */
+
+#ifndef _PERIPH_CONF_H_
+#define _PERIPH_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * @brief The peripheral clock is required for the UART Baud rate calculation
+ *        It is configured by the 'config' registers (see pic32_config_settings.c)
+ *        Note 120MHz is the max F for this device.
+ */
+#define PERIPHERAL_CLOCK (96000000)  /* Hz */
+
+/**
+ * @brief   Timer definitions
+ * @{
+ */
+#define TIMER_NUMOF         (1)
+#define TIMER_0_CHANNELS    (3)
+/** @} */
+
+/**
+  * @brief   UART Definitions
+  *          There are 4 UARTS available on this CPU.
+  *          We route debug via UART3 on this board,
+  *          this is the UART connected to the MikroBUS
+  *
+  *          Note Microchip number the UARTS 1->4
+  * @{
+  */
+#define UART_NUMOF          (4)
+#define DEBUG_VIA_UART      (3)
+#define DEBUG_UART_BAUD     (9600)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */

boards/pic32-clicker/pic32_config_settings.c

@@ -0,0 +1,117 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+#include <stdint.h>
+#include "vendor/p32mx470f512h.h"
+/*
+ *  DEVCFG3  @ 0x1FC02FF0
+ *
+ *
+ *  USERID
+ *  FSRSSEL     7   Assign IPL 7 to a shadow register set.
+ *  PMDLIWAY    1
+ *  IOL1WAY     1
+ *  FUSBIDIO    OFF USB USBID Selection Controlled by Port Function
+ *  FVBUSONIO   ON  VBUSON pin is controlled by the USB module function
+
+ */
+volatile uint32_t _DEVCFG3 __attribute__((used, section(".devcfg3"))) =
+    0x0 /* unused bits must be 0 */
+    | (_DEVCFG3_USERID_MASK     &  0xFFFF   << _DEVCFG3_USERID_POSITION)
+    | (_DEVCFG3_FSRSSEL_MASK    &  7        << _DEVCFG3_FSRSSEL_POSITION)
+    | (_DEVCFG3_PMDL1WAY_MASK   &  1        << _DEVCFG3_PMDL1WAY_POSITION)
+    | (_DEVCFG3_IOL1WAY_MASK    &  1        << _DEVCFG3_IOL1WAY_POSITION)
+    | (_DEVCFG3_FUSBIDIO_MASK   &  0        << _DEVCFG3_FUSBIDIO_POSITION)
+    | (_DEVCFG3_FVBUSONIO_MASK  &  1        << _DEVCFG3_FVBUSONIO_POSITION);
+
+
+
+/* Note this sets the PLL to 96MHz (8/2 * 24) which is only supported by 3xx
+ * and 4xx parts and assumes an 8MHz XTAL.
+ *
+ * 1xx/2xx/53x/57x only support 50MHz (use 8/2 x 24 / 2 = 48Mhz)
+ * 5xx/6xx/7xx only support 80Mhz (use 8/2 * 20 = 80MHz).
+ *
+ *
+ * DEVCFG2  @ 0x1FC02FF4 (
+ *
+ *  FPLLIDIV    DIV_2     System PLL Input Divider  2x Divider
+ *  FPLLMUL     24x       System PLL Multiplier PLL Multiply by 24, 8/2 x 24 = 96MHz
+ *  UPLLIDIV    DIV_12x   USB PLL divider
+ *  UPLLEN      OFF       USB PLL disabled
+ *  FPLLODIV    DIV_1     System PLL Output Clock Divider   1x Divider
+ */
+
+volatile uint32_t _DEVCFG2 __attribute__ ((used, section(".devcfg2"))) =
+    0xffffffff /* unused bits must be 1 */
+    & (~_DEVCFG2_FPLLIDIV_MASK   |  1        << _DEVCFG2_FPLLIDIV_POSITION)
+    & (~_DEVCFG2_FPLLMUL_MASK    |  7        << _DEVCFG2_FPLLMUL_POSITION)
+    & (~_DEVCFG2_UPLLIDIV_MASK   |  7        << _DEVCFG2_UPLLIDIV_POSITION)
+    & (~_DEVCFG2_UPLLEN_MASK     |  0        << _DEVCFG2_UPLLEN_POSITION)
+    & (~_DEVCFG2_FPLLODIV_MASK   |  0        << _DEVCFG2_FPLLODIV_POSITION);
+
+/*
+ * DEVCFG1  @ 0x1FC02FF8
+ *
+ * FNOSC     PRIPLL   Oscillator Selection Bits Primary Osc w/PLL (XT+,HS+,EC+PLL)
+ * FSOSCEN   ON       Secondary Oscillator Enable Enabled
+ * IESO      ON       Internal/External Switch Over Enabled
+ * OSCIOFNC  OFF CLKO Output Signal Active on the OSCO Pin Disabled
+ * FPBDIV    DIV_1    Peripheral Clock Divisor  Pb_Clk is Sys_Clk/1
+ * FCKSM     CSDCMD   Clock Switching and Monitor Selection Clock Switch Disable, FSCM Disabled
+ * WDTPS     PS2      Watchdog Timer Postscaler 1:2
+ * WINDIS    OFF      Watchdog Timer Window Enable Watchdog Timer is in Non-Window Mode
+ * FWDTEN    OFF      Watchdog Timer Enable WDT Disabled (SWDTEN Bit Controls)
+ * FWDTWINSZ 25%
+ */
+
+volatile uint32_t _DEVCFG1 __attribute__ ((used, section(".devcfg1"))) =
+    0xffffffff /* unused bits must be 1 */
+    & (~_DEVCFG1_FNOSC_MASK     |  3        << _DEVCFG1_FNOSC_POSITION)
+    & (~_DEVCFG1_FSOSCEN_MASK   |  1        << _DEVCFG1_FSOSCEN_POSITION)
+    & (~_DEVCFG1_IESO_MASK      |  1        << _DEVCFG1_IESO_POSITION)
+    & (~_DEVCFG1_POSCMOD_MASK   |  1        << _DEVCFG1_POSCMOD_POSITION)
+    & (~_DEVCFG1_OSCIOFNC_MASK  |  1        << _DEVCFG1_OSCIOFNC_POSITION)
+    & (~_DEVCFG1_FPBDIV_MASK    |  0        << _DEVCFG1_FPBDIV_POSITION)
+    & (~_DEVCFG1_FCKSM_MASK     |  3        << _DEVCFG1_FCKSM_POSITION)
+    & (~_DEVCFG1_WDTPS_MASK     |  1        << _DEVCFG1_WDTPS_POSITION)
+    & (~_DEVCFG1_WINDIS_MASK    |  0        << _DEVCFG1_WINDIS_POSITION)
+    & (~_DEVCFG1_FWDTEN_MASK    |  0        << _DEVCFG1_FWDTEN_POSITION)
+    & (~_DEVCFG1_FWDTWINSZ_MASK |  3        << _DEVCFG1_FWDTWINSZ_POSITION);
+
+
+/*
+ * DEVCFG0  @ 0x1FC02FFC
+ *
+ * DEBUG    OFF      Background Debugger Enable Debugger is disabled
+ * JTAGEN   ON       JTAG Enable    JTAG Port Enabled
+ * ICESEL   ICS_PGx1 CE/ICD Comm Channel Select Communicate on PGEC1/PGED1
+ * PWP      OFF      Program Flash Write Protect Disable
+ * BWP      OFF      Boot Flash Write Protect bit Protection Disabled
+ * CP       OFF      Code Protect Protection Disabled
+ */
+
+volatile uint32_t _DEVCFG0 __attribute__ ((used, section(".devcfg0"))) =
+    0x7fffffff /* unused bits must be 1 except MSB which is 0 for some odd reason */
+    & (~_DEVCFG0_DEBUG_MASK     |  3        << _DEVCFG0_DEBUG_POSITION)
+    & (~_DEVCFG0_JTAGEN_MASK    |  1        << _DEVCFG0_JTAGEN_POSITION)
+    & (~_DEVCFG0_ICESEL_MASK    |  3        << _DEVCFG0_ICESEL_POSITION)
+    & (~_DEVCFG0_PWP_MASK       |  0xff     << _DEVCFG0_PWP_POSITION)
+    & (~_DEVCFG0_BWP_MASK       |  1        << _DEVCFG0_BWP_POSITION)
+    & (~_DEVCFG0_CP_MASK        |  1        << _DEVCFG0_CP_POSITION);
+
+/*
+ * Without a reference to this function from elsewhere LD throws the whole
+ * compile unit away even though the data is 'volatile' and 'used' !!!
+ */
+void dummy(void)
+{
+    (void)1;
+}

cpu/mips_pic32mx/Makefile

@@ -0,0 +1,8 @@
+MODULE = cpu
+
+USEMODULE += mips_pic32_common
+USEMODULE += mips32r2_common
+
+DIRS += $(RIOTCPU)/mips_pic32_common $(RIOTCPU)/mips32r2_common
+
+include $(RIOTBASE)/Makefile.base

cpu/mips_pic32mx/Makefile.include

@@ -0,0 +1,32 @@
+export MEMORY_BASE=0x80000000
+export MEMORY_SIZE=128K
+export APP_START=0x80000000
+export ROMABLE = 1
+
+include $(RIOTCPU)/Makefile.include.mips_common
+
+# define build specific options
+export CFLAGS += -march=m4k -DSKIP_COPY_TO_RAM
+
+export USEMODULE += periph
+
+export LINKFLAGS += -Wl,--defsym,__use_excpt_boot=0 $(CFLAGS)
+export LINKFLAGS += -T$(RIOTCPU)/$(CPU)/ldscripts/pic32mx512_12_128_uhi.ld
+
+# the pickit programmer (MPLAB-IPE) wants physical addresses in the hex file!!
+export OBJCOPY = objcopy #use system objcopy as toolchain one is broken.
+export OFLAGS += -O ihex \
+				--change-section-lma .bootflash-0xA0000000 \
+				--change-section-lma .exception_vector-0x80000000 \
+				--change-section-lma .text-0x80000000 \
+				--change-section-lma .init-0x80000000 \
+				--change-section-lma .fini-0x80000000 \
+				--change-section-lma .eh_frame-0x80000000 \
+				--change-section-lma .gcc_except_table-0x80000000 \
+				--change-section-lma .jcr-0x80000000 \
+				--change-section-lma .ctors-0x80000000 \
+				--change-section-lma .dtors-0x80000000 \
+				--change-section-lma .rodata-0x80000000 \
+				--change-section-lma .data-0x80000000 \
+				--change-section-lma .bss-0x80000000 \
+				--change-section-lma .startdata-0x80000000 \

cpu/mips_pic32mx/eic_pic32mx.c

@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+#include <assert.h>
+
+#include "board.h"
+#include "../mips32r2_common/include/eic_irq.h"
+
+void eic_irq_configure(int irq_num)
+{
+    /* Only timer interrupt supported currently */
+    assert(irq_num == EIC_IRQ_TIMER);
+
+    /* Enable IRQ0 CPU Timer Interrupt */
+    IEC0SET = _IEC0_CTIE_MASK;
+
+    /* Set IRQ 0 to priority 1.0 */
+    IPC0SET = 1 << _IPC0_CTIP_POSITION | 0 << _IPC0_CTIS_POSITION;
+}
+
+void eic_irq_enable(int irq_num)
+{
+    /* Only timer interrupt supported currently */
+    assert(irq_num == EIC_IRQ_TIMER);
+
+    /* Enable IRQ0 CPU Timer Interrupt */
+    IEC0SET = _IEC0_CTIE_MASK;
+}
+
+void eic_irq_disable(int irq_num)
+{
+    /* Only timer interrupt supported currently */
+    assert(irq_num == EIC_IRQ_TIMER);
+
+    /* Disable IRQ0 CPU Timer Interrupt */
+    IEC0CLR = _IEC0_CTIE_MASK;
+}
+
+void eic_irq_ack(int irq_num)
+{
+    /* Only timer interrupt supported currently */
+    assert(irq_num == EIC_IRQ_TIMER);
+
+    /* Ack the timer interrupt */
+    IFS0CLR =_IFS0_CTIF_MASK;
+}

cpu/mips_pic32mx/include/cpu.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.#
+ *
+ */
+
+/**
+ * @defgroup    cpu_mips_pic32mx MIPS PIC32MX
+ * @ingroup     cpu
+ * @brief       main CPU definitions for pic32mx devices.
+ * @{
+ *
+ * @file
+ * @brief       main CPU definitions for pic32mx devices.
+ *
+ * @author      Neil Jones <neil.jones@imgtec.com>
+ */
+
+#ifndef _CPU_H_
+#define _CPU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <inttypes.h>
+#include <assert.h>
+#include "irq.h"
+
+/**
+ * @brief We run from flash on PIC32
+ */
+#define FLASH_XIP (1)
+
+/**
+ * @brief   Print the last instruction's address
+ *
+ * @todo:   Not supported
+ */
+static inline void cpu_print_last_instruction(void)
+{
+    /* This function must exist else RIOT won't compile */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */

cpu/mips_pic32mx/include/cpu_conf.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+/**
+ * @defgroup    cpu_mips_pic32mx MIPS PIC32MX
+ * @ingroup     cpu
+ * @{
+ *
+ * @file
+ * @brief       CPU definitions for pic32mx devices.
+ *
+ * @author      Neil Jones <neil.jones@imgtec.com>
+ */
+
+#ifndef _CPU_CONF_H_
+#define _CPU_CONF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief    Configuration of default stack sizes
+ *
+ * printf takes a pretty tortured route through the C lib
+ * then via UHI syscall exception to end up at the UART
+ * driver.
+ *
+ * When debugging timer code we get printfs on the idle threads
+ * stack which can easily blow its limits.
+ *
+ * Note code must be compiled at -Os with these values, using -O0
+ * you'll overflow these stacks.
+ *
+ * NO ISR stack is in use yet, interrupt use the current running stack
+ * hence the big-ish default stack size.
+ * @{
+ */
+#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
+#define THREAD_EXTRA_STACKSIZE_PRINTF   (1024)
+#endif
+
+#ifndef THREAD_STACKSIZE_DEFAULT
+#define THREAD_STACKSIZE_DEFAULT        (2048)
+#endif
+
+#ifndef THREAD_STACKSIZE_IDLE
+#ifdef NDEBUG
+#define THREAD_STACKSIZE_IDLE           (512)
+#else
+#define THREAD_STACKSIZE_IDLE           (512 + THREAD_EXTRA_STACKSIZE_PRINTF)
+#endif
+#endif
+
+#define ISR_STACKSIZE                   (0)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */

cpu/mips_pic32mx/include/periph_cpu.h

@@ -0,0 +1,19 @@
+/*
+ * Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
+ *                 affiliated group companies.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ *
+ */
+
+/* This file must exist to get timer code to build */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif

cpu/mips_pic32mx/ldscripts/pic32mx512_12_128_uhi.ld

@@ -0,0 +1,324 @@
+/*
+ * For all MX devices with 512K program flash / 12KB boot flash and 128KB Ram
+ *
+ * A platform and target independent link script to produce UHI
+ * compliant binaries with varying levels of system initialization
+ * support.
+ */
+
+__entry = DEFINED(__reset_vector) ? 0xbfc00000 : _start;
+ENTRY(__entry)
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips")
+GROUP(-lc -luhi -lgcc -lhal)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+STARTUP(crt0.o)
+/* Force the exception handler to be registered */
+EXTERN(__register_excpt_handler)
+/* Force the exception handler to be included in the link */
+EXTERN(__exception_entry)
+/*
+ * Require verbose exceptions. This can be changed to pull in
+ * __exception_handle_quiet to reduce code size but be less
+ * informative
+ */
+EXTERN(__exception_handle_verbose)
+/* Force the interrupt handlers to tbe included in the link */
+EXTERN(__isr_vec)
+/* Require the UHI getargs support */
+EXTERN(__getargs)
+
+/*
+ * Set the location of the top of the stack.  A value of 0 means
+ * that it will be automatically placed at the highest address
+ * available as described by the __memory_* setttings
+ */
+PROVIDE (__stack = 0);
+
+/* Size of the memory returned by _get_ram_range */
+PROVIDE (__memory_size = 128K);
+
+/* Base of the memory returned by _get_ram_range */
+PROVIDE (__memory_base = 0x80000000);
+
+/* Stride length for tlb software invalidate for tlbinvf
+ * (mipsXXr3+). Some MIPS implementations may layout the sets/ways
+ * differently in the index register. Either sets LSB or ways LSB.
+ *
+ * By setting this to 1 we presume that sets come first. The default boot
+ * code will decrement this value from the Number of TLB entries.
+ */
+PROVIDE (__tlb_stride_length = 1);
+
+/* By default, XPA is not used even if available. To enable XPA,
+ * __enable_xpa should be 1.
+ */
+PROVIDE (__enable_xpa = 0);
+
+/*
+ * 0 = Do not use exception handler present in boot for UHI
+ * 1 = Use exception handler present in boot for UHI if BEV is 0 at
+ *     startup
+ * 2 = Always use exception handler present in boot for UHI
+ */
+PROVIDE (__use_excpt_boot = 0);
+/*
+ * Include the code to be able to return to boot context.  This is
+ * necessary if __use_excpt_boot != 0.
+ */
+EXTERN (__register_excpt_boot);
+
+ASSERT (DEFINED(__register_excpt_boot) || __use_excpt_boot == 0,
+	"Registration for boot context is required for UHI chaining")
+
+/* Control if subnormal floating-point values are flushed to zero in
+   hardware.  This applies to both FPU and MSA operations.  */
+PROVIDE (__flush_to_zero = 1);
+
+/* Set up the public symbols depending on whether the user has chosen
+   quiet or verbose exception handling above */
+EXTERN (__exception_handle);
+PROVIDE(__exception_handle = (DEFINED(__exception_handle_quiet)
+				      ? __exception_handle_quiet
+				      : __exception_handle_verbose));
+PROVIDE(_mips_handle_exception = __exception_handle);
+
+/*
+ * Initalize some symbols to be zero so we can reference them in the
+ * crt0 without core dumping. These functions are all optional, but
+ * we do this so we can have our crt0 always use them if they exist.
+ * This is so BSPs work better when using the crt0 installed with gcc.
+ * We have to initalize them twice, so we multiple object file
+ * formats, as some prepend an underscore.
+ */
+PROVIDE (hardware_exit_hook = 0);
+PROVIDE (hardware_hazard_hook = 0);
+PROVIDE (hardware_init_hook = 0);
+PROVIDE (software_init_hook = 0);
+
+/* The default base address for application flash code is 0x9D001000 */
+PROVIDE (__app_start = 0x9D001000) ;
+/* Set default vector spacing to 32 bytes. */
+PROVIDE (__isr_vec_space = 32);
+/* Leave space for 9 vector entries by default. 8 entry points and one
+   fallback handler. */
+PROVIDE (__isr_vec_count = 9);
+/*
+ * The start of boot flash must be set if including boot code.  By default
+ * the use of boot code will mean that application code is copied
+ * from flash to RAM at runtime before being executed.
+ */
+PROVIDE (__boot_flash_start = DEFINED(__reset_vector) ? 0xbfc00000 : __app_start);
+
+PROVIDE (__bev_override = 0x9fc00000);
+
+PROVIDE (__flash_vector_start = 0x9D000000);
+
+PROVIDE (__flash_app_start = 0x9D001000);
+
+SECTIONS
+{
+  /* Start of bootrom */
+  .bootflash __bev_override : /* Runs uncached (from 0xBfc00000) until I$ is
+			       initialized. */
+  AT (__boot_flash_start)
+  {
+    __base = .;
+
+    *(.reset)		/* Reset entry point. */
+    *(.boot)		/* Boot code. */
+    . = ALIGN(8);
+
+    . = __base + 0x2ff0; /*Alternate Config bits (lower Alias)*/
+    KEEP(*(.devcfg3))
+    KEEP(*(.devcfg2))
+    KEEP(*(.devcfg1))
+    KEEP(*(.devcfg0))
+  } = 0xFFFFFFFF
+
+  /* Start of the application */
+  .exception_vector ALIGN(__flash_vector_start, 0x1000) :
+  AT (__flash_vector_start)
+  {
+    PROVIDE (__excpt_ebase = ABSOLUTE(.));
+    __base = .;
+    KEEP(* (.text.__exception_entry))
+
+    . = __base + 0x200;
+    KEEP(* (SORT(.text.__isr_vec*)))
+    /* Leave space for all the vector entries */
+    . = __base + 0x200 + (__isr_vec_space * __isr_vec_count);
+    ASSERT(__isr_vec_space == (DEFINED(__isr_vec_sw0)
+			       ? __isr_vec_sw1 - __isr_vec_sw0
+			       : __isr_vec_space),
+	   "Actual ISR vector spacing does not match __isr_vec_space");
+    ASSERT(__base + 0x200 == (DEFINED(__isr_vec_sw0)
+			      ? __isr_vec_sw0 & 0xfffffffe : __base + 0x200),
+	   "__isr_vec_sw0 is not placed at EBASE + 0x200");
+    . = ALIGN(8);
+  } = 0
+
+  . = __flash_app_start;
+
+  .text : {
+     _ftext = . ;
+    PROVIDE (eprol  =  .);
+    *(.text)
+    *(.text.*)
+    *(.gnu.linkonce.t.*)
+    *(.mips16.fn.*)
+    *(.mips16.call.*)
+  }
+  .init : {
+    KEEP (*(.init))
+  }
+  .fini : {
+    KEEP (*(.fini))
+  }
+  .rel.sdata : {
+    PROVIDE (__runtime_reloc_start = .);
+    *(.rel.sdata)
+    PROVIDE (__runtime_reloc_stop = .);
+  }
+  PROVIDE (etext  =  .);
+  _etext  =  .;
+
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame : { KEEP (*(.eh_frame)) }
+  .gcc_except_table : { *(.gcc_except_table*) }
+  .jcr : { KEEP (*(.jcr)) }
+  .ctors    :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+
+    KEEP (*crtbegin.o(.ctors))
+
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+
+  .dtors    :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+
+  . = .;
+  .MIPS.abiflags : {
+    __MIPS_abiflags_start = .;
+    *(.MIPS.abiflags)
+    __MIPS_abiflags_end = .;
+  }
+  .rodata : {
+    *(.rdata)
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+  }
+  _rom_data_copy = .;
+
+  .data ALIGN(__memory_base + 0x1000, 16) :
+  AT (_rom_data_copy)
+  {
+     _fdata = .;
+
+      *(.data)
+      *(.data.*)
+      *(.gnu.linkonce.d.*)
+
+    . = ALIGN(8);
+    _gp = . + 0x8000;
+    __global = _gp;
+
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+      *(.sdata.*)
+      *(.gnu.linkonce.s.*)
+  }
+  . = ALIGN(4);
+  PROVIDE (edata  =  .);
+  _edata  =  .;
+  _fbss = .;
+  .sbss : {
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : {
+    _bss_start = . ;
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+  }
+
+  . = ALIGN(4);
+  PROVIDE (end = .);
+  _end = .;
+  /* Now place the data that is only needed within start.S and can be
+     overwritten by the heap.  */
+  .startdata : {
+    *(.startdata)
+  }
+
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to
+     the beginning of the section so we begin them at 0.  */
+
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  .debug_ranges   0 : { *(.debug_ranges) }
+
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  /* Special sections generated by gcc */
+  /* Newer GNU linkers strip by default */
+  .mdebug.abi32            0 : { KEEP(*(.mdebug.abi32)) }
+  .mdebug.abiN32           0 : { KEEP(*(.mdebug.abiN32)) }
+  .mdebug.abi64            0 : { KEEP(*(.mdebug.abi64)) }
+  .mdebug.abiO64           0 : { KEEP(*(.mdebug.abiO64)) }
+  .mdebug.eabi32           0 : { KEEP(*(.mdebug.eabi32)) }
+  .mdebug.eabi64           0 : { KEEP(*(.mdebug.eabi64)) }
+  .gcc_compiled_long32     0 : { KEEP(*(.gcc_compiled_long32)) }
+  .gcc_compiled_long64     0 : { KEEP(*(.gcc_compiled_long64)) }
+}

cpu/mips_pic32mx/p32mx470f512h/Makefile

@@ -0,0 +1 @@
+include $(RIOTBASE)/Makefile.base

examples/javascript/Makefile

@@ -13,7 +13,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
 
 BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
                    msb-430 msb-430h qemu-i386 telosb waspmote-pro wsn430-v1_3b \
-                   wsn430-v1_4 z1 pic32-wifire
+                   wsn430-v1_4 z1 pic32-wifire pic32-clicker
 
 # Comment this out to disable code in RIOT that does safety checking
 # which is not needed in a production environment but helps in the