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boards/f4vil: Fix kconfig clk tree

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MrKevinWeiss 2022-02-09 10:43:50 +01:00
parent 04a235933d
commit 199d10ae05
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3 changed files with 7 additions and 7 deletions
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7
boards/f4vi1/Kconfig
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@ -21,4 +21,11 @@ config BOARD_F4VI1
select BOARD_HAS_HSE
select BOARD_HAS_LSE
config CLOCK_PLL_M
default 16
config CLOCK_PLL_N
default 336 if MODULE_PERIPH_USBDEV && TEST_KCONFIG
default 360
source "$(RIOTBOARD)/common/stm32/Kconfig"

3
boards/f4vi1/Makefile.features
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@ -5,6 +5,3 @@ CPU_MODEL = stm32f415rg
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# f4vi1 provides a custom default Kconfig clock configuration
KCONFIG_BOARD_CONFIG += $(RIOTBOARD)/f4vi1/clock.config

4
boards/f4vi1/clock.config
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@ -1,4 +0,0 @@
# f4vi1 provides a 16MHz HSE so they need a custom PLL config
# to remain in 180MHz max clock.
CONFIG_CUSTOM_PLL_PARAMS=y
CONFIG_CLOCK_PLL_N=90