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Merge pull request #6951 from aabadie/st-l072z-lrwan1

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boards/b-l072z-lrwan1: add basic support
This commit is contained in:
Vincent Dupont 2017-06-21 15:34:28 +02:00 committed by GitHub
commit 18d180987e
17 changed files with 8134 additions and 5 deletions
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3
boards/b-l072z-lrwan1/Makefile Normal file
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MODULE = board
include $(RIOTBASE)/Makefile.base

3
boards/b-l072z-lrwan1/Makefile.dep Normal file
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ifneq (,$(filter saul_default,$(USEMODULE)))
USEMODULE += saul_gpio
endif

13
boards/b-l072z-lrwan1/Makefile.features Normal file
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# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_hwrng
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# Load extra provided features
FEATURES_PROVIDED += cpp
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m0_1

13
boards/b-l072z-lrwan1/Makefile.include Normal file
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## the cpu to build for
export CPU = stm32l0
export CPU_MODEL = stm32l072cz
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyACM0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# setup serial terminal
include $(RIOTMAKE)/tools/serial.inc.mk
# this board uses openocd
include $(RIOTMAKE)/tools/openocd.inc.mk

35
boards/b-l072z-lrwan1/board.c Normal file
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_b-l072z-lrwan1
* @{
*
* @file
* @brief Board specific implementations for the ST b-l072z-lrwan1 discovery board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
#include "board.h"
#include "periph/gpio.h"
void board_init(void)
{
/* initialize the CPU */
cpu_init();
#ifdef AUTO_INIT_LED0
/* The LED pin is also used for SPI, so we enable it
only if explicitly wanted by the user */
gpio_init(LED0_PIN, GPIO_OUT);
#endif
}

7
boards/b-l072z-lrwan1/dist/openocd.cfg vendored Normal file
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source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32l0.cfg]
reset_config srst_only

89
boards/b-l072z-lrwan1/include/board.h Normal file
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @defgroup boards_b-l072z-lrwan1 ST b-l072z-lrwan1 discovery
* @ingroup boards
* @brief Board specific files for the ST b-l072z-lrwan1 board
* @{
*
* @file
* @brief Board specific definitions for the ST b-l072z-lrwan1 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef BOARD_H
#define BOARD_H
#include <stdint.h>
#include "cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name xtimer configuration
* @{
*/
#define XTIMER_DEV TIMER_DEV(0)
#define XTIMER_CHAN (0)
#define XTIMER_WIDTH (16)
/** @} */
/**
* @name LED pin definitions and handlers
* @{
*/
#define LED0_PIN GPIO_PIN(PORT_A, 5)
#define LED0_MASK (1 << 5)
#define LED0_ON (GPIOA->BSRR = LED0_MASK)
#define LED0_OFF (GPIOA->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOA->ODR ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_B, 5)
#define LED1_MASK (1 << 5)
#define LED1_ON (GPIOB->BSRR = LED0_MASK)
#define LED1_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED1_TOGGLE (GPIOB->ODR ^= LED0_MASK)
#define LED2_PIN GPIO_PIN(PORT_B, 6)
#define LED2_MASK (1 << 6)
#define LED2_ON (GPIOB->BSRR = LED0_MASK)
#define LED2_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED2_TOGGLE (GPIOB->ODR ^= LED0_MASK)
#define LED3_PIN GPIO_PIN(PORT_B, 7)
#define LED3_MASK (1 << 7)
#define LED3_ON (GPIOB->BSRR = LED0_MASK)
#define LED3_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED3_TOGGLE (GPIOB->ODR ^= LED0_MASK)
/** @} */
/**
* @brief User button
*/
#define BTN_B1_PIN GPIO_PIN(PORT_B, 2)
/**
* @brief Initialize board specific hardware, including clock, LEDs and std-IO
*/
void board_init(void);
#ifdef __cplusplus
}
#endif
#endif /* BOARD_H */
/** @} */

68
boards/b-l072z-lrwan1/include/gpio_params.h Normal file
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/*
* Copyright (C) Inria 2016
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-common
* @{
*
* @file
* @brief Board specific configuration of direct mapped GPIOs
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef GPIO_PARAMS_H
#define GPIO_PARAMS_H
#include "board.h"
#include "saul/periph.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief GPIO pin configuration
*/
static const saul_gpio_params_t saul_gpio_params[] =
{
#ifdef AUTO_INIT_LED0
{
.name = "LD2(red)",
.pin = LED0_PIN,
.mode = GPIO_OUT
},
#endif
{
.name = "LD1(green)",
.pin = LED1_PIN,
.mode = GPIO_OUT
},
{
.name = "LD3(blue)",
.pin = LED2_PIN,
.mode = GPIO_OUT
},
{
.name = "LD4(red)",
.pin = LED3_PIN,
.mode = GPIO_OUT
},
{
.name = "Button(B1 User)",
.pin = BTN_B1_PIN,
.mode = GPIO_IN_PU
},
};
#ifdef __cplusplus
}
#endif
#endif /* GPIO_PARAMS_H */
/** @} */

181
boards/b-l072z-lrwan1/include/periph_conf.h Normal file
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_b-l072z-lrwan1
* @{
*
* @file
* @brief Peripheral MCU configuration for the ST b-l072z-lrwan1 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
#define CLOCK_HSI (16000000U) /* internal oscillator */
#define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
/* configuration of PLL prescaler and multiply values */
/* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
#define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
#define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
/* configuration of peripheral bus clock prescalers */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
/* configuration of flash access cycles */
#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
};
#define TIMER_0_ISR isr_tim2
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART2,
.rcc_mask = RCC_APB1ENR_USART2EN,
.rx_pin = GPIO_PIN(PORT_A, 3),
.tx_pin = GPIO_PIN(PORT_A, 2),
.rx_af = GPIO_AF4,
.tx_af = GPIO_AF4,
.bus = APB1,
.irqn = USART2_IRQn
},
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF4,
.tx_af = GPIO_AF4,
.bus = APB2,
.irqn = USART1_IRQn
},
};
#define UART_0_ISR (isr_usart2)
#define UART_1_ISR (isr_usart1)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
},
{ /* for APB2 @ 32000000Hz */
7, /* -> 125000Hz */
5, /* -> 500000Hz */
4, /* -> 1000000Hz */
2, /* -> 4000000Hz */
1 /* -> 8000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
},
{
.dev = SPI1, /* connected to SX1276 */
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name DAC configuration
* @{
*/
#define DAC_NUMOF (0)
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1U)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

3
cpu/stm32l0/include/cpu_conf.h
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@ -28,6 +28,9 @@
#ifdef CPU_MODEL_STM32L073RZ
#include "vendor/stm32l073xx.h"
#endif
#ifdef CPU_MODEL_STM32L072CZ
#include "vendor/stm32l072xx.h"
#endif
#ifdef CPU_MODEL_STM32L053R8
#include "vendor/stm32l053xx.h"
#endif

7679
cpu/stm32l0/include/vendor/stm32l072xx.h vendored Normal file
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30
cpu/stm32l0/ldscripts/stm32l072cz.ld Normal file
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/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_stm32l0
* @{
*
* @file
* @brief Memory definitions for the STM32L072CZ
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 192K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
examples/dtls-echo/Makefile
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@ -13,7 +13,8 @@ BOARD_BLACKLIST := arduino-duemilanove arduino-mega2560 arduino-uno chronos \
z1 \
nrf52dk # see #6022
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 \
calliope-mini cc2650stk maple-mini \
microbit nrf51dongle nrf6310 nucleo32-f031 \
nucleo32-f042 nucleo32-f303 nucleo32-l031 nucleo-f030 \
nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 nucleo-f334 \

3
examples/gnrc_border_router/Makefile
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@ -7,7 +7,8 @@ BOARD ?= samr21-xpro
# This has to be the absolute path to the RIOT base directory:
RIOTBASE ?= $(CURDIR)/../..
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 \
calliope-mini cc2650stk maple-mini \
microbit msb-430 msb-430h nrf51dongle nrf6310 \
nucleo32-f031 nucleo32-f042 nucleo32-f303 nucleo32-l031 \
nucleo-f030 nucleo-f070 nucleo-f072 nucleo-f103 nucleo-f302 \

3
examples/javascript/Makefile
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@ -4,7 +4,8 @@ APPLICATION = riot_javascript
# default BOARD environment
BOARD ?= native
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk maple-mini \
BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 \
calliope-mini cc2650stk maple-mini \
microbit nrf51dongle nrf6310 nucleo-f030 nucleo-f070 \
nucleo-f072 nucleo-f103 nucleo-f302 nucleo-f334 nucleo-f410 \
nucleo-l053 nucleo-l073 nucleo32-f031 nucleo32-f042 \

4
tests/thread_cooperation/Makefile
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@ -1,8 +1,8 @@
APPLICATION = thread_cooperation
include ../Makefile.tests_common
BOARD_INSUFFICIENT_MEMORY := airfy-beacon calliope-mini cc2650stk chronos maple-mini \
mbed_lpc1768 microbit msb-430 msb-430h nrf51dongle \
BOARD_INSUFFICIENT_MEMORY := airfy-beacon b-l072z-lrwan1 calliope-mini cc2650stk chronos \
maple-mini mbed_lpc1768 microbit msb-430 msb-430h nrf51dongle \
nrf6310 nucleo32-f031 nucleo32-f042 nucleo32-f303 \
nucleo32-l031 nucleo-f030 nucleo-f070 nucleo-f072 \
nucleo-f103 nucleo-f302 nucleo-f334 nucleo-l053 nucleo-l073 \

2
tests/unittests/Makefile
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@ -7,6 +7,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon \
arduino-mkr1000 \
arduino-uno \
arduino-zero \
b-l072z-lrwan1 \
calliope-mini \
cc2538dk \
cc2650stk \
@ -76,6 +77,7 @@ ARM_CORTEX_M_BOARDS := airfy-beacon \
arduino-due \
arduino-mkr1000 \
arduino-zero \
b-l072z-lrwan1 \
cc2538dk \
ek-lm4f120xl \
f4vi1 \