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cpu/stm32l1: fix ADC initialization & resolution setting
Co-authored-by: benpicco <benpicco@googlemail.com>
This commit is contained in:
parent
2f8b23a596
commit
17ee40dafa
@ -131,8 +131,6 @@ int adc_init(adc_t line)
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ADC->CCR |= ADC_CCR_TSVREFE;
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}
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/* enable the ADC module */
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ADC1->CR2 = ADC_CR2_ADON;
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/* turn off during idle phase*/
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ADC1->CR1 = ADC_CR1_PDI;
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@ -157,12 +155,17 @@ int32_t adc_sample(adc_t line, adc_res_t res)
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/* lock and power on the ADC device */
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prep();
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/* set resolution, conversion channel and single read */
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ADC1->CR1 |= res & ADC_CR1_RES;
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/* mask and set resolution, conversion channel and single read */
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ADC1->CR1 = (ADC1->CR1 & ~ADC_CR1_RES) | (res & ADC_CR1_RES);
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ADC1->SQR1 &= ~ADC_SQR1_L;
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ADC1->SQR5 = adc_config[line].chan;
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/* wait for regulat channel to be ready*/
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/* only set ADON when ADONS bit is cleared (ADC not ready) */
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if (!(ADC1->SR & ADC_SR_ADONS)) {
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ADC1->CR2 |= ADC_CR2_ADON;
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}
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/* wait for regular channel to be ready*/
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while (!(ADC1->SR & ADC_SR_RCNR)) {}
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/* start conversion and wait for results */
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ADC1->CR2 |= ADC_CR2_SWSTART;
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@ -171,6 +174,10 @@ int32_t adc_sample(adc_t line, adc_res_t res)
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sample = (int)ADC1->DR;
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ADC1 -> SR &= ~ADC_SR_STRT;
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/* wait for ADC to become ready before disabling it */
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while (!(ADC1->SR & ADC_SR_ADONS)) {}
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ADC1->CR2 &= ~ADC_CR2_ADON;
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/* power off and unlock device again */
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done();
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