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mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00

cpu/stm32l1: fix ADC initialization & resolution setting

Co-authored-by: benpicco <benpicco@googlemail.com>
This commit is contained in:
crasbe 2024-11-19 16:26:31 +01:00
parent 2f8b23a596
commit 17ee40dafa

View File

@ -131,8 +131,6 @@ int adc_init(adc_t line)
ADC->CCR |= ADC_CCR_TSVREFE;
}
/* enable the ADC module */
ADC1->CR2 = ADC_CR2_ADON;
/* turn off during idle phase*/
ADC1->CR1 = ADC_CR1_PDI;
@ -157,12 +155,17 @@ int32_t adc_sample(adc_t line, adc_res_t res)
/* lock and power on the ADC device */
prep();
/* set resolution, conversion channel and single read */
ADC1->CR1 |= res & ADC_CR1_RES;
/* mask and set resolution, conversion channel and single read */
ADC1->CR1 = (ADC1->CR1 & ~ADC_CR1_RES) | (res & ADC_CR1_RES);
ADC1->SQR1 &= ~ADC_SQR1_L;
ADC1->SQR5 = adc_config[line].chan;
/* wait for regulat channel to be ready*/
/* only set ADON when ADONS bit is cleared (ADC not ready) */
if (!(ADC1->SR & ADC_SR_ADONS)) {
ADC1->CR2 |= ADC_CR2_ADON;
}
/* wait for regular channel to be ready*/
while (!(ADC1->SR & ADC_SR_RCNR)) {}
/* start conversion and wait for results */
ADC1->CR2 |= ADC_CR2_SWSTART;
@ -171,6 +174,10 @@ int32_t adc_sample(adc_t line, adc_res_t res)
sample = (int)ADC1->DR;
ADC1 -> SR &= ~ADC_SR_STRT;
/* wait for ADC to become ready before disabling it */
while (!(ADC1->SR & ADC_SR_ADONS)) {}
ADC1->CR2 &= ~ADC_CR2_ADON;
/* power off and unlock device again */
done();