From 16f6a4bb936499a7e37c02eadab6b5b0a6f775a5 Mon Sep 17 00:00:00 2001
From: Dylan Laduranty <dylan.laduranty@mesotic.com>
Date: Thu, 30 May 2024 12:01:24 +0200
Subject: [PATCH] cpu/samd21: avoid the use of bitfield

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>
---
 cpu/samd21/cpu.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/cpu/samd21/cpu.c b/cpu/samd21/cpu.c
index d673c44c95..3b5cb3b8d3 100644
--- a/cpu/samd21/cpu.c
+++ b/cpu/samd21/cpu.c
@@ -130,10 +130,8 @@ static void clk_init(void)
 
 #if CLOCK_8MHZ
     /* configure internal 8MHz oscillator to run without prescaler */
-    SYSCTRL->OSC8M.bit.PRESC = 0;
-    SYSCTRL->OSC8M.bit.ONDEMAND = 1;
-    SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
-    SYSCTRL->OSC8M.bit.ENABLE = 1;
+    SYSCTRL->OSC8M.reg &= ~(SYSCTRL_OSC8M_PRESC_Msk);
+    SYSCTRL->OSC8M.reg |= (SYSCTRL_OSC8M_ONDEMAND | SYSCTRL_OSC8M_ENABLE);
     while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY)) {}
 #endif
 
@@ -144,7 +142,7 @@ static void clk_init(void)
                             SYSCTRL_XOSC32K_STARTUP(XOSC32_STARTUP_TIME) |
                             SYSCTRL_XOSC32K_RUNSTDBY;
     /* Enable XOSC32 with Separate Call */
-    SYSCTRL->XOSC32K.bit.ENABLE = 1;
+    SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE;
 #endif
 
     /* reset the GCLK module so it is in a known state */
@@ -202,7 +200,7 @@ static void clk_init(void)
     while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
 
     /* Disable ONDEMAND mode while writing configurations */
-    SYSCTRL->DFLLCTRL.bit.ONDEMAND = 0;
+    SYSCTRL->DFLLCTRL.reg &= ~(SYSCTRL_DFLLCTRL_ONDEMAND);
     while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
         /* Wait for DFLL sync */
     }
@@ -221,7 +219,7 @@ static void clk_init(void)
         /* Wait for DFLL sync */
     }
 
-    SYSCTRL->DFLLCTRL.bit.ENABLE = 1;
+    SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE;
     uint32_t mask = SYSCTRL_PCLKSR_DFLLRDY |
                     SYSCTRL_PCLKSR_DFLLLCKF |
                     SYSCTRL_PCLKSR_DFLLLCKC;
@@ -237,7 +235,7 @@ static void clk_init(void)
                       | GCLK_CLKCTRL_GEN(SAM0_GCLK_MAIN);
     while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
 
-    SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
+    SYSCTRL->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND;
     while ((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) == 0) {
         /* Wait for DFLL sync */
     }
@@ -265,14 +263,14 @@ static void clk_init(void)
     /* redirect all peripherals to a disabled clock generator (7) by default */
     for (unsigned i = 0x3; i <= GCLK_CLKCTRL_ID_Msk; i++) {
         GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(i) | GCLK_CLKCTRL_GEN(SAM0_GCLK_DISABLED);
-        while (GCLK->STATUS.bit.SYNCBUSY) {}
+        while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
     }
 }
 
 void cpu_init(void)
 {
     /* disable the watchdog timer */
-    WDT->CTRL.bit.ENABLE = 0;
+    WDT->CTRL.reg = 0;
     /* initialize the Cortex-M core */
     cortexm_init();
     /* Initialise clock sources and generic clocks */