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cpu/efm32: add family EFM32GG11 (generated with EFM2RIOT)
This commit is contained in:
Gunar Schorcht
parent
f32b661666
commit
165f86ad4c
328
cpu/efm32/families/efm32gg11b/Kconfig
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328
cpu/efm32/families/efm32gg11b/Kconfig
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# Copyright (c) 2020 HAW Hamburg
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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config CPU_FAM_EFM32GG11B
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bool
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select CPU_CORE_CORTEX_M4F
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select CPU_COMMON_EFM32
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select CPU_EFM32_SERIES1
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select HAS_PERIPH_HWRNG
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select HAS_CORTEXM_MPU
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config MODULE_CPU_EFM32GG11B
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bool
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depends on CPU_FAM_EFM32GG11B
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depends on TEST_KCONFIG
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default y
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help
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EFM32GG11B family-specific code.
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## CPU Models
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config CPU_MODEL_EFM32GG11B510F2048IL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B120F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B120F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GL152
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048IL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048GL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048IL112
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048IQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B310F2048GL112
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GL152
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B310F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048IQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B110F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B110F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048IL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024IQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GL192
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B320F2048GL112
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048IQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B110F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B110F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B320F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048GL112
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048GQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024IL152
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048GL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024IL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B520F2048IL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GL192
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B120F2048IM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B120F2048GQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048IQ100
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B420F2048GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B510F2048GL120
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024IQ64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B840F1024GM64
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bool
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select CPU_FAM_EFM32GG11B
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config CPU_MODEL_EFM32GG11B820F2048IL152
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bool
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select CPU_FAM_EFM32GG11B
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## Common CPU symbols
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config CPU_FAM
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default "efm32gg11b" if CPU_FAM_EFM32GG11B
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config CPU_MODEL
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default "efm32gg11b510f2048il120" if CPU_MODEL_EFM32GG11B510F2048IL120
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default "efm32gg11b120f2048gm64" if CPU_MODEL_EFM32GG11B120F2048GM64
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default "efm32gg11b120f2048iq64" if CPU_MODEL_EFM32GG11B120F2048IQ64
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default "efm32gg11b820f2048gl152" if CPU_MODEL_EFM32GG11B820F2048GL152
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default "efm32gg11b520f2048im64" if CPU_MODEL_EFM32GG11B520F2048IM64
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default "efm32gg11b520f2048gq64" if CPU_MODEL_EFM32GG11B520F2048GQ64
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default "efm32gg11b840f1024gl120" if CPU_MODEL_EFM32GG11B840F1024GL120
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default "efm32gg11b420f2048il120" if CPU_MODEL_EFM32GG11B420F2048IL120
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default "efm32gg11b520f2048gl120" if CPU_MODEL_EFM32GG11B520F2048GL120
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default "efm32gg11b840f1024gq64" if CPU_MODEL_EFM32GG11B840F1024GQ64
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default "efm32gg11b840f1024im64" if CPU_MODEL_EFM32GG11B840F1024IM64
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default "efm32gg11b820f2048gq100" if CPU_MODEL_EFM32GG11B820F2048GQ100
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default "efm32gg11b420f2048gq64" if CPU_MODEL_EFM32GG11B420F2048GQ64
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default "efm32gg11b420f2048im64" if CPU_MODEL_EFM32GG11B420F2048IM64
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default "efm32gg11b420f2048il112" if CPU_MODEL_EFM32GG11B420F2048IL112
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default "efm32gg11b510f2048iq100" if CPU_MODEL_EFM32GG11B510F2048IQ100
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default "efm32gg11b310f2048gl112" if CPU_MODEL_EFM32GG11B310F2048GL112
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default "efm32gg11b840f1024gl152" if CPU_MODEL_EFM32GG11B840F1024GL152
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default "efm32gg11b310f2048gq100" if CPU_MODEL_EFM32GG11B310F2048GQ100
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default "efm32gg11b510f2048gq64" if CPU_MODEL_EFM32GG11B510F2048GQ64
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default "efm32gg11b510f2048im64" if CPU_MODEL_EFM32GG11B510F2048IM64
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default "efm32gg11b820f2048gq64" if CPU_MODEL_EFM32GG11B820F2048GQ64
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default "efm32gg11b820f2048gl120" if CPU_MODEL_EFM32GG11B820F2048GL120
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default "efm32gg11b820f2048im64" if CPU_MODEL_EFM32GG11B820F2048IM64
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default "efm32gg11b420f2048iq100" if CPU_MODEL_EFM32GG11B420F2048IQ100
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default "efm32gg11b840f1024gq100" if CPU_MODEL_EFM32GG11B840F1024GQ100
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default "efm32gg11b110f2048iq64" if CPU_MODEL_EFM32GG11B110F2048IQ64
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default "efm32gg11b110f2048gm64" if CPU_MODEL_EFM32GG11B110F2048GM64
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default "efm32gg11b520f2048gq100" if CPU_MODEL_EFM32GG11B520F2048GQ100
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default "efm32gg11b820f2048il120" if CPU_MODEL_EFM32GG11B820F2048IL120
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default "efm32gg11b840f1024iq100" if CPU_MODEL_EFM32GG11B840F1024IQ100
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default "efm32gg11b420f2048gq100" if CPU_MODEL_EFM32GG11B420F2048GQ100
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default "efm32gg11b820f2048gl192" if CPU_MODEL_EFM32GG11B820F2048GL192
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default "efm32gg11b320f2048gl112" if CPU_MODEL_EFM32GG11B320F2048GL112
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default "efm32gg11b520f2048iq100" if CPU_MODEL_EFM32GG11B520F2048IQ100
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default "efm32gg11b110f2048gq64" if CPU_MODEL_EFM32GG11B110F2048GQ64
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default "efm32gg11b110f2048im64" if CPU_MODEL_EFM32GG11B110F2048IM64
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default "efm32gg11b320f2048gq100" if CPU_MODEL_EFM32GG11B320F2048GQ100
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default "efm32gg11b420f2048gl112" if CPU_MODEL_EFM32GG11B420F2048GL112
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default "efm32gg11b510f2048gq100" if CPU_MODEL_EFM32GG11B510F2048GQ100
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default "efm32gg11b820f2048iq64" if CPU_MODEL_EFM32GG11B820F2048IQ64
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default "efm32gg11b820f2048gm64" if CPU_MODEL_EFM32GG11B820F2048GM64
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default "efm32gg11b510f2048iq64" if CPU_MODEL_EFM32GG11B510F2048IQ64
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default "efm32gg11b510f2048gm64" if CPU_MODEL_EFM32GG11B510F2048GM64
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default "efm32gg11b840f1024il152" if CPU_MODEL_EFM32GG11B840F1024IL152
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default "efm32gg11b420f2048gl120" if CPU_MODEL_EFM32GG11B420F2048GL120
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default "efm32gg11b840f1024il120" if CPU_MODEL_EFM32GG11B840F1024IL120
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default "efm32gg11b520f2048gm64" if CPU_MODEL_EFM32GG11B520F2048GM64
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default "efm32gg11b520f2048iq64" if CPU_MODEL_EFM32GG11B520F2048IQ64
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default "efm32gg11b520f2048il120" if CPU_MODEL_EFM32GG11B520F2048IL120
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default "efm32gg11b840f1024gl192" if CPU_MODEL_EFM32GG11B840F1024GL192
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default "efm32gg11b120f2048im64" if CPU_MODEL_EFM32GG11B120F2048IM64
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default "efm32gg11b120f2048gq64" if CPU_MODEL_EFM32GG11B120F2048GQ64
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default "efm32gg11b820f2048iq100" if CPU_MODEL_EFM32GG11B820F2048IQ100
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default "efm32gg11b420f2048iq64" if CPU_MODEL_EFM32GG11B420F2048IQ64
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default "efm32gg11b420f2048gm64" if CPU_MODEL_EFM32GG11B420F2048GM64
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default "efm32gg11b510f2048gl120" if CPU_MODEL_EFM32GG11B510F2048GL120
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default "efm32gg11b840f1024iq64" if CPU_MODEL_EFM32GG11B840F1024IQ64
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default "efm32gg11b840f1024gm64" if CPU_MODEL_EFM32GG11B840F1024GM64
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default "efm32gg11b820f2048il152" if CPU_MODEL_EFM32GG11B820F2048IL152
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6
cpu/efm32/families/efm32gg11b/Makefile
Normal file
6
cpu/efm32/families/efm32gg11b/Makefile
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MODULE = cpu_efm32gg11b
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# (file triggers compiler bug. see #5775)
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SRC_NOLTO += vectors.c
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include $(RIOTBASE)/Makefile.base
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7
cpu/efm32/families/efm32gg11b/Makefile.include
Normal file
7
cpu/efm32/families/efm32gg11b/Makefile.include
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# Find the header file that should exist if the CPU is supported. Only headers
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# for supported boards are included, but to support another CPU, it should be
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# as easy as adding the header file only.
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EFM32_HEADER = $(wildcard $(RIOTCPU)/efm32/families/efm32gg11b/include/vendor/$(CPU_MODEL).h)
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# include vendor device headers
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INCLUDES += -I$(RIOTCPU)/efm32/families/efm32gg11b/include/vendor
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65
cpu/efm32/families/efm32gg11b/efm32-info.mk
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65
cpu/efm32/families/efm32gg11b/efm32-info.mk
Normal file
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# This file is automatically generated, and should not be changed. There is
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# probably little reason to edit this file anyway, since it should already
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# contain all information for the EFM32GG11B family of CPUs.
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# Series - Architecture - Flash base - Flash size - SRAM base - SRAM size - Crypto? - TRNG? - Radio?
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EFM32_INFO_efm32gg11b510f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
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EFM32_INFO_efm32gg11b120f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b120f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b820f2048gl152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b520f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b520f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b840f1024gl120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b420f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b520f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
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EFM32_INFO_efm32gg11b840f1024gq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024im64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048il112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b310f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gl152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b310f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024iq100 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gl192 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b320f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b110f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b320f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gl112 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024il152 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024il120 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b520f2048il120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gl192 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048im64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b120f2048gq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048iq100 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048iq64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b420f2048gm64 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b510f2048gl120 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00060000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024iq64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b840f1024gm64 = 1 cortex-m4f 0x00000000 0x00100000 0x20000000 0x00080000 1 1 0
|
||||
EFM32_INFO_efm32gg11b820f2048il152 = 1 cortex-m4f 0x00000000 0x00200000 0x20000000 0x00080000 1 1 0
|
||||
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b110f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h
vendored
Normal file
9940
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b120f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b310f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h
vendored
Normal file
9976
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b320f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il112.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h
vendored
Normal file
1921
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b420f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b510f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h
vendored
Normal file
9978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b520f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gl192.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gm64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048gq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048il152.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048im64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq100.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b820f2048iq64.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h
vendored
Normal file
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl120.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl152.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gl192.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gm64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq100.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024gq64.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il120.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024il152.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024im64.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq100.h
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1923
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b840f1024iq64.h
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1390
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_acmp.h
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2435
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_adc.h
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403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h
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cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_pins.h
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@ -0,0 +1,403 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_AF_PINS register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_AF_Pins Alternate Function Pins
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
#define AF_CMU_CLK0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 12 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 12 : -1) /**< Pin number for AF_CMU_CLK0 location number i */
|
||||
#define AF_CMU_CLK1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 11 : -1) /**< Pin number for AF_CMU_CLK1 location number i */
|
||||
#define AF_CMU_CLK2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 10 : -1) /**< Pin number for AF_CMU_CLK2 location number i */
|
||||
#define AF_CMU_CLKI0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 10 : (i) == 6 ? 12 : (i) == 7 ? 11 : -1) /**< Pin number for AF_CMU_CLKI0 location number i */
|
||||
#define AF_CMU_DIGEXTCLK_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_DIGEXTCLK location number i */
|
||||
#define AF_CMU_IOPOVR_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_CMU_IOPOVR location number i */
|
||||
#define AF_CMU_IONOVR_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_CMU_IONOVR location number i */
|
||||
#define AF_LESENSE_CH0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_LESENSE_CH0 location number i */
|
||||
#define AF_LESENSE_CH1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_LESENSE_CH1 location number i */
|
||||
#define AF_LESENSE_CH2_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_LESENSE_CH2 location number i */
|
||||
#define AF_LESENSE_CH3_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_CH3 location number i */
|
||||
#define AF_LESENSE_CH4_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_CH4 location number i */
|
||||
#define AF_LESENSE_CH5_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_CH5 location number i */
|
||||
#define AF_LESENSE_CH6_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_CH6 location number i */
|
||||
#define AF_LESENSE_CH7_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_CH7 location number i */
|
||||
#define AF_LESENSE_CH8_PIN(i) ((i) == 0 ? 8 : -1) /**< Pin number for AF_LESENSE_CH8 location number i */
|
||||
#define AF_LESENSE_CH9_PIN(i) ((i) == 0 ? 9 : -1) /**< Pin number for AF_LESENSE_CH9 location number i */
|
||||
#define AF_LESENSE_CH10_PIN(i) ((i) == 0 ? 10 : -1) /**< Pin number for AF_LESENSE_CH10 location number i */
|
||||
#define AF_LESENSE_CH11_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_CH11 location number i */
|
||||
#define AF_LESENSE_CH12_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_CH12 location number i */
|
||||
#define AF_LESENSE_CH13_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_CH13 location number i */
|
||||
#define AF_LESENSE_CH14_PIN(i) ((i) == 0 ? 14 : -1) /**< Pin number for AF_LESENSE_CH14 location number i */
|
||||
#define AF_LESENSE_CH15_PIN(i) ((i) == 0 ? 15 : -1) /**< Pin number for AF_LESENSE_CH15 location number i */
|
||||
#define AF_LESENSE_ALTEX0_PIN(i) ((i) == 0 ? 6 : -1) /**< Pin number for AF_LESENSE_ALTEX0 location number i */
|
||||
#define AF_LESENSE_ALTEX1_PIN(i) ((i) == 0 ? 7 : -1) /**< Pin number for AF_LESENSE_ALTEX1 location number i */
|
||||
#define AF_LESENSE_ALTEX2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_LESENSE_ALTEX2 location number i */
|
||||
#define AF_LESENSE_ALTEX3_PIN(i) ((i) == 0 ? 4 : -1) /**< Pin number for AF_LESENSE_ALTEX3 location number i */
|
||||
#define AF_LESENSE_ALTEX4_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_LESENSE_ALTEX4 location number i */
|
||||
#define AF_LESENSE_ALTEX5_PIN(i) ((i) == 0 ? 11 : -1) /**< Pin number for AF_LESENSE_ALTEX5 location number i */
|
||||
#define AF_LESENSE_ALTEX6_PIN(i) ((i) == 0 ? 12 : -1) /**< Pin number for AF_LESENSE_ALTEX6 location number i */
|
||||
#define AF_LESENSE_ALTEX7_PIN(i) ((i) == 0 ? 13 : -1) /**< Pin number for AF_LESENSE_ALTEX7 location number i */
|
||||
#define AF_EBI_AD00_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 0 : -1) /**< Pin number for AF_EBI_AD00 location number i */
|
||||
#define AF_EBI_AD01_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 1 : -1) /**< Pin number for AF_EBI_AD01 location number i */
|
||||
#define AF_EBI_AD02_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Pin number for AF_EBI_AD02 location number i */
|
||||
#define AF_EBI_AD03_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 3 : -1) /**< Pin number for AF_EBI_AD03 location number i */
|
||||
#define AF_EBI_AD04_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : (i) == 2 ? 4 : -1) /**< Pin number for AF_EBI_AD04 location number i */
|
||||
#define AF_EBI_AD05_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 5 : (i) == 2 ? 5 : -1) /**< Pin number for AF_EBI_AD05 location number i */
|
||||
#define AF_EBI_AD06_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 6 : -1) /**< Pin number for AF_EBI_AD06 location number i */
|
||||
#define AF_EBI_AD07_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 0 : (i) == 2 ? 7 : -1) /**< Pin number for AF_EBI_AD07 location number i */
|
||||
#define AF_EBI_AD08_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 8 : -1) /**< Pin number for AF_EBI_AD08 location number i */
|
||||
#define AF_EBI_AD09_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_EBI_AD09 location number i */
|
||||
#define AF_EBI_AD10_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_EBI_AD10 location number i */
|
||||
#define AF_EBI_AD11_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 11 : -1) /**< Pin number for AF_EBI_AD11 location number i */
|
||||
#define AF_EBI_AD12_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 12 : -1) /**< Pin number for AF_EBI_AD12 location number i */
|
||||
#define AF_EBI_AD13_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : -1) /**< Pin number for AF_EBI_AD13 location number i */
|
||||
#define AF_EBI_AD14_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 14 : -1) /**< Pin number for AF_EBI_AD14 location number i */
|
||||
#define AF_EBI_AD15_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 15 : -1) /**< Pin number for AF_EBI_AD15 location number i */
|
||||
#define AF_EBI_CS0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 8 : -1) /**< Pin number for AF_EBI_CS0 location number i */
|
||||
#define AF_EBI_CS1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 9 : -1) /**< Pin number for AF_EBI_CS1 location number i */
|
||||
#define AF_EBI_CS2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 10 : -1) /**< Pin number for AF_EBI_CS2 location number i */
|
||||
#define AF_EBI_CS3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 11 : -1) /**< Pin number for AF_EBI_CS3 location number i */
|
||||
#define AF_EBI_ARDY_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 13 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 10 : -1) /**< Pin number for AF_EBI_ARDY location number i */
|
||||
#define AF_EBI_ALE_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 11 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_ALE location number i */
|
||||
#define AF_EBI_WEn_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 6 : (i) == 4 ? 8 : (i) == 5 ? 4 : -1) /**< Pin number for AF_EBI_WEn location number i */
|
||||
#define AF_EBI_REn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 0 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_EBI_REn location number i */
|
||||
#define AF_EBI_BL0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 8 : (i) == 2 ? 10 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Pin number for AF_EBI_BL0 location number i */
|
||||
#define AF_EBI_BL1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 3 : (i) == 4 ? 7 : (i) == 5 ? 7 : -1) /**< Pin number for AF_EBI_BL1 location number i */
|
||||
#define AF_EBI_NANDWEn_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 13 : (i) == 3 ? 2 : (i) == 4 ? 14 : (i) == 5 ? 11 : -1) /**< Pin number for AF_EBI_NANDWEn location number i */
|
||||
#define AF_EBI_NANDREn_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 15 : (i) == 2 ? 9 : (i) == 3 ? 4 : (i) == 4 ? 15 : (i) == 5 ? 12 : -1) /**< Pin number for AF_EBI_NANDREn location number i */
|
||||
#define AF_EBI_A00_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A00 location number i */
|
||||
#define AF_EBI_A01_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A01 location number i */
|
||||
#define AF_EBI_A02_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A02 location number i */
|
||||
#define AF_EBI_A03_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A03 location number i */
|
||||
#define AF_EBI_A04_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A04 location number i */
|
||||
#define AF_EBI_A05_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A05 location number i */
|
||||
#define AF_EBI_A06_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 4 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A06 location number i */
|
||||
#define AF_EBI_A07_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 13 : -1) /**< Pin number for AF_EBI_A07 location number i */
|
||||
#define AF_EBI_A08_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : -1) /**< Pin number for AF_EBI_A08 location number i */
|
||||
#define AF_EBI_A09_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A09 location number i */
|
||||
#define AF_EBI_A10_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 10 : -1) /**< Pin number for AF_EBI_A10 location number i */
|
||||
#define AF_EBI_A11_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 6 : (i) == 3 ? 11 : -1) /**< Pin number for AF_EBI_A11 location number i */
|
||||
#define AF_EBI_A12_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 8 : (i) == 2 ? 7 : (i) == 3 ? 12 : -1) /**< Pin number for AF_EBI_A12 location number i */
|
||||
#define AF_EBI_A13_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 7 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_A13 location number i */
|
||||
#define AF_EBI_A14_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 9 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_A14 location number i */
|
||||
#define AF_EBI_A15_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 10 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_A15 location number i */
|
||||
#define AF_EBI_A16_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_A16 location number i */
|
||||
#define AF_EBI_A17_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A17 location number i */
|
||||
#define AF_EBI_A18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A18 location number i */
|
||||
#define AF_EBI_A19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A19 location number i */
|
||||
#define AF_EBI_A20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 8 : (i) == 2 ? 8 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A20 location number i */
|
||||
#define AF_EBI_A21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 9 : (i) == 2 ? 9 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A21 location number i */
|
||||
#define AF_EBI_A22_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 10 : (i) == 2 ? 10 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_A22 location number i */
|
||||
#define AF_EBI_A23_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 11 : (i) == 2 ? 11 : (i) == 3 ? 5 : -1) /**< Pin number for AF_EBI_A23 location number i */
|
||||
#define AF_EBI_A24_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 12 : (i) == 3 ? 6 : -1) /**< Pin number for AF_EBI_A24 location number i */
|
||||
#define AF_EBI_A25_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 13 : (i) == 3 ? 7 : -1) /**< Pin number for AF_EBI_A25 location number i */
|
||||
#define AF_EBI_A26_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 14 : (i) == 3 ? 8 : -1) /**< Pin number for AF_EBI_A26 location number i */
|
||||
#define AF_EBI_A27_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_EBI_A27 location number i */
|
||||
#define AF_EBI_CSTFT_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 0 : -1) /**< Pin number for AF_EBI_CSTFT location number i */
|
||||
#define AF_EBI_DCLK_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 7 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Pin number for AF_EBI_DCLK location number i */
|
||||
#define AF_EBI_DTEN_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 9 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_EBI_DTEN location number i */
|
||||
#define AF_EBI_VSNC_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 10 : (i) == 2 ? 2 : (i) == 3 ? 3 : -1) /**< Pin number for AF_EBI_VSNC location number i */
|
||||
#define AF_EBI_HSNC_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 11 : (i) == 2 ? 3 : (i) == 3 ? 4 : -1) /**< Pin number for AF_EBI_HSNC location number i */
|
||||
#define AF_ETH_MIITXCLK_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : -1) /**< Pin number for AF_ETH_MIITXCLK location number i */
|
||||
#define AF_ETH_MIITXD3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : -1) /**< Pin number for AF_ETH_MIITXD3 location number i */
|
||||
#define AF_ETH_MIITXD2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : -1) /**< Pin number for AF_ETH_MIITXD2 location number i */
|
||||
#define AF_ETH_MIITXD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : -1) /**< Pin number for AF_ETH_MIITXD1 location number i */
|
||||
#define AF_ETH_MIITXD0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Pin number for AF_ETH_MIITXD0 location number i */
|
||||
#define AF_ETH_MIITXEN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : -1) /**< Pin number for AF_ETH_MIITXEN location number i */
|
||||
#define AF_ETH_MIITXER_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_MIITXER location number i */
|
||||
#define AF_ETH_MIIRXCLK_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 12 : -1) /**< Pin number for AF_ETH_MIIRXCLK location number i */
|
||||
#define AF_ETH_MIIRXD3_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 11 : -1) /**< Pin number for AF_ETH_MIIRXD3 location number i */
|
||||
#define AF_ETH_MIIRXD2_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 10 : -1) /**< Pin number for AF_ETH_MIIRXD2 location number i */
|
||||
#define AF_ETH_MIIRXD1_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD1 location number i */
|
||||
#define AF_ETH_MIIRXD0_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 11 : (i) == 2 ? 9 : -1) /**< Pin number for AF_ETH_MIIRXD0 location number i */
|
||||
#define AF_ETH_MIIRXDV_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 12 : (i) == 2 ? 8 : -1) /**< Pin number for AF_ETH_MIIRXDV location number i */
|
||||
#define AF_ETH_MIIRXER_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 7 : -1) /**< Pin number for AF_ETH_MIIRXER location number i */
|
||||
#define AF_ETH_MIICRS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 3 : -1) /**< Pin number for AF_ETH_MIICRS location number i */
|
||||
#define AF_ETH_MIICOL_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 4 : -1) /**< Pin number for AF_ETH_MIICOL location number i */
|
||||
#define AF_ETH_MDIO_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 0 : (i) == 3 ? 15 : -1) /**< Pin number for AF_ETH_MDIO location number i */
|
||||
#define AF_ETH_MDC_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 1 : (i) == 3 ? 6 : -1) /**< Pin number for AF_ETH_MDC location number i */
|
||||
#define AF_ETH_TSUEXTCLK_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 2 : (i) == 3 ? 8 : -1) /**< Pin number for AF_ETH_TSUEXTCLK location number i */
|
||||
#define AF_ETH_TSUTMRTOG_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 15 : (i) == 2 ? 3 : (i) == 3 ? 9 : -1) /**< Pin number for AF_ETH_TSUTMRTOG location number i */
|
||||
#define AF_ETH_RMIITXD1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : -1) /**< Pin number for AF_ETH_RMIITXD1 location number i */
|
||||
#define AF_ETH_RMIITXD0_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : -1) /**< Pin number for AF_ETH_RMIITXD0 location number i */
|
||||
#define AF_ETH_RMIITXEN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : -1) /**< Pin number for AF_ETH_RMIITXEN location number i */
|
||||
#define AF_ETH_RMIIRXD1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD1 location number i */
|
||||
#define AF_ETH_RMIIRXD0_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 9 : -1) /**< Pin number for AF_ETH_RMIIRXD0 location number i */
|
||||
#define AF_ETH_RMIIREFCLK_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 10 : -1) /**< Pin number for AF_ETH_RMIIREFCLK location number i */
|
||||
#define AF_ETH_RMIICRSDV_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : -1) /**< Pin number for AF_ETH_RMIICRSDV location number i */
|
||||
#define AF_ETH_RMIIRXER_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : -1) /**< Pin number for AF_ETH_RMIIRXER location number i */
|
||||
#define AF_SDIO_CLK_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : -1) /**< Pin number for AF_SDIO_CLK location number i */
|
||||
#define AF_SDIO_CMD_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : -1) /**< Pin number for AF_SDIO_CMD location number i */
|
||||
#define AF_SDIO_DAT0_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : -1) /**< Pin number for AF_SDIO_DAT0 location number i */
|
||||
#define AF_SDIO_DAT1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 1 : -1) /**< Pin number for AF_SDIO_DAT1 location number i */
|
||||
#define AF_SDIO_DAT2_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : -1) /**< Pin number for AF_SDIO_DAT2 location number i */
|
||||
#define AF_SDIO_DAT3_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT3 location number i */
|
||||
#define AF_SDIO_DAT4_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT4 location number i */
|
||||
#define AF_SDIO_DAT5_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 5 : -1) /**< Pin number for AF_SDIO_DAT5 location number i */
|
||||
#define AF_SDIO_DAT6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : -1) /**< Pin number for AF_SDIO_DAT6 location number i */
|
||||
#define AF_SDIO_DAT7_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : -1) /**< Pin number for AF_SDIO_DAT7 location number i */
|
||||
#define AF_SDIO_CD_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 4 : (i) == 2 ? 6 : (i) == 3 ? 10 : -1) /**< Pin number for AF_SDIO_CD location number i */
|
||||
#define AF_SDIO_WP_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 5 : (i) == 2 ? 15 : (i) == 3 ? 9 : -1) /**< Pin number for AF_SDIO_WP location number i */
|
||||
#define AF_PRS_CH0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 14 : (i) == 3 ? 2 : -1) /**< Pin number for AF_PRS_CH0 location number i */
|
||||
#define AF_PRS_CH1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 15 : (i) == 3 ? 12 : -1) /**< Pin number for AF_PRS_CH1 location number i */
|
||||
#define AF_PRS_CH2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 10 : (i) == 3 ? 13 : -1) /**< Pin number for AF_PRS_CH2 location number i */
|
||||
#define AF_PRS_CH3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 0 : -1) /**< Pin number for AF_PRS_CH3 location number i */
|
||||
#define AF_PRS_CH4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Pin number for AF_PRS_CH4 location number i */
|
||||
#define AF_PRS_CH5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH5 location number i */
|
||||
#define AF_PRS_CH6_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH6 location number i */
|
||||
#define AF_PRS_CH7_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 7 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH7 location number i */
|
||||
#define AF_PRS_CH8_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 9 : -1) /**< Pin number for AF_PRS_CH8 location number i */
|
||||
#define AF_PRS_CH9_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 10 : -1) /**< Pin number for AF_PRS_CH9 location number i */
|
||||
#define AF_PRS_CH10_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH10 location number i */
|
||||
#define AF_PRS_CH11_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH11 location number i */
|
||||
#define AF_PRS_CH12_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_PRS_CH12 location number i */
|
||||
#define AF_PRS_CH13_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 9 : (i) == 2 ? 14 : -1) /**< Pin number for AF_PRS_CH13 location number i */
|
||||
#define AF_PRS_CH14_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 6 : (i) == 2 ? 15 : -1) /**< Pin number for AF_PRS_CH14 location number i */
|
||||
#define AF_PRS_CH15_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 7 : (i) == 2 ? 0 : -1) /**< Pin number for AF_PRS_CH15 location number i */
|
||||
#define AF_PRS_CH16_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH16 location number i */
|
||||
#define AF_PRS_CH17_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH17 location number i */
|
||||
#define AF_PRS_CH18_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 10 : (i) == 2 ? 4 : -1) /**< Pin number for AF_PRS_CH18 location number i */
|
||||
#define AF_PRS_CH19_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 11 : (i) == 2 ? 5 : -1) /**< Pin number for AF_PRS_CH19 location number i */
|
||||
#define AF_PRS_CH20_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 12 : (i) == 2 ? 2 : -1) /**< Pin number for AF_PRS_CH20 location number i */
|
||||
#define AF_PRS_CH21_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 11 : -1) /**< Pin number for AF_PRS_CH21 location number i */
|
||||
#define AF_PRS_CH22_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Pin number for AF_PRS_CH22 location number i */
|
||||
#define AF_PRS_CH23_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 7 : -1) /**< Pin number for AF_PRS_CH23 location number i */
|
||||
#define AF_CAN0_RX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 9 : (i) == 4 ? 8 : (i) == 5 ? 14 : (i) == 6 ? 0 : (i) == 7 ? 12 : -1) /**< Pin number for AF_CAN0_RX location number i */
|
||||
#define AF_CAN0_TX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 10 : (i) == 4 ? 9 : (i) == 5 ? 15 : (i) == 6 ? 1 : (i) == 7 ? 13 : -1) /**< Pin number for AF_CAN0_TX location number i */
|
||||
#define AF_CAN1_RX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 12 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_CAN1_RX location number i */
|
||||
#define AF_CAN1_TX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 11 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_CAN1_TX location number i */
|
||||
#define AF_TIMER0_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 8 : (i) == 7 ? 1 : -1) /**< Pin number for AF_TIMER0_CC0 location number i */
|
||||
#define AF_TIMER0_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 5 : (i) == 6 ? 9 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER0_CC1 location number i */
|
||||
#define AF_TIMER0_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER0_CC2 location number i */
|
||||
#define AF_TIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CC3 location number i */
|
||||
#define AF_TIMER0_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 7 : -1) /**< Pin number for AF_TIMER0_CDTI0 location number i */
|
||||
#define AF_TIMER0_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 8 : -1) /**< Pin number for AF_TIMER0_CDTI1 location number i */
|
||||
#define AF_TIMER0_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 5 : (i) == 3 ? 4 : (i) == 4 ? 11 : -1) /**< Pin number for AF_TIMER0_CDTI2 location number i */
|
||||
#define AF_TIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER0_CDTI3 location number i */
|
||||
#define AF_TIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 10 : (i) == 2 ? 0 : (i) == 3 ? 7 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 13 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER1_CC0 location number i */
|
||||
#define AF_TIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 11 : (i) == 2 ? 1 : (i) == 3 ? 8 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 14 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER1_CC1 location number i */
|
||||
#define AF_TIMER1_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 12 : (i) == 2 ? 2 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 4 : (i) == 6 ? 15 : (i) == 7 ? 8 : -1) /**< Pin number for AF_TIMER1_CC2 location number i */
|
||||
#define AF_TIMER1_CC3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 12 : (i) == 6 ? 5 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER1_CC3 location number i */
|
||||
#define AF_TIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI0 location number i */
|
||||
#define AF_TIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI1 location number i */
|
||||
#define AF_TIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI2 location number i */
|
||||
#define AF_TIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER1_CDTI3 location number i */
|
||||
#define AF_TIMER2_CC0_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 12 : (i) == 2 ? 8 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 8 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER2_CC0 location number i */
|
||||
#define AF_TIMER2_CC1_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 13 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 9 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER2_CC1 location number i */
|
||||
#define AF_TIMER2_CC2_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 13 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 10 : (i) == 7 ? 7 : -1) /**< Pin number for AF_TIMER2_CC2 location number i */
|
||||
#define AF_TIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CC3 location number i */
|
||||
#define AF_TIMER2_CDTI0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 13 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Pin number for AF_TIMER2_CDTI0 location number i */
|
||||
#define AF_TIMER2_CDTI1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 14 : (i) == 2 ? 14 : (i) == 3 ? 1 : -1) /**< Pin number for AF_TIMER2_CDTI1 location number i */
|
||||
#define AF_TIMER2_CDTI2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 15 : (i) == 3 ? 2 : -1) /**< Pin number for AF_TIMER2_CDTI2 location number i */
|
||||
#define AF_TIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER2_CDTI3 location number i */
|
||||
#define AF_TIMER3_CC0_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 3 : (i) == 6 ? 6 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC0 location number i */
|
||||
#define AF_TIMER3_CC1_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 4 : (i) == 6 ? 13 : (i) == 7 ? 15 : -1) /**< Pin number for AF_TIMER3_CC1 location number i */
|
||||
#define AF_TIMER3_CC2_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 14 : (i) == 7 ? 0 : -1) /**< Pin number for AF_TIMER3_CC2 location number i */
|
||||
#define AF_TIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CC3 location number i */
|
||||
#define AF_TIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI0 location number i */
|
||||
#define AF_TIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI1 location number i */
|
||||
#define AF_TIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI2 location number i */
|
||||
#define AF_TIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER3_CDTI3 location number i */
|
||||
#define AF_TIMER4_CC0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 6 : (i) == 5 ? 9 : (i) == 6 ? 11 : (i) == 7 ? 9 : -1) /**< Pin number for AF_TIMER4_CC0 location number i */
|
||||
#define AF_TIMER4_CC1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 14 : (i) == 2 ? 6 : (i) == 3 ? 9 : (i) == 4 ? 7 : (i) == 5 ? 9 : (i) == 6 ? 12 : (i) == 7 ? 10 : -1) /**< Pin number for AF_TIMER4_CC1 location number i */
|
||||
#define AF_TIMER4_CC2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 7 : (i) == 3 ? 10 : (i) == 4 ? 8 : (i) == 5 ? 10 : (i) == 6 ? 8 : (i) == 7 ? 11 : -1) /**< Pin number for AF_TIMER4_CC2 location number i */
|
||||
#define AF_TIMER4_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CC3 location number i */
|
||||
#define AF_TIMER4_CDTI0_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_TIMER4_CDTI0 location number i */
|
||||
#define AF_TIMER4_CDTI1_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_TIMER4_CDTI1 location number i */
|
||||
#define AF_TIMER4_CDTI2_PIN(i) ((i) == 0 ? 3 : -1) /**< Pin number for AF_TIMER4_CDTI2 location number i */
|
||||
#define AF_TIMER4_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER4_CDTI3 location number i */
|
||||
#define AF_TIMER5_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 0 : (i) == 4 ? 8 : (i) == 5 ? 11 : (i) == 6 ? 14 : (i) == 7 ? 12 : -1) /**< Pin number for AF_TIMER5_CC0 location number i */
|
||||
#define AF_TIMER5_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 14 : (i) == 3 ? 1 : (i) == 4 ? 9 : (i) == 5 ? 12 : (i) == 6 ? 10 : (i) == 7 ? 13 : -1) /**< Pin number for AF_TIMER5_CC1 location number i */
|
||||
#define AF_TIMER5_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 12 : (i) == 2 ? 15 : (i) == 3 ? 2 : (i) == 4 ? 10 : (i) == 5 ? 13 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_TIMER5_CC2 location number i */
|
||||
#define AF_TIMER5_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CC3 location number i */
|
||||
#define AF_TIMER5_CDTI0_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI0 location number i */
|
||||
#define AF_TIMER5_CDTI1_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI1 location number i */
|
||||
#define AF_TIMER5_CDTI2_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI2 location number i */
|
||||
#define AF_TIMER5_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER5_CDTI3 location number i */
|
||||
#define AF_TIMER6_CC0_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 1 : (i) == 7 ? 4 : -1) /**< Pin number for AF_TIMER6_CC0 location number i */
|
||||
#define AF_TIMER6_CC1_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 13 : (i) == 3 ? 3 : (i) == 4 ? 9 : (i) == 5 ? 14 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Pin number for AF_TIMER6_CC1 location number i */
|
||||
#define AF_TIMER6_CC2_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 8 : (i) == 2 ? 14 : (i) == 3 ? 4 : (i) == 4 ? 10 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 6 : -1) /**< Pin number for AF_TIMER6_CC2 location number i */
|
||||
#define AF_TIMER6_CC3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CC3 location number i */
|
||||
#define AF_TIMER6_CDTI0_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 9 : (i) == 2 ? 4 : (i) == 3 ? 5 : -1) /**< Pin number for AF_TIMER6_CDTI0 location number i */
|
||||
#define AF_TIMER6_CDTI1_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 10 : (i) == 2 ? 5 : (i) == 3 ? 6 : -1) /**< Pin number for AF_TIMER6_CDTI1 location number i */
|
||||
#define AF_TIMER6_CDTI2_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 11 : (i) == 2 ? 6 : (i) == 3 ? 7 : -1) /**< Pin number for AF_TIMER6_CDTI2 location number i */
|
||||
#define AF_TIMER6_CDTI3_PIN(i) (-1) /**< Pin number for AF_TIMER6_CDTI3 location number i */
|
||||
#define AF_WTIMER0_CC0_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 15 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Pin number for AF_WTIMER0_CC0 location number i */
|
||||
#define AF_WTIMER0_CC1_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 4 : (i) == 7 ? 2 : -1) /**< Pin number for AF_WTIMER0_CC1 location number i */
|
||||
#define AF_WTIMER0_CC2_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 3 : -1) /**< Pin number for AF_WTIMER0_CC2 location number i */
|
||||
#define AF_WTIMER0_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CC3 location number i */
|
||||
#define AF_WTIMER0_CDTI0_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 11 : (i) == 4 ? 4 : -1) /**< Pin number for AF_WTIMER0_CDTI0 location number i */
|
||||
#define AF_WTIMER0_CDTI1_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 0 : (i) == 2 ? 13 : (i) == 3 ? 12 : (i) == 4 ? 5 : -1) /**< Pin number for AF_WTIMER0_CDTI1 location number i */
|
||||
#define AF_WTIMER0_CDTI2_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 6 : -1) /**< Pin number for AF_WTIMER0_CDTI2 location number i */
|
||||
#define AF_WTIMER0_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER0_CDTI3 location number i */
|
||||
#define AF_WTIMER1_CC0_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 3 : (i) == 5 ? 7 : (i) == 6 ? 8 : (i) == 7 ? 12 : -1) /**< Pin number for AF_WTIMER1_CC0 location number i */
|
||||
#define AF_WTIMER1_CC1_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : (i) == 6 ? 9 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER1_CC1 location number i */
|
||||
#define AF_WTIMER1_CC2_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 10 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER1_CC2 location number i */
|
||||
#define AF_WTIMER1_CC3_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 2 : (i) == 6 ? 11 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER1_CC3 location number i */
|
||||
#define AF_WTIMER1_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI0 location number i */
|
||||
#define AF_WTIMER1_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI1 location number i */
|
||||
#define AF_WTIMER1_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI2 location number i */
|
||||
#define AF_WTIMER1_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER1_CDTI3 location number i */
|
||||
#define AF_WTIMER2_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 12 : (i) == 2 ? 9 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 7 : -1) /**< Pin number for AF_WTIMER2_CC0 location number i */
|
||||
#define AF_WTIMER2_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 13 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 15 : (i) == 5 ? 4 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Pin number for AF_WTIMER2_CC1 location number i */
|
||||
#define AF_WTIMER2_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 14 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 0 : (i) == 5 ? 5 : (i) == 6 ? 6 : (i) == 7 ? 9 : -1) /**< Pin number for AF_WTIMER2_CC2 location number i */
|
||||
#define AF_WTIMER2_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CC3 location number i */
|
||||
#define AF_WTIMER2_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI0 location number i */
|
||||
#define AF_WTIMER2_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI1 location number i */
|
||||
#define AF_WTIMER2_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI2 location number i */
|
||||
#define AF_WTIMER2_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER2_CDTI3 location number i */
|
||||
#define AF_WTIMER3_CC0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 8 : (i) == 2 ? 11 : (i) == 3 ? 14 : (i) == 4 ? 3 : (i) == 5 ? 6 : (i) == 6 ? 6 : (i) == 7 ? 13 : -1) /**< Pin number for AF_WTIMER3_CC0 location number i */
|
||||
#define AF_WTIMER3_CC1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 9 : (i) == 2 ? 12 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 7 : (i) == 6 ? 4 : (i) == 7 ? 14 : -1) /**< Pin number for AF_WTIMER3_CC1 location number i */
|
||||
#define AF_WTIMER3_CC2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 10 : (i) == 2 ? 13 : (i) == 3 ? 11 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_WTIMER3_CC2 location number i */
|
||||
#define AF_WTIMER3_CC3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CC3 location number i */
|
||||
#define AF_WTIMER3_CDTI0_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI0 location number i */
|
||||
#define AF_WTIMER3_CDTI1_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI1 location number i */
|
||||
#define AF_WTIMER3_CDTI2_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI2 location number i */
|
||||
#define AF_WTIMER3_CDTI3_PIN(i) (-1) /**< Pin number for AF_WTIMER3_CDTI3 location number i */
|
||||
#define AF_USART0_TX_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 7 : (i) == 2 ? 11 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 0 : (i) == 6 ? 12 : -1) /**< Pin number for AF_USART0_TX location number i */
|
||||
#define AF_USART0_RX_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 1 : (i) == 6 ? 13 : -1) /**< Pin number for AF_USART0_RX location number i */
|
||||
#define AF_USART0_CLK_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 13 : (i) == 5 ? 12 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART0_CLK location number i */
|
||||
#define AF_USART0_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 14 : (i) == 5 ? 13 : (i) == 6 ? 15 : -1) /**< Pin number for AF_USART0_CS location number i */
|
||||
#define AF_USART0_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 11 : (i) == 6 ? 0 : -1) /**< Pin number for AF_USART0_CTS location number i */
|
||||
#define AF_USART0_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 5 : (i) == 5 ? 6 : (i) == 6 ? 1 : -1) /**< Pin number for AF_USART0_RTS location number i */
|
||||
#define AF_USART1_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 7 : (i) == 3 ? 6 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 14 : -1) /**< Pin number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 15 : (i) == 4 ? 3 : (i) == 5 ? 11 : (i) == 6 ? 5 : -1) /**< Pin number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 4 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 12 : (i) == 5 ? 13 : (i) == 6 ? 2 : -1) /**< Pin number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 7 : (i) == 4 ? 13 : (i) == 5 ? 14 : (i) == 6 ? 3 : -1) /**< Pin number for AF_USART1_RTS location number i */
|
||||
#define AF_USART2_TX_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 13 : (i) == 4 ? 6 : (i) == 5 ? 0 : -1) /**< Pin number for AF_USART2_TX location number i */
|
||||
#define AF_USART2_RX_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 14 : (i) == 4 ? 7 : (i) == 5 ? 1 : -1) /**< Pin number for AF_USART2_RX location number i */
|
||||
#define AF_USART2_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 9 : (i) == 3 ? 15 : (i) == 4 ? 8 : (i) == 5 ? 2 : -1) /**< Pin number for AF_USART2_CLK location number i */
|
||||
#define AF_USART2_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 6 : (i) == 2 ? 10 : (i) == 3 ? 11 : (i) == 4 ? 9 : (i) == 5 ? 5 : -1) /**< Pin number for AF_USART2_CS location number i */
|
||||
#define AF_USART2_CTS_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 12 : (i) == 2 ? 11 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 6 : -1) /**< Pin number for AF_USART2_CTS location number i */
|
||||
#define AF_USART2_RTS_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 12 : (i) == 3 ? 14 : (i) == 4 ? 13 : (i) == 5 ? 8 : -1) /**< Pin number for AF_USART2_RTS location number i */
|
||||
#define AF_USART3_TX_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 12 : -1) /**< Pin number for AF_USART3_TX location number i */
|
||||
#define AF_USART3_RX_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 13 : -1) /**< Pin number for AF_USART3_RX location number i */
|
||||
#define AF_USART3_CLK_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 7 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_USART3_CLK location number i */
|
||||
#define AF_USART3_CS_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 3 : (i) == 5 ? 15 : -1) /**< Pin number for AF_USART3_CS location number i */
|
||||
#define AF_USART3_CTS_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : (i) == 2 ? 6 : (i) == 3 ? 10 : (i) == 4 ? 4 : (i) == 5 ? 9 : -1) /**< Pin number for AF_USART3_CTS location number i */
|
||||
#define AF_USART3_RTS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 14 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 11 : -1) /**< Pin number for AF_USART3_RTS location number i */
|
||||
#define AF_USART4_TX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 9 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 4 : -1) /**< Pin number for AF_USART4_TX location number i */
|
||||
#define AF_USART4_RX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 10 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 5 : -1) /**< Pin number for AF_USART4_RX location number i */
|
||||
#define AF_USART4_CLK_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 2 : (i) == 3 ? 8 : (i) == 4 ? 6 : -1) /**< Pin number for AF_USART4_CLK location number i */
|
||||
#define AF_USART4_CS_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 3 : (i) == 3 ? 9 : (i) == 4 ? 7 : -1) /**< Pin number for AF_USART4_CS location number i */
|
||||
#define AF_USART4_CTS_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 13 : (i) == 2 ? 4 : (i) == 3 ? 10 : (i) == 4 ? 8 : -1) /**< Pin number for AF_USART4_CTS location number i */
|
||||
#define AF_USART4_RTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 5 : (i) == 3 ? 11 : (i) == 4 ? 9 : -1) /**< Pin number for AF_USART4_RTS location number i */
|
||||
#define AF_USART5_TX_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 6 : (i) == 2 ? 15 : (i) == 3 ? 10 : -1) /**< Pin number for AF_USART5_TX location number i */
|
||||
#define AF_USART5_RX_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 7 : (i) == 2 ? 1 : (i) == 3 ? 11 : -1) /**< Pin number for AF_USART5_RX location number i */
|
||||
#define AF_USART5_CLK_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 13 : (i) == 2 ? 13 : (i) == 3 ? 12 : -1) /**< Pin number for AF_USART5_CLK location number i */
|
||||
#define AF_USART5_CS_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 14 : (i) == 2 ? 12 : (i) == 3 ? 13 : -1) /**< Pin number for AF_USART5_CS location number i */
|
||||
#define AF_USART5_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 14 : -1) /**< Pin number for AF_USART5_CTS location number i */
|
||||
#define AF_USART5_RTS_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 15 : (i) == 2 ? 10 : (i) == 3 ? 15 : -1) /**< Pin number for AF_USART5_RTS location number i */
|
||||
#define AF_UART0_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 14 : (i) == 4 ? 4 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Pin number for AF_UART0_TX location number i */
|
||||
#define AF_UART0_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 15 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 4 : -1) /**< Pin number for AF_UART0_RX location number i */
|
||||
#define AF_UART0_CLK_PIN(i) (-1) /**< Pin number for AF_UART0_CLK location number i */
|
||||
#define AF_UART0_CS_PIN(i) (-1) /**< Pin number for AF_UART0_CS location number i */
|
||||
#define AF_UART0_CTS_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 13 : (i) == 4 ? 7 : (i) == 5 ? 5 : -1) /**< Pin number for AF_UART0_CTS location number i */
|
||||
#define AF_UART0_RTS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 12 : (i) == 4 ? 8 : (i) == 5 ? 6 : -1) /**< Pin number for AF_UART0_RTS location number i */
|
||||
#define AF_UART1_TX_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 10 : (i) == 2 ? 9 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 11 : -1) /**< Pin number for AF_UART1_TX location number i */
|
||||
#define AF_UART1_RX_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 11 : (i) == 2 ? 10 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 12 : -1) /**< Pin number for AF_UART1_RX location number i */
|
||||
#define AF_UART1_CLK_PIN(i) (-1) /**< Pin number for AF_UART1_CLK location number i */
|
||||
#define AF_UART1_CS_PIN(i) (-1) /**< Pin number for AF_UART1_CS location number i */
|
||||
#define AF_UART1_CTS_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 9 : (i) == 2 ? 11 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 13 : -1) /**< Pin number for AF_UART1_CTS location number i */
|
||||
#define AF_UART1_RTS_PIN(i) ((i) == 0 ? 15 : (i) == 1 ? 8 : (i) == 2 ? 12 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 14 : -1) /**< Pin number for AF_UART1_RTS location number i */
|
||||
#define AF_QSPI0_SCLK_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 14 : (i) == 2 ? 0 : -1) /**< Pin number for AF_QSPI0_SCLK location number i */
|
||||
#define AF_QSPI0_DQ0_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Pin number for AF_QSPI0_DQ0 location number i */
|
||||
#define AF_QSPI0_DQ1_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 3 : (i) == 2 ? 2 : -1) /**< Pin number for AF_QSPI0_DQ1 location number i */
|
||||
#define AF_QSPI0_DQ2_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 4 : (i) == 2 ? 3 : -1) /**< Pin number for AF_QSPI0_DQ2 location number i */
|
||||
#define AF_QSPI0_DQ3_PIN(i) ((i) == 0 ? 12 : (i) == 1 ? 5 : (i) == 2 ? 4 : -1) /**< Pin number for AF_QSPI0_DQ3 location number i */
|
||||
#define AF_QSPI0_DQ4_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 3 : (i) == 2 ? 5 : -1) /**< Pin number for AF_QSPI0_DQ4 location number i */
|
||||
#define AF_QSPI0_DQ5_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Pin number for AF_QSPI0_DQ5 location number i */
|
||||
#define AF_QSPI0_DQ6_PIN(i) ((i) == 0 ? 10 : (i) == 1 ? 5 : (i) == 2 ? 7 : -1) /**< Pin number for AF_QSPI0_DQ6 location number i */
|
||||
#define AF_QSPI0_DQ7_PIN(i) ((i) == 0 ? 11 : (i) == 1 ? 6 : (i) == 2 ? 8 : -1) /**< Pin number for AF_QSPI0_DQ7 location number i */
|
||||
#define AF_QSPI0_CS0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 0 : (i) == 2 ? 9 : -1) /**< Pin number for AF_QSPI0_CS0 location number i */
|
||||
#define AF_QSPI0_CS1_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 1 : (i) == 2 ? 10 : -1) /**< Pin number for AF_QSPI0_CS1 location number i */
|
||||
#define AF_QSPI0_DQS_PIN(i) ((i) == 0 ? 9 : (i) == 1 ? 15 : (i) == 2 ? 11 : -1) /**< Pin number for AF_QSPI0_DQS location number i */
|
||||
#define AF_LEUART0_TX_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 0 : (i) == 4 ? 2 : (i) == 5 ? 14 : -1) /**< Pin number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 14 : (i) == 2 ? 15 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 15 : -1) /**< Pin number for AF_LEUART0_RX location number i */
|
||||
#define AF_LEUART1_TX_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 0 : -1) /**< Pin number for AF_LEUART1_TX location number i */
|
||||
#define AF_LEUART1_RX_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 6 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Pin number for AF_LEUART1_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 12 : (i) == 5 ? 14 : (i) == 6 ? 8 : (i) == 7 ? 9 : -1) /**< Pin number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 9 : (i) == 7 ? 10 : -1) /**< Pin number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_LETIMER1_OUT0_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 11 : (i) == 2 ? 12 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 2 : -1) /**< Pin number for AF_LETIMER1_OUT0 location number i */
|
||||
#define AF_LETIMER1_OUT1_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 13 : (i) == 2 ? 14 : (i) == 3 ? 3 : (i) == 4 ? 6 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 3 : -1) /**< Pin number for AF_LETIMER1_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 5 : (i) == 7 ? 12 : -1) /**< Pin number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PIN(i) ((i) == 0 ? 14 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 7 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 11 : -1) /**< Pin number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_PCNT1_S0IN_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 15 : (i) == 3 ? 4 : (i) == 4 ? 7 : (i) == 5 ? 12 : (i) == 6 ? 11 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT1_S0IN location number i */
|
||||
#define AF_PCNT1_S1IN_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 13 : (i) == 6 ? 12 : (i) == 7 ? 15 : -1) /**< Pin number for AF_PCNT1_S1IN location number i */
|
||||
#define AF_PCNT2_S0IN_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 8 : (i) == 2 ? 13 : (i) == 3 ? 10 : (i) == 4 ? 12 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 14 : -1) /**< Pin number for AF_PCNT2_S0IN location number i */
|
||||
#define AF_PCNT2_S1IN_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 9 : (i) == 2 ? 14 : (i) == 3 ? 11 : (i) == 4 ? 13 : (i) == 5 ? 1 : (i) == 6 ? 15 : (i) == 7 ? 13 : -1) /**< Pin number for AF_PCNT2_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 14 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PIN(i) ((i) == 0 ? 1 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 15 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C0_SCL location number i */
|
||||
#define AF_I2C1_SDA_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 11 : (i) == 2 ? 0 : (i) == 3 ? 4 : (i) == 4 ? 11 : (i) == 5 ? 11 : (i) == 6 ? 13 : (i) == 7 ? 2 : -1) /**< Pin number for AF_I2C1_SDA location number i */
|
||||
#define AF_I2C1_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 12 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 12 : (i) == 6 ? 14 : (i) == 7 ? 3 : -1) /**< Pin number for AF_I2C1_SCL location number i */
|
||||
#define AF_I2C2_SDA_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 14 : (i) == 2 ? 10 : (i) == 3 ? 4 : (i) == 4 ? 13 : (i) == 5 ? 15 : (i) == 6 ? 12 : (i) == 7 ? 4 : -1) /**< Pin number for AF_I2C2_SDA location number i */
|
||||
#define AF_I2C2_SCL_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 15 : (i) == 2 ? 11 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 3 : (i) == 6 ? 13 : (i) == 7 ? 5 : -1) /**< Pin number for AF_I2C2_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PIN(i) ((i) == 0 ? 13 : (i) == 1 ? 2 : (i) == 2 ? 6 : (i) == 3 ? 11 : (i) == 4 ? 6 : (i) == 5 ? 0 : (i) == 6 ? 2 : (i) == 7 ? 3 : -1) /**< Pin number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 12 : (i) == 4 ? 14 : (i) == 5 ? 9 : (i) == 6 ? 10 : (i) == 7 ? 5 : -1) /**< Pin number for AF_ACMP1_OUT location number i */
|
||||
#define AF_ACMP2_OUT_PIN(i) ((i) == 0 ? 8 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 0 : (i) == 4 ? 1 : (i) == 5 ? 2 : -1) /**< Pin number for AF_ACMP2_OUT location number i */
|
||||
#define AF_ACMP3_OUT_PIN(i) ((i) == 0 ? 0 : (i) == 1 ? 15 : (i) == 2 ? 14 : (i) == 3 ? 13 : (i) == 4 ? 4 : (i) == 5 ? 5 : -1) /**< Pin number for AF_ACMP3_OUT location number i */
|
||||
#define AF_USB_VBUSEN_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_USB_VBUSEN location number i */
|
||||
#define AF_DBG_TDI_PIN(i) ((i) == 0 ? 5 : -1) /**< Pin number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PIN(i) ((i) == 0 ? 2 : -1) /**< Pin number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PIN(i) ((i) == 0 ? 2 : (i) == 1 ? 15 : (i) == 2 ? 1 : (i) == 3 ? 2 : -1) /**< Pin number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PIN(i) ((i) == 0 ? 1 : -1) /**< Pin number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PIN(i) ((i) == 0 ? 0 : -1) /**< Pin number for AF_DBG_SWCLKTCK location number i */
|
||||
#define AF_ETM_TCLK_PIN(i) ((i) == 0 ? 7 : (i) == 1 ? 8 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 11 : (i) == 5 ? 15 : -1) /**< Pin number for AF_ETM_TCLK location number i */
|
||||
#define AF_ETM_TD0_PIN(i) ((i) == 0 ? 6 : (i) == 1 ? 9 : (i) == 2 ? 7 : (i) == 3 ? 2 : (i) == 4 ? 12 : (i) == 5 ? 14 : -1) /**< Pin number for AF_ETM_TD0 location number i */
|
||||
#define AF_ETM_TD1_PIN(i) ((i) == 0 ? 3 : (i) == 1 ? 13 : (i) == 2 ? 3 : (i) == 3 ? 3 : (i) == 4 ? 13 : (i) == 5 ? 13 : -1) /**< Pin number for AF_ETM_TD1 location number i */
|
||||
#define AF_ETM_TD2_PIN(i) ((i) == 0 ? 4 : (i) == 1 ? 15 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 14 : (i) == 5 ? 12 : -1) /**< Pin number for AF_ETM_TD2 location number i */
|
||||
#define AF_ETM_TD3_PIN(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 15 : (i) == 5 ? 11 : -1) /**< Pin number for AF_ETM_TD3 location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_AF_Pins */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h
vendored
Normal file
403
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_af_ports.h
vendored
Normal file
@ -0,0 +1,403 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_AF_PORTS register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_Alternate_Function Alternate Function
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_AF_Ports Alternate Function Ports
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
#define AF_CMU_CLK0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 0 : -1) /**< Port number for AF_CMU_CLK0 location number i */
|
||||
#define AF_CMU_CLK1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : -1) /**< Port number for AF_CMU_CLK1 location number i */
|
||||
#define AF_CMU_CLK2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 0 : (i) == 5 ? 3 : -1) /**< Port number for AF_CMU_CLK2 location number i */
|
||||
#define AF_CMU_CLKI0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 4 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 1 : -1) /**< Port number for AF_CMU_CLKI0 location number i */
|
||||
#define AF_CMU_DIGEXTCLK_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_DIGEXTCLK location number i */
|
||||
#define AF_CMU_IOPOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IOPOVR location number i */
|
||||
#define AF_CMU_IONOVR_PORT(i) ((i) == 0 ? 1 : -1) /**< Port number for AF_CMU_IONOVR location number i */
|
||||
#define AF_LESENSE_CH0_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH0 location number i */
|
||||
#define AF_LESENSE_CH1_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH1 location number i */
|
||||
#define AF_LESENSE_CH2_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH2 location number i */
|
||||
#define AF_LESENSE_CH3_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH3 location number i */
|
||||
#define AF_LESENSE_CH4_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH4 location number i */
|
||||
#define AF_LESENSE_CH5_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH5 location number i */
|
||||
#define AF_LESENSE_CH6_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH6 location number i */
|
||||
#define AF_LESENSE_CH7_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH7 location number i */
|
||||
#define AF_LESENSE_CH8_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH8 location number i */
|
||||
#define AF_LESENSE_CH9_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH9 location number i */
|
||||
#define AF_LESENSE_CH10_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH10 location number i */
|
||||
#define AF_LESENSE_CH11_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH11 location number i */
|
||||
#define AF_LESENSE_CH12_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH12 location number i */
|
||||
#define AF_LESENSE_CH13_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH13 location number i */
|
||||
#define AF_LESENSE_CH14_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH14 location number i */
|
||||
#define AF_LESENSE_CH15_PORT(i) ((i) == 0 ? 2 : -1) /**< Port number for AF_LESENSE_CH15 location number i */
|
||||
#define AF_LESENSE_ALTEX0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX0 location number i */
|
||||
#define AF_LESENSE_ALTEX1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_LESENSE_ALTEX1 location number i */
|
||||
#define AF_LESENSE_ALTEX2_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX2 location number i */
|
||||
#define AF_LESENSE_ALTEX3_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX3 location number i */
|
||||
#define AF_LESENSE_ALTEX4_PORT(i) ((i) == 0 ? 0 : -1) /**< Port number for AF_LESENSE_ALTEX4 location number i */
|
||||
#define AF_LESENSE_ALTEX5_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX5 location number i */
|
||||
#define AF_LESENSE_ALTEX6_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX6 location number i */
|
||||
#define AF_LESENSE_ALTEX7_PORT(i) ((i) == 0 ? 4 : -1) /**< Port number for AF_LESENSE_ALTEX7 location number i */
|
||||
#define AF_EBI_AD00_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD00 location number i */
|
||||
#define AF_EBI_AD01_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD01 location number i */
|
||||
#define AF_EBI_AD02_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD02 location number i */
|
||||
#define AF_EBI_AD03_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD03 location number i */
|
||||
#define AF_EBI_AD04_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD04 location number i */
|
||||
#define AF_EBI_AD05_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD05 location number i */
|
||||
#define AF_EBI_AD06_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD06 location number i */
|
||||
#define AF_EBI_AD07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD07 location number i */
|
||||
#define AF_EBI_AD08_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD08 location number i */
|
||||
#define AF_EBI_AD09_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD09 location number i */
|
||||
#define AF_EBI_AD10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD10 location number i */
|
||||
#define AF_EBI_AD11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD11 location number i */
|
||||
#define AF_EBI_AD12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD12 location number i */
|
||||
#define AF_EBI_AD13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD13 location number i */
|
||||
#define AF_EBI_AD14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD14 location number i */
|
||||
#define AF_EBI_AD15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_EBI_AD15 location number i */
|
||||
#define AF_EBI_CS0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS0 location number i */
|
||||
#define AF_EBI_CS1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS1 location number i */
|
||||
#define AF_EBI_CS2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS2 location number i */
|
||||
#define AF_EBI_CS3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 4 : -1) /**< Port number for AF_EBI_CS3 location number i */
|
||||
#define AF_EBI_ARDY_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_ARDY location number i */
|
||||
#define AF_EBI_ALE_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 2 : -1) /**< Port number for AF_EBI_ALE location number i */
|
||||
#define AF_EBI_WEn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_WEn location number i */
|
||||
#define AF_EBI_REn_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_REn location number i */
|
||||
#define AF_EBI_BL0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL0 location number i */
|
||||
#define AF_EBI_BL1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_BL1 location number i */
|
||||
#define AF_EBI_NANDWEn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDWEn location number i */
|
||||
#define AF_EBI_NANDREn_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : -1) /**< Port number for AF_EBI_NANDREn location number i */
|
||||
#define AF_EBI_A00_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A00 location number i */
|
||||
#define AF_EBI_A01_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A01 location number i */
|
||||
#define AF_EBI_A02_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A02 location number i */
|
||||
#define AF_EBI_A03_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A03 location number i */
|
||||
#define AF_EBI_A04_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A04 location number i */
|
||||
#define AF_EBI_A05_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A05 location number i */
|
||||
#define AF_EBI_A06_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A06 location number i */
|
||||
#define AF_EBI_A07_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A07 location number i */
|
||||
#define AF_EBI_A08_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_A08 location number i */
|
||||
#define AF_EBI_A09_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A09 location number i */
|
||||
#define AF_EBI_A10_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A10 location number i */
|
||||
#define AF_EBI_A11_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A11 location number i */
|
||||
#define AF_EBI_A12_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 1 : -1) /**< Port number for AF_EBI_A12 location number i */
|
||||
#define AF_EBI_A13_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A13 location number i */
|
||||
#define AF_EBI_A14_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A14 location number i */
|
||||
#define AF_EBI_A15_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 8 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A15 location number i */
|
||||
#define AF_EBI_A16_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A16 location number i */
|
||||
#define AF_EBI_A17_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A17 location number i */
|
||||
#define AF_EBI_A18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A18 location number i */
|
||||
#define AF_EBI_A19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A19 location number i */
|
||||
#define AF_EBI_A20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 3 : -1) /**< Port number for AF_EBI_A20 location number i */
|
||||
#define AF_EBI_A21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A21 location number i */
|
||||
#define AF_EBI_A22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A22 location number i */
|
||||
#define AF_EBI_A23_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 2 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A23 location number i */
|
||||
#define AF_EBI_A24_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A24 location number i */
|
||||
#define AF_EBI_A25_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 4 : -1) /**< Port number for AF_EBI_A25 location number i */
|
||||
#define AF_EBI_A26_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A26 location number i */
|
||||
#define AF_EBI_A27_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 2 : -1) /**< Port number for AF_EBI_A27 location number i */
|
||||
#define AF_EBI_CSTFT_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_CSTFT location number i */
|
||||
#define AF_EBI_DCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DCLK location number i */
|
||||
#define AF_EBI_DTEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_DTEN location number i */
|
||||
#define AF_EBI_VSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_VSNC location number i */
|
||||
#define AF_EBI_HSNC_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 7 : (i) == 3 ? 0 : -1) /**< Port number for AF_EBI_HSNC location number i */
|
||||
#define AF_ETH_MIITXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXCLK location number i */
|
||||
#define AF_ETH_MIITXD3_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD3 location number i */
|
||||
#define AF_ETH_MIITXD2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD2 location number i */
|
||||
#define AF_ETH_MIITXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD1 location number i */
|
||||
#define AF_ETH_MIITXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXD0 location number i */
|
||||
#define AF_ETH_MIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXEN location number i */
|
||||
#define AF_ETH_MIITXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : -1) /**< Port number for AF_ETH_MIITXER location number i */
|
||||
#define AF_ETH_MIIRXCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXCLK location number i */
|
||||
#define AF_ETH_MIIRXD3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD3 location number i */
|
||||
#define AF_ETH_MIIRXD2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD2 location number i */
|
||||
#define AF_ETH_MIIRXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 3 : -1) /**< Port number for AF_ETH_MIIRXD1 location number i */
|
||||
#define AF_ETH_MIIRXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXD0 location number i */
|
||||
#define AF_ETH_MIIRXDV_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXDV location number i */
|
||||
#define AF_ETH_MIIRXER_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 5 : -1) /**< Port number for AF_ETH_MIIRXER location number i */
|
||||
#define AF_ETH_MIICRS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICRS location number i */
|
||||
#define AF_ETH_MIICOL_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 6 : (i) == 2 ? 1 : -1) /**< Port number for AF_ETH_MIICOL location number i */
|
||||
#define AF_ETH_MDIO_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDIO location number i */
|
||||
#define AF_ETH_MDC_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 0 : -1) /**< Port number for AF_ETH_MDC location number i */
|
||||
#define AF_ETH_TSUEXTCLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUEXTCLK location number i */
|
||||
#define AF_ETH_TSUTMRTOG_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_ETH_TSUTMRTOG location number i */
|
||||
#define AF_ETH_RMIITXD1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD1 location number i */
|
||||
#define AF_ETH_RMIITXD0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXD0 location number i */
|
||||
#define AF_ETH_RMIITXEN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIITXEN location number i */
|
||||
#define AF_ETH_RMIIRXD1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : -1) /**< Port number for AF_ETH_RMIIRXD1 location number i */
|
||||
#define AF_ETH_RMIIRXD0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXD0 location number i */
|
||||
#define AF_ETH_RMIIREFCLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIREFCLK location number i */
|
||||
#define AF_ETH_RMIICRSDV_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIICRSDV location number i */
|
||||
#define AF_ETH_RMIIRXER_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : -1) /**< Port number for AF_ETH_RMIIRXER location number i */
|
||||
#define AF_SDIO_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CLK location number i */
|
||||
#define AF_SDIO_CMD_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : -1) /**< Port number for AF_SDIO_CMD location number i */
|
||||
#define AF_SDIO_DAT0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT0 location number i */
|
||||
#define AF_SDIO_DAT1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT1 location number i */
|
||||
#define AF_SDIO_DAT2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT2 location number i */
|
||||
#define AF_SDIO_DAT3_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT3 location number i */
|
||||
#define AF_SDIO_DAT4_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT4 location number i */
|
||||
#define AF_SDIO_DAT5_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : -1) /**< Port number for AF_SDIO_DAT5 location number i */
|
||||
#define AF_SDIO_DAT6_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT6 location number i */
|
||||
#define AF_SDIO_DAT7_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : -1) /**< Port number for AF_SDIO_DAT7 location number i */
|
||||
#define AF_SDIO_CD_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_CD location number i */
|
||||
#define AF_SDIO_WP_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 1 : (i) == 3 ? 1 : -1) /**< Port number for AF_SDIO_WP location number i */
|
||||
#define AF_PRS_CH0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 5 : -1) /**< Port number for AF_PRS_CH0 location number i */
|
||||
#define AF_PRS_CH1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH1 location number i */
|
||||
#define AF_PRS_CH2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 4 : (i) == 3 ? 4 : -1) /**< Port number for AF_PRS_CH2 location number i */
|
||||
#define AF_PRS_CH3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 0 : -1) /**< Port number for AF_PRS_CH3 location number i */
|
||||
#define AF_PRS_CH4_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH4 location number i */
|
||||
#define AF_PRS_CH5_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH5 location number i */
|
||||
#define AF_PRS_CH6_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH6 location number i */
|
||||
#define AF_PRS_CH7_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH7 location number i */
|
||||
#define AF_PRS_CH8_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH8 location number i */
|
||||
#define AF_PRS_CH9_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH9 location number i */
|
||||
#define AF_PRS_CH10_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH10 location number i */
|
||||
#define AF_PRS_CH11_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH11 location number i */
|
||||
#define AF_PRS_CH12_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : -1) /**< Port number for AF_PRS_CH12 location number i */
|
||||
#define AF_PRS_CH13_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH13 location number i */
|
||||
#define AF_PRS_CH14_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH14 location number i */
|
||||
#define AF_PRS_CH15_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH15 location number i */
|
||||
#define AF_PRS_CH16_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH16 location number i */
|
||||
#define AF_PRS_CH17_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH17 location number i */
|
||||
#define AF_PRS_CH18_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH18 location number i */
|
||||
#define AF_PRS_CH19_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 2 : -1) /**< Port number for AF_PRS_CH19 location number i */
|
||||
#define AF_PRS_CH20_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 4 : -1) /**< Port number for AF_PRS_CH20 location number i */
|
||||
#define AF_PRS_CH21_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 2 : (i) == 2 ? 1 : -1) /**< Port number for AF_PRS_CH21 location number i */
|
||||
#define AF_PRS_CH22_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH22 location number i */
|
||||
#define AF_PRS_CH23_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 4 : (i) == 2 ? 5 : -1) /**< Port number for AF_PRS_CH23 location number i */
|
||||
#define AF_CAN0_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_RX location number i */
|
||||
#define AF_CAN0_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN0_TX location number i */
|
||||
#define AF_CAN1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_RX location number i */
|
||||
#define AF_CAN1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 6 : (i) == 7 ? 8 : -1) /**< Port number for AF_CAN1_TX location number i */
|
||||
#define AF_TIMER0_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC0 location number i */
|
||||
#define AF_TIMER0_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC1 location number i */
|
||||
#define AF_TIMER0_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 5 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 0 : -1) /**< Port number for AF_TIMER0_CC2 location number i */
|
||||
#define AF_TIMER0_CC3_PORT(i) (-1) /**< Port number for AF_TIMER0_CC3 location number i */
|
||||
#define AF_TIMER0_CDTI0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI0 location number i */
|
||||
#define AF_TIMER0_CDTI1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI1 location number i */
|
||||
#define AF_TIMER0_CDTI2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 1 : -1) /**< Port number for AF_TIMER0_CDTI2 location number i */
|
||||
#define AF_TIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER0_CDTI3 location number i */
|
||||
#define AF_TIMER1_CC0_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC0 location number i */
|
||||
#define AF_TIMER1_CC1_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 3 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC1 location number i */
|
||||
#define AF_TIMER1_CC2_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC2 location number i */
|
||||
#define AF_TIMER1_CC3_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 8 : -1) /**< Port number for AF_TIMER1_CC3 location number i */
|
||||
#define AF_TIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI0 location number i */
|
||||
#define AF_TIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI1 location number i */
|
||||
#define AF_TIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI2 location number i */
|
||||
#define AF_TIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER1_CDTI3 location number i */
|
||||
#define AF_TIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC0 location number i */
|
||||
#define AF_TIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC1 location number i */
|
||||
#define AF_TIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_TIMER2_CC2 location number i */
|
||||
#define AF_TIMER2_CC3_PORT(i) (-1) /**< Port number for AF_TIMER2_CC3 location number i */
|
||||
#define AF_TIMER2_CDTI0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI0 location number i */
|
||||
#define AF_TIMER2_CDTI1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI1 location number i */
|
||||
#define AF_TIMER2_CDTI2_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 4 : (i) == 3 ? 6 : -1) /**< Port number for AF_TIMER2_CDTI2 location number i */
|
||||
#define AF_TIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER2_CDTI3 location number i */
|
||||
#define AF_TIMER3_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 0 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER3_CC0 location number i */
|
||||
#define AF_TIMER3_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC1 location number i */
|
||||
#define AF_TIMER3_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 4 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 3 : (i) == 7 ? 1 : -1) /**< Port number for AF_TIMER3_CC2 location number i */
|
||||
#define AF_TIMER3_CC3_PORT(i) (-1) /**< Port number for AF_TIMER3_CC3 location number i */
|
||||
#define AF_TIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI0 location number i */
|
||||
#define AF_TIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI1 location number i */
|
||||
#define AF_TIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI2 location number i */
|
||||
#define AF_TIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER3_CDTI3 location number i */
|
||||
#define AF_TIMER4_CC0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 5 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC0 location number i */
|
||||
#define AF_TIMER4_CC1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC1 location number i */
|
||||
#define AF_TIMER4_CC2_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 5 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 5 : (i) == 5 ? 3 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_TIMER4_CC2 location number i */
|
||||
#define AF_TIMER4_CC3_PORT(i) (-1) /**< Port number for AF_TIMER4_CC3 location number i */
|
||||
#define AF_TIMER4_CDTI0_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI0 location number i */
|
||||
#define AF_TIMER4_CDTI1_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI1 location number i */
|
||||
#define AF_TIMER4_CDTI2_PORT(i) ((i) == 0 ? 3 : -1) /**< Port number for AF_TIMER4_CDTI2 location number i */
|
||||
#define AF_TIMER4_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER4_CDTI3 location number i */
|
||||
#define AF_TIMER5_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 2 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC0 location number i */
|
||||
#define AF_TIMER5_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC1 location number i */
|
||||
#define AF_TIMER5_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 7 : (i) == 2 ? 7 : (i) == 3 ? 8 : (i) == 4 ? 2 : (i) == 5 ? 2 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_TIMER5_CC2 location number i */
|
||||
#define AF_TIMER5_CC3_PORT(i) (-1) /**< Port number for AF_TIMER5_CC3 location number i */
|
||||
#define AF_TIMER5_CDTI0_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI0 location number i */
|
||||
#define AF_TIMER5_CDTI1_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI1 location number i */
|
||||
#define AF_TIMER5_CDTI2_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI2 location number i */
|
||||
#define AF_TIMER5_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER5_CDTI3 location number i */
|
||||
#define AF_TIMER6_CC0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC0 location number i */
|
||||
#define AF_TIMER6_CC1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 1 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC1 location number i */
|
||||
#define AF_TIMER6_CC2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 6 : (i) == 3 ? 7 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 3 : (i) == 7 ? 3 : -1) /**< Port number for AF_TIMER6_CC2 location number i */
|
||||
#define AF_TIMER6_CC3_PORT(i) (-1) /**< Port number for AF_TIMER6_CC3 location number i */
|
||||
#define AF_TIMER6_CDTI0_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI0 location number i */
|
||||
#define AF_TIMER6_CDTI1_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI1 location number i */
|
||||
#define AF_TIMER6_CDTI2_PORT(i) ((i) == 0 ? 6 : (i) == 1 ? 6 : (i) == 2 ? 4 : (i) == 3 ? 7 : -1) /**< Port number for AF_TIMER6_CDTI2 location number i */
|
||||
#define AF_TIMER6_CDTI3_PORT(i) (-1) /**< Port number for AF_TIMER6_CDTI3 location number i */
|
||||
#define AF_WTIMER0_CC0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC0 location number i */
|
||||
#define AF_WTIMER0_CC1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC1 location number i */
|
||||
#define AF_WTIMER0_CC2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 6 : (i) == 3 ? 6 : (i) == 4 ? 5 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 2 : -1) /**< Port number for AF_WTIMER0_CC2 location number i */
|
||||
#define AF_WTIMER0_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CC3 location number i */
|
||||
#define AF_WTIMER0_CDTI0_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 3 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI0 location number i */
|
||||
#define AF_WTIMER0_CDTI1_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI1 location number i */
|
||||
#define AF_WTIMER0_CDTI2_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 6 : (i) == 2 ? 0 : (i) == 3 ? 6 : (i) == 4 ? 3 : -1) /**< Port number for AF_WTIMER0_CDTI2 location number i */
|
||||
#define AF_WTIMER0_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER0_CDTI3 location number i */
|
||||
#define AF_WTIMER1_CC0_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 4 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC0 location number i */
|
||||
#define AF_WTIMER1_CC1_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC1 location number i */
|
||||
#define AF_WTIMER1_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC2 location number i */
|
||||
#define AF_WTIMER1_CC3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER1_CC3 location number i */
|
||||
#define AF_WTIMER1_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI0 location number i */
|
||||
#define AF_WTIMER1_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI1 location number i */
|
||||
#define AF_WTIMER1_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI2 location number i */
|
||||
#define AF_WTIMER1_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER1_CDTI3 location number i */
|
||||
#define AF_WTIMER2_CC0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 1 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC0 location number i */
|
||||
#define AF_WTIMER2_CC1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC1 location number i */
|
||||
#define AF_WTIMER2_CC2_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 7 : (i) == 5 ? 3 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_WTIMER2_CC2 location number i */
|
||||
#define AF_WTIMER2_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CC3 location number i */
|
||||
#define AF_WTIMER2_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI0 location number i */
|
||||
#define AF_WTIMER2_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI1 location number i */
|
||||
#define AF_WTIMER2_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI2 location number i */
|
||||
#define AF_WTIMER2_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER2_CDTI3 location number i */
|
||||
#define AF_WTIMER3_CC0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 1 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC0 location number i */
|
||||
#define AF_WTIMER3_CC1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 8 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC1 location number i */
|
||||
#define AF_WTIMER3_CC2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 5 : (i) == 4 ? 8 : (i) == 5 ? 5 : (i) == 6 ? 5 : (i) == 7 ? 5 : -1) /**< Port number for AF_WTIMER3_CC2 location number i */
|
||||
#define AF_WTIMER3_CC3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CC3 location number i */
|
||||
#define AF_WTIMER3_CDTI0_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI0 location number i */
|
||||
#define AF_WTIMER3_CDTI1_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI1 location number i */
|
||||
#define AF_WTIMER3_CDTI2_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI2 location number i */
|
||||
#define AF_WTIMER3_CDTI3_PORT(i) (-1) /**< Port number for AF_WTIMER3_CDTI3 location number i */
|
||||
#define AF_USART0_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_TX location number i */
|
||||
#define AF_USART0_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 4 : (i) == 4 ? 1 : (i) == 5 ? 2 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_RX location number i */
|
||||
#define AF_USART0_CLK_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CLK location number i */
|
||||
#define AF_USART0_CS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 0 : (i) == 6 ? 6 : -1) /**< Port number for AF_USART0_CS location number i */
|
||||
#define AF_USART0_CTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_CTS location number i */
|
||||
#define AF_USART0_RTS_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART0_RTS location number i */
|
||||
#define AF_USART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_TX location number i */
|
||||
#define AF_USART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 0 : (i) == 6 ? 0 : -1) /**< Port number for AF_USART1_RX location number i */
|
||||
#define AF_USART1_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 4 : -1) /**< Port number for AF_USART1_CLK location number i */
|
||||
#define AF_USART1_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 4 : (i) == 6 ? 1 : -1) /**< Port number for AF_USART1_CS location number i */
|
||||
#define AF_USART1_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_CTS location number i */
|
||||
#define AF_USART1_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 1 : (i) == 6 ? 7 : -1) /**< Port number for AF_USART1_RTS location number i */
|
||||
#define AF_USART2_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_TX location number i */
|
||||
#define AF_USART2_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_RX location number i */
|
||||
#define AF_USART2_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 0 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CLK location number i */
|
||||
#define AF_USART2_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 5 : (i) == 5 ? 5 : -1) /**< Port number for AF_USART2_CS location number i */
|
||||
#define AF_USART2_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 1 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_CTS location number i */
|
||||
#define AF_USART2_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 3 : -1) /**< Port number for AF_USART2_RTS location number i */
|
||||
#define AF_USART3_TX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_TX location number i */
|
||||
#define AF_USART3_RX_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_RX location number i */
|
||||
#define AF_USART3_CLK_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CLK location number i */
|
||||
#define AF_USART3_CS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 8 : -1) /**< Port number for AF_USART3_CS location number i */
|
||||
#define AF_USART3_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 6 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_CTS location number i */
|
||||
#define AF_USART3_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 2 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 6 : (i) == 5 ? 6 : -1) /**< Port number for AF_USART3_RTS location number i */
|
||||
#define AF_USART4_TX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_TX location number i */
|
||||
#define AF_USART4_RX_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RX location number i */
|
||||
#define AF_USART4_CLK_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CLK location number i */
|
||||
#define AF_USART4_CS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CS location number i */
|
||||
#define AF_USART4_CTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_CTS location number i */
|
||||
#define AF_USART4_RTS_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 8 : (i) == 3 ? 8 : (i) == 4 ? 7 : -1) /**< Port number for AF_USART4_RTS location number i */
|
||||
#define AF_USART5_TX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_TX location number i */
|
||||
#define AF_USART5_RX_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 0 : (i) == 2 ? 1 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RX location number i */
|
||||
#define AF_USART5_CLK_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CLK location number i */
|
||||
#define AF_USART5_CS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CS location number i */
|
||||
#define AF_USART5_CTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 3 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_CTS location number i */
|
||||
#define AF_USART5_RTS_PORT(i) ((i) == 0 ? 1 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 7 : -1) /**< Port number for AF_USART5_RTS location number i */
|
||||
#define AF_UART0_TX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 3 : -1) /**< Port number for AF_UART0_TX location number i */
|
||||
#define AF_UART0_RX_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : -1) /**< Port number for AF_UART0_RX location number i */
|
||||
#define AF_UART0_CLK_PORT(i) (-1) /**< Port number for AF_UART0_CLK location number i */
|
||||
#define AF_UART0_CS_PORT(i) (-1) /**< Port number for AF_UART0_CS location number i */
|
||||
#define AF_UART0_CTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_CTS location number i */
|
||||
#define AF_UART0_RTS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 3 : -1) /**< Port number for AF_UART0_RTS location number i */
|
||||
#define AF_UART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_TX location number i */
|
||||
#define AF_UART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 4 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RX location number i */
|
||||
#define AF_UART1_CLK_PORT(i) (-1) /**< Port number for AF_UART1_CLK location number i */
|
||||
#define AF_UART1_CS_PORT(i) (-1) /**< Port number for AF_UART1_CS location number i */
|
||||
#define AF_UART1_CTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_CTS location number i */
|
||||
#define AF_UART1_RTS_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 5 : (i) == 2 ? 1 : (i) == 3 ? 4 : (i) == 4 ? 2 : (i) == 5 ? 7 : -1) /**< Port number for AF_UART1_RTS location number i */
|
||||
#define AF_QSPI0_SCLK_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_SCLK location number i */
|
||||
#define AF_QSPI0_DQ0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ0 location number i */
|
||||
#define AF_QSPI0_DQ1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ1 location number i */
|
||||
#define AF_QSPI0_DQ2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ2 location number i */
|
||||
#define AF_QSPI0_DQ3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ3 location number i */
|
||||
#define AF_QSPI0_DQ4_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ4 location number i */
|
||||
#define AF_QSPI0_DQ5_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ5 location number i */
|
||||
#define AF_QSPI0_DQ6_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ6 location number i */
|
||||
#define AF_QSPI0_DQ7_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 1 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQ7 location number i */
|
||||
#define AF_QSPI0_CS0_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS0 location number i */
|
||||
#define AF_QSPI0_CS1_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 0 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_CS1 location number i */
|
||||
#define AF_QSPI0_DQS_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 6 : -1) /**< Port number for AF_QSPI0_DQS location number i */
|
||||
#define AF_LEUART0_TX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_TX location number i */
|
||||
#define AF_LEUART0_RX_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 5 : (i) == 4 ? 0 : (i) == 5 ? 2 : -1) /**< Port number for AF_LEUART0_RX location number i */
|
||||
#define AF_LEUART1_TX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_TX location number i */
|
||||
#define AF_LEUART1_RX_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 0 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 1 : (i) == 5 ? 7 : -1) /**< Port number for AF_LEUART1_RX location number i */
|
||||
#define AF_LETIMER0_OUT0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT0 location number i */
|
||||
#define AF_LETIMER0_OUT1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 5 : (i) == 3 ? 2 : (i) == 4 ? 4 : (i) == 5 ? 2 : (i) == 6 ? 0 : (i) == 7 ? 1 : -1) /**< Port number for AF_LETIMER0_OUT1 location number i */
|
||||
#define AF_LETIMER1_OUT0_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT0 location number i */
|
||||
#define AF_LETIMER1_OUT1_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 0 : (i) == 2 ? 0 : (i) == 3 ? 2 : (i) == 4 ? 1 : (i) == 5 ? 1 : (i) == 6 ? 6 : (i) == 7 ? 6 : -1) /**< Port number for AF_LETIMER1_OUT1 location number i */
|
||||
#define AF_PCNT0_S0IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S0IN location number i */
|
||||
#define AF_PCNT0_S1IN_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 4 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_PCNT0_S1IN location number i */
|
||||
#define AF_PCNT1_S0IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S0IN location number i */
|
||||
#define AF_PCNT1_S1IN_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 1 : (i) == 2 ? 1 : (i) == 3 ? 2 : (i) == 4 ? 0 : (i) == 5 ? 0 : (i) == 6 ? 1 : (i) == 7 ? 6 : -1) /**< Port number for AF_PCNT1_S1IN location number i */
|
||||
#define AF_PCNT2_S0IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 8 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S0IN location number i */
|
||||
#define AF_PCNT2_S1IN_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 1 : (i) == 3 ? 5 : (i) == 4 ? 2 : (i) == 5 ? 8 : (i) == 6 ? 7 : (i) == 7 ? 7 : -1) /**< Port number for AF_PCNT2_S1IN location number i */
|
||||
#define AF_I2C0_SDA_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SDA location number i */
|
||||
#define AF_I2C0_SCL_PORT(i) ((i) == 0 ? 0 : (i) == 1 ? 3 : (i) == 2 ? 2 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 5 : (i) == 6 ? 4 : (i) == 7 ? 4 : -1) /**< Port number for AF_I2C0_SCL location number i */
|
||||
#define AF_I2C1_SDA_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 2 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SDA location number i */
|
||||
#define AF_I2C1_SCL_PORT(i) ((i) == 0 ? 2 : (i) == 1 ? 1 : (i) == 2 ? 4 : (i) == 3 ? 3 : (i) == 4 ? 5 : (i) == 5 ? 7 : (i) == 6 ? 7 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C1_SCL location number i */
|
||||
#define AF_I2C2_SDA_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SDA location number i */
|
||||
#define AF_I2C2_SCL_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 5 : (i) == 3 ? 5 : (i) == 4 ? 5 : (i) == 5 ? 5 : (i) == 6 ? 2 : (i) == 7 ? 8 : -1) /**< Port number for AF_I2C2_SCL location number i */
|
||||
#define AF_ACMP0_OUT_PORT(i) ((i) == 0 ? 4 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 1 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 1 : -1) /**< Port number for AF_ACMP0_OUT location number i */
|
||||
#define AF_ACMP1_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 4 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 0 : (i) == 5 ? 1 : (i) == 6 ? 1 : (i) == 7 ? 0 : -1) /**< Port number for AF_ACMP1_OUT location number i */
|
||||
#define AF_ACMP2_OUT_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 4 : (i) == 2 ? 4 : (i) == 3 ? 8 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP2_OUT location number i */
|
||||
#define AF_ACMP3_OUT_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 2 : (i) == 3 ? 2 : (i) == 4 ? 8 : (i) == 5 ? 8 : -1) /**< Port number for AF_ACMP3_OUT location number i */
|
||||
#define AF_USB_VBUSEN_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_USB_VBUSEN location number i */
|
||||
#define AF_DBG_TDI_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDI location number i */
|
||||
#define AF_DBG_TDO_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_TDO location number i */
|
||||
#define AF_DBG_SWV_PORT(i) ((i) == 0 ? 5 : (i) == 1 ? 2 : (i) == 2 ? 3 : (i) == 3 ? 3 : -1) /**< Port number for AF_DBG_SWV location number i */
|
||||
#define AF_DBG_SWDIOTMS_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWDIOTMS location number i */
|
||||
#define AF_DBG_SWCLKTCK_PORT(i) ((i) == 0 ? 5 : -1) /**< Port number for AF_DBG_SWCLKTCK location number i */
|
||||
#define AF_ETM_TCLK_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TCLK location number i */
|
||||
#define AF_ETM_TD0_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 2 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD0 location number i */
|
||||
#define AF_ETM_TD1_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 3 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD1 location number i */
|
||||
#define AF_ETM_TD2_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 1 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD2 location number i */
|
||||
#define AF_ETM_TD3_PORT(i) ((i) == 0 ? 3 : (i) == 1 ? 5 : (i) == 2 ? 3 : (i) == 3 ? 0 : (i) == 4 ? 4 : (i) == 5 ? 6 : -1) /**< Port number for AF_ETM_TD3 location number i */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_AF_Ports */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
652
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h
vendored
Normal file
652
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can.h
vendored
Normal file
@ -0,0 +1,652 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CAN register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_CAN CAN
|
||||
* @{
|
||||
* @brief EFM32GG11B_CAN Register Declaration
|
||||
******************************************************************************/
|
||||
/** CAN Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t ERRCNT; /**< Error Count Register */
|
||||
__IOM uint32_t BITTIMING; /**< Bit Timing Register */
|
||||
__IM uint32_t INTID; /**< Interrupt Identification Register */
|
||||
__IOM uint32_t TEST; /**< Test Register */
|
||||
__IOM uint32_t BRPE; /**< BRP Extension Register */
|
||||
__IM uint32_t TRANSREQ; /**< Transmission Request Register */
|
||||
__IM uint32_t MESSAGEDATA; /**< New Data Register */
|
||||
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t MESSAGESTATE; /**< Message Valid Register */
|
||||
__IOM uint32_t CONFIG; /**< Configuration Register */
|
||||
__IM uint32_t IF0IF; /**< Message Object Interrupt Flag Register */
|
||||
__IOM uint32_t IF0IFS; /**< Message Object Interrupt Flag Set Register */
|
||||
__IOM uint32_t IF0IFC; /**< Message Object Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IF0IEN; /**< Message Object Interrupt Enable Register */
|
||||
__IM uint32_t IF1IF; /**< Status Interrupt Flag Register */
|
||||
__IOM uint32_t IF1IFS; /**< Message Object Interrupt Flag Set Register */
|
||||
__IOM uint32_t IF1IFC; /**< Message Object Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IF1IEN; /**< Status Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTE; /**< I/O Routing Register */
|
||||
|
||||
uint32_t RESERVED1[3U]; /**< Reserved registers */
|
||||
CAN_MIR_TypeDef MIR[2U]; /**< Interface Registers */
|
||||
} CAN_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_CAN
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_CAN_BitFields CAN Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CAN CTRL */
|
||||
#define _CAN_CTRL_RESETVALUE 0x00000001UL /**< Default value for CAN_CTRL */
|
||||
#define _CAN_CTRL_MASK 0x000000EFUL /**< Mask for CAN_CTRL */
|
||||
#define CAN_CTRL_INIT (0x1UL << 0) /**< Initialize */
|
||||
#define _CAN_CTRL_INIT_SHIFT 0 /**< Shift value for CAN_INIT */
|
||||
#define _CAN_CTRL_INIT_MASK 0x1UL /**< Bit mask for CAN_INIT */
|
||||
#define _CAN_CTRL_INIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_INIT_DEFAULT (_CAN_CTRL_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_IE (0x1UL << 1) /**< Module Interrupt Enable */
|
||||
#define _CAN_CTRL_IE_SHIFT 1 /**< Shift value for CAN_IE */
|
||||
#define _CAN_CTRL_IE_MASK 0x2UL /**< Bit mask for CAN_IE */
|
||||
#define _CAN_CTRL_IE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_IE_DEFAULT (_CAN_CTRL_IE_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_SIE (0x1UL << 2) /**< Status Change Interrupt Enable */
|
||||
#define _CAN_CTRL_SIE_SHIFT 2 /**< Shift value for CAN_SIE */
|
||||
#define _CAN_CTRL_SIE_MASK 0x4UL /**< Bit mask for CAN_SIE */
|
||||
#define _CAN_CTRL_SIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_SIE_DEFAULT (_CAN_CTRL_SIE_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_EIE (0x1UL << 3) /**< Error Interrupt Enable */
|
||||
#define _CAN_CTRL_EIE_SHIFT 3 /**< Shift value for CAN_EIE */
|
||||
#define _CAN_CTRL_EIE_MASK 0x8UL /**< Bit mask for CAN_EIE */
|
||||
#define _CAN_CTRL_EIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_EIE_DEFAULT (_CAN_CTRL_EIE_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_DAR (0x1UL << 5) /**< Disable Automatic Retransmission */
|
||||
#define _CAN_CTRL_DAR_SHIFT 5 /**< Shift value for CAN_DAR */
|
||||
#define _CAN_CTRL_DAR_MASK 0x20UL /**< Bit mask for CAN_DAR */
|
||||
#define _CAN_CTRL_DAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_DAR_DEFAULT (_CAN_CTRL_DAR_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_CCE (0x1UL << 6) /**< Configuration Change Enable */
|
||||
#define _CAN_CTRL_CCE_SHIFT 6 /**< Shift value for CAN_CCE */
|
||||
#define _CAN_CTRL_CCE_MASK 0x40UL /**< Bit mask for CAN_CCE */
|
||||
#define _CAN_CTRL_CCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_CCE_DEFAULT (_CAN_CTRL_CCE_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_TEST (0x1UL << 7) /**< Test Mode Enable Write */
|
||||
#define _CAN_CTRL_TEST_SHIFT 7 /**< Shift value for CAN_TEST */
|
||||
#define _CAN_CTRL_TEST_MASK 0x80UL /**< Bit mask for CAN_TEST */
|
||||
#define _CAN_CTRL_TEST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CTRL */
|
||||
#define CAN_CTRL_TEST_DEFAULT (_CAN_CTRL_TEST_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_CTRL */
|
||||
|
||||
/* Bit fields for CAN STATUS */
|
||||
#define _CAN_STATUS_RESETVALUE 0x00000000UL /**< Default value for CAN_STATUS */
|
||||
#define _CAN_STATUS_MASK 0x000000FFUL /**< Mask for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_SHIFT 0 /**< Shift value for CAN_LEC */
|
||||
#define _CAN_STATUS_LEC_MASK 0x7UL /**< Bit mask for CAN_LEC */
|
||||
#define _CAN_STATUS_LEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_NONE 0x00000000UL /**< Mode NONE for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_STUFF 0x00000001UL /**< Mode STUFF for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_FORM 0x00000002UL /**< Mode FORM for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_ACK 0x00000003UL /**< Mode ACK for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_BIT1 0x00000004UL /**< Mode BIT1 for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_BIT0 0x00000005UL /**< Mode BIT0 for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_CRC 0x00000006UL /**< Mode CRC for CAN_STATUS */
|
||||
#define _CAN_STATUS_LEC_UNUSED 0x00000007UL /**< Mode UNUSED for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_DEFAULT (_CAN_STATUS_LEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_NONE (_CAN_STATUS_LEC_NONE << 0) /**< Shifted mode NONE for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_STUFF (_CAN_STATUS_LEC_STUFF << 0) /**< Shifted mode STUFF for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_FORM (_CAN_STATUS_LEC_FORM << 0) /**< Shifted mode FORM for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_ACK (_CAN_STATUS_LEC_ACK << 0) /**< Shifted mode ACK for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_BIT1 (_CAN_STATUS_LEC_BIT1 << 0) /**< Shifted mode BIT1 for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_BIT0 (_CAN_STATUS_LEC_BIT0 << 0) /**< Shifted mode BIT0 for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_CRC (_CAN_STATUS_LEC_CRC << 0) /**< Shifted mode CRC for CAN_STATUS */
|
||||
#define CAN_STATUS_LEC_UNUSED (_CAN_STATUS_LEC_UNUSED << 0) /**< Shifted mode UNUSED for CAN_STATUS */
|
||||
#define CAN_STATUS_TXOK (0x1UL << 3) /**< Transmitted a Message Successfully */
|
||||
#define _CAN_STATUS_TXOK_SHIFT 3 /**< Shift value for CAN_TXOK */
|
||||
#define _CAN_STATUS_TXOK_MASK 0x8UL /**< Bit mask for CAN_TXOK */
|
||||
#define _CAN_STATUS_TXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_TXOK_DEFAULT (_CAN_STATUS_TXOK_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_RXOK (0x1UL << 4) /**< Received a Message Successfully */
|
||||
#define _CAN_STATUS_RXOK_SHIFT 4 /**< Shift value for CAN_RXOK */
|
||||
#define _CAN_STATUS_RXOK_MASK 0x10UL /**< Bit mask for CAN_RXOK */
|
||||
#define _CAN_STATUS_RXOK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_RXOK_DEFAULT (_CAN_STATUS_RXOK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EPASS (0x1UL << 5) /**< Error Passive */
|
||||
#define _CAN_STATUS_EPASS_SHIFT 5 /**< Shift value for CAN_EPASS */
|
||||
#define _CAN_STATUS_EPASS_MASK 0x20UL /**< Bit mask for CAN_EPASS */
|
||||
#define _CAN_STATUS_EPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EPASS_DEFAULT (_CAN_STATUS_EPASS_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EWARN (0x1UL << 6) /**< Warning Status */
|
||||
#define _CAN_STATUS_EWARN_SHIFT 6 /**< Shift value for CAN_EWARN */
|
||||
#define _CAN_STATUS_EWARN_MASK 0x40UL /**< Bit mask for CAN_EWARN */
|
||||
#define _CAN_STATUS_EWARN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_EWARN_DEFAULT (_CAN_STATUS_EWARN_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_BOFF (0x1UL << 7) /**< Bus Off Status */
|
||||
#define _CAN_STATUS_BOFF_SHIFT 7 /**< Shift value for CAN_BOFF */
|
||||
#define _CAN_STATUS_BOFF_MASK 0x80UL /**< Bit mask for CAN_BOFF */
|
||||
#define _CAN_STATUS_BOFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_STATUS */
|
||||
#define CAN_STATUS_BOFF_DEFAULT (_CAN_STATUS_BOFF_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_STATUS */
|
||||
|
||||
/* Bit fields for CAN ERRCNT */
|
||||
#define _CAN_ERRCNT_RESETVALUE 0x00000000UL /**< Default value for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_MASK 0x0000FFFFUL /**< Mask for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_TEC_SHIFT 0 /**< Shift value for CAN_TEC */
|
||||
#define _CAN_ERRCNT_TEC_MASK 0xFFUL /**< Bit mask for CAN_TEC */
|
||||
#define _CAN_ERRCNT_TEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_TEC_DEFAULT (_CAN_ERRCNT_TEC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_REC_SHIFT 8 /**< Shift value for CAN_REC */
|
||||
#define _CAN_ERRCNT_REC_MASK 0x7F00UL /**< Bit mask for CAN_REC */
|
||||
#define _CAN_ERRCNT_REC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_REC_DEFAULT (_CAN_ERRCNT_REC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP (0x1UL << 15) /**< Receive Error Passive */
|
||||
#define _CAN_ERRCNT_RECERRP_SHIFT 15 /**< Shift value for CAN_RECERRP */
|
||||
#define _CAN_ERRCNT_RECERRP_MASK 0x8000UL /**< Bit mask for CAN_RECERRP */
|
||||
#define _CAN_ERRCNT_RECERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_RECERRP_FALSE 0x00000000UL /**< Mode FALSE for CAN_ERRCNT */
|
||||
#define _CAN_ERRCNT_RECERRP_TRUE 0x00000001UL /**< Mode TRUE for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_DEFAULT (_CAN_ERRCNT_RECERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_FALSE (_CAN_ERRCNT_RECERRP_FALSE << 15) /**< Shifted mode FALSE for CAN_ERRCNT */
|
||||
#define CAN_ERRCNT_RECERRP_TRUE (_CAN_ERRCNT_RECERRP_TRUE << 15) /**< Shifted mode TRUE for CAN_ERRCNT */
|
||||
|
||||
/* Bit fields for CAN BITTIMING */
|
||||
#define _CAN_BITTIMING_RESETVALUE 0x00002301UL /**< Default value for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_MASK 0x00007FFFUL /**< Mask for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_BRP_SHIFT 0 /**< Shift value for CAN_BRP */
|
||||
#define _CAN_BITTIMING_BRP_MASK 0x3FUL /**< Bit mask for CAN_BRP */
|
||||
#define _CAN_BITTIMING_BRP_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_BRP_DEFAULT (_CAN_BITTIMING_BRP_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_SJW_SHIFT 6 /**< Shift value for CAN_SJW */
|
||||
#define _CAN_BITTIMING_SJW_MASK 0xC0UL /**< Bit mask for CAN_SJW */
|
||||
#define _CAN_BITTIMING_SJW_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_SJW_DEFAULT (_CAN_BITTIMING_SJW_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_TSEG1_SHIFT 8 /**< Shift value for CAN_TSEG1 */
|
||||
#define _CAN_BITTIMING_TSEG1_MASK 0xF00UL /**< Bit mask for CAN_TSEG1 */
|
||||
#define _CAN_BITTIMING_TSEG1_DEFAULT 0x00000003UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_TSEG1_DEFAULT (_CAN_BITTIMING_TSEG1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
#define _CAN_BITTIMING_TSEG2_SHIFT 12 /**< Shift value for CAN_TSEG2 */
|
||||
#define _CAN_BITTIMING_TSEG2_MASK 0x7000UL /**< Bit mask for CAN_TSEG2 */
|
||||
#define _CAN_BITTIMING_TSEG2_DEFAULT 0x00000002UL /**< Mode DEFAULT for CAN_BITTIMING */
|
||||
#define CAN_BITTIMING_TSEG2_DEFAULT (_CAN_BITTIMING_TSEG2_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_BITTIMING */
|
||||
|
||||
/* Bit fields for CAN INTID */
|
||||
#define _CAN_INTID_RESETVALUE 0x00000000UL /**< Default value for CAN_INTID */
|
||||
#define _CAN_INTID_MASK 0x0000803FUL /**< Mask for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_SHIFT 0 /**< Shift value for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_MASK 0x3FUL /**< Bit mask for CAN_INTID */
|
||||
#define _CAN_INTID_INTID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTID_DEFAULT (_CAN_INTID_INTID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT (0x1UL << 15) /**< Status Interupt */
|
||||
#define _CAN_INTID_INTSTAT_SHIFT 15 /**< Shift value for CAN_INTSTAT */
|
||||
#define _CAN_INTID_INTSTAT_MASK 0x8000UL /**< Bit mask for CAN_INTSTAT */
|
||||
#define _CAN_INTID_INTSTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_INTID */
|
||||
#define _CAN_INTID_INTSTAT_FALSE 0x00000000UL /**< Mode FALSE for CAN_INTID */
|
||||
#define _CAN_INTID_INTSTAT_TRUE 0x00000001UL /**< Mode TRUE for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_DEFAULT (_CAN_INTID_INTSTAT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_FALSE (_CAN_INTID_INTSTAT_FALSE << 15) /**< Shifted mode FALSE for CAN_INTID */
|
||||
#define CAN_INTID_INTSTAT_TRUE (_CAN_INTID_INTSTAT_TRUE << 15) /**< Shifted mode TRUE for CAN_INTID */
|
||||
|
||||
/* Bit fields for CAN TEST */
|
||||
#define _CAN_TEST_RESETVALUE 0x00000000UL /**< Default value for CAN_TEST */
|
||||
#define _CAN_TEST_MASK 0x000000FCUL /**< Mask for CAN_TEST */
|
||||
#define CAN_TEST_BASIC (0x1UL << 2) /**< Basic Mode */
|
||||
#define _CAN_TEST_BASIC_SHIFT 2 /**< Shift value for CAN_BASIC */
|
||||
#define _CAN_TEST_BASIC_MASK 0x4UL /**< Bit mask for CAN_BASIC */
|
||||
#define _CAN_TEST_BASIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_BASIC_DEFAULT (_CAN_TEST_BASIC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_SILENT (0x1UL << 3) /**< Silent Mode */
|
||||
#define _CAN_TEST_SILENT_SHIFT 3 /**< Shift value for CAN_SILENT */
|
||||
#define _CAN_TEST_SILENT_MASK 0x8UL /**< Bit mask for CAN_SILENT */
|
||||
#define _CAN_TEST_SILENT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_SILENT_DEFAULT (_CAN_TEST_SILENT_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_LBACK (0x1UL << 4) /**< Loopback Mode */
|
||||
#define _CAN_TEST_LBACK_SHIFT 4 /**< Shift value for CAN_LBACK */
|
||||
#define _CAN_TEST_LBACK_MASK 0x10UL /**< Bit mask for CAN_LBACK */
|
||||
#define _CAN_TEST_LBACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_LBACK_DEFAULT (_CAN_TEST_LBACK_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_SHIFT 5 /**< Shift value for CAN_TX */
|
||||
#define _CAN_TEST_TX_MASK 0x60UL /**< Bit mask for CAN_TX */
|
||||
#define _CAN_TEST_TX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_CORE 0x00000000UL /**< Mode CORE for CAN_TEST */
|
||||
#define _CAN_TEST_TX_SAMPT 0x00000001UL /**< Mode SAMPT for CAN_TEST */
|
||||
#define _CAN_TEST_TX_LOW 0x00000002UL /**< Mode LOW for CAN_TEST */
|
||||
#define _CAN_TEST_TX_HIGH 0x00000003UL /**< Mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_TX_DEFAULT (_CAN_TEST_TX_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_TX_CORE (_CAN_TEST_TX_CORE << 5) /**< Shifted mode CORE for CAN_TEST */
|
||||
#define CAN_TEST_TX_SAMPT (_CAN_TEST_TX_SAMPT << 5) /**< Shifted mode SAMPT for CAN_TEST */
|
||||
#define CAN_TEST_TX_LOW (_CAN_TEST_TX_LOW << 5) /**< Shifted mode LOW for CAN_TEST */
|
||||
#define CAN_TEST_TX_HIGH (_CAN_TEST_TX_HIGH << 5) /**< Shifted mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_RX (0x1UL << 7) /**< Monitors the Actual Value of CAN_RX Pin */
|
||||
#define _CAN_TEST_RX_SHIFT 7 /**< Shift value for CAN_RX */
|
||||
#define _CAN_TEST_RX_MASK 0x80UL /**< Bit mask for CAN_RX */
|
||||
#define _CAN_TEST_RX_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TEST */
|
||||
#define _CAN_TEST_RX_LOW 0x00000000UL /**< Mode LOW for CAN_TEST */
|
||||
#define _CAN_TEST_RX_HIGH 0x00000001UL /**< Mode HIGH for CAN_TEST */
|
||||
#define CAN_TEST_RX_DEFAULT (_CAN_TEST_RX_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_TEST */
|
||||
#define CAN_TEST_RX_LOW (_CAN_TEST_RX_LOW << 7) /**< Shifted mode LOW for CAN_TEST */
|
||||
#define CAN_TEST_RX_HIGH (_CAN_TEST_RX_HIGH << 7) /**< Shifted mode HIGH for CAN_TEST */
|
||||
|
||||
/* Bit fields for CAN BRPE */
|
||||
#define _CAN_BRPE_RESETVALUE 0x00000000UL /**< Default value for CAN_BRPE */
|
||||
#define _CAN_BRPE_MASK 0x0000000FUL /**< Mask for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_SHIFT 0 /**< Shift value for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_MASK 0xFUL /**< Bit mask for CAN_BRPE */
|
||||
#define _CAN_BRPE_BRPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_BRPE */
|
||||
#define CAN_BRPE_BRPE_DEFAULT (_CAN_BRPE_BRPE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_BRPE */
|
||||
|
||||
/* Bit fields for CAN TRANSREQ */
|
||||
#define _CAN_TRANSREQ_RESETVALUE 0x00000000UL /**< Default value for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_MASK 0xFFFFFFFFUL /**< Mask for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_SHIFT 0 /**< Shift value for CAN_TXRQSTOUT */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_TXRQSTOUT */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_FALSE 0x00000000UL /**< Mode FALSE for CAN_TRANSREQ */
|
||||
#define _CAN_TRANSREQ_TXRQSTOUT_TRUE 0x00000001UL /**< Mode TRUE for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_DEFAULT (_CAN_TRANSREQ_TXRQSTOUT_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_FALSE (_CAN_TRANSREQ_TXRQSTOUT_FALSE << 0) /**< Shifted mode FALSE for CAN_TRANSREQ */
|
||||
#define CAN_TRANSREQ_TXRQSTOUT_TRUE (_CAN_TRANSREQ_TXRQSTOUT_TRUE << 0) /**< Shifted mode TRUE for CAN_TRANSREQ */
|
||||
|
||||
/* Bit fields for CAN MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGEDATA */
|
||||
#define _CAN_MESSAGEDATA_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
|
||||
#define _CAN_MESSAGEDATA_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
|
||||
#define _CAN_MESSAGEDATA_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGEDATA */
|
||||
#define CAN_MESSAGEDATA_VALID_DEFAULT (_CAN_MESSAGEDATA_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGEDATA */
|
||||
|
||||
/* Bit fields for CAN MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_RESETVALUE 0x00000000UL /**< Default value for CAN_MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_MASK 0xFFFFFFFFUL /**< Mask for CAN_MESSAGESTATE */
|
||||
#define _CAN_MESSAGESTATE_VALID_SHIFT 0 /**< Shift value for CAN_VALID */
|
||||
#define _CAN_MESSAGESTATE_VALID_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_VALID */
|
||||
#define _CAN_MESSAGESTATE_VALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MESSAGESTATE */
|
||||
#define CAN_MESSAGESTATE_VALID_DEFAULT (_CAN_MESSAGESTATE_VALID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MESSAGESTATE */
|
||||
|
||||
/* Bit fields for CAN CONFIG */
|
||||
#define _CAN_CONFIG_RESETVALUE 0x00000000UL /**< Default value for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_MASK 0x00008000UL /**< Mask for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT (0x1UL << 15) /**< Debug Halt */
|
||||
#define _CAN_CONFIG_DBGHALT_SHIFT 15 /**< Shift value for CAN_DBGHALT */
|
||||
#define _CAN_CONFIG_DBGHALT_MASK 0x8000UL /**< Bit mask for CAN_DBGHALT */
|
||||
#define _CAN_CONFIG_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_DBGHALT_NORMAL 0x00000000UL /**< Mode NORMAL for CAN_CONFIG */
|
||||
#define _CAN_CONFIG_DBGHALT_STALL 0x00000001UL /**< Mode STALL for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_DEFAULT (_CAN_CONFIG_DBGHALT_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_NORMAL (_CAN_CONFIG_DBGHALT_NORMAL << 15) /**< Shifted mode NORMAL for CAN_CONFIG */
|
||||
#define CAN_CONFIG_DBGHALT_STALL (_CAN_CONFIG_DBGHALT_STALL << 15) /**< Shifted mode STALL for CAN_CONFIG */
|
||||
|
||||
/* Bit fields for CAN IF0IF */
|
||||
#define _CAN_IF0IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IF */
|
||||
#define _CAN_IF0IF_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IF */
|
||||
#define _CAN_IF0IF_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IF_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IF_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IF */
|
||||
#define CAN_IF0IF_MESSAGE_DEFAULT (_CAN_IF0IF_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IF */
|
||||
|
||||
/* Bit fields for CAN IF0IFS */
|
||||
#define _CAN_IF0IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFS */
|
||||
#define _CAN_IF0IFS_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFS */
|
||||
#define _CAN_IF0IFS_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFS_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFS_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFS */
|
||||
#define CAN_IF0IFS_MESSAGE_DEFAULT (_CAN_IF0IFS_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFS */
|
||||
|
||||
/* Bit fields for CAN IF0IFC */
|
||||
#define _CAN_IF0IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF0IFC */
|
||||
#define _CAN_IF0IFC_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IFC */
|
||||
#define _CAN_IF0IFC_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFC_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IFC_MESSAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF0IFC */
|
||||
#define CAN_IF0IFC_MESSAGE_DEFAULT (_CAN_IF0IFC_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IFC */
|
||||
|
||||
/* Bit fields for CAN IF0IEN */
|
||||
#define _CAN_IF0IEN_RESETVALUE 0xFFFFFFFFUL /**< Default value for CAN_IF0IEN */
|
||||
#define _CAN_IF0IEN_MASK 0xFFFFFFFFUL /**< Mask for CAN_IF0IEN */
|
||||
#define _CAN_IF0IEN_MESSAGE_SHIFT 0 /**< Shift value for CAN_MESSAGE */
|
||||
#define _CAN_IF0IEN_MESSAGE_MASK 0xFFFFFFFFUL /**< Bit mask for CAN_MESSAGE */
|
||||
#define _CAN_IF0IEN_MESSAGE_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for CAN_IF0IEN */
|
||||
#define CAN_IF0IEN_MESSAGE_DEFAULT (_CAN_IF0IEN_MESSAGE_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF0IEN */
|
||||
|
||||
/* Bit fields for CAN IF1IF */
|
||||
#define _CAN_IF1IF_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IF */
|
||||
#define _CAN_IF1IF_MASK 0x00000001UL /**< Mask for CAN_IF1IF */
|
||||
#define CAN_IF1IF_STATUS (0x1UL << 0) /**< Status Interrupt Flag */
|
||||
#define _CAN_IF1IF_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IF_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IF_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IF */
|
||||
#define CAN_IF1IF_STATUS_DEFAULT (_CAN_IF1IF_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IF */
|
||||
|
||||
/* Bit fields for CAN IF1IFS */
|
||||
#define _CAN_IF1IFS_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFS */
|
||||
#define _CAN_IF1IFS_MASK 0x00000001UL /**< Mask for CAN_IF1IFS */
|
||||
#define CAN_IF1IFS_STATUS (0x1UL << 0) /**< Set STATUS Interrupt Flag */
|
||||
#define _CAN_IF1IFS_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IFS_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IFS_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFS */
|
||||
#define CAN_IF1IFS_STATUS_DEFAULT (_CAN_IF1IFS_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFS */
|
||||
|
||||
/* Bit fields for CAN IF1IFC */
|
||||
#define _CAN_IF1IFC_RESETVALUE 0x00000000UL /**< Default value for CAN_IF1IFC */
|
||||
#define _CAN_IF1IFC_MASK 0x00000001UL /**< Mask for CAN_IF1IFC */
|
||||
#define CAN_IF1IFC_STATUS (0x1UL << 0) /**< Clear STATUS Interrupt Flag */
|
||||
#define _CAN_IF1IFC_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IFC_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IFC_STATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_IF1IFC */
|
||||
#define CAN_IF1IFC_STATUS_DEFAULT (_CAN_IF1IFC_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IFC */
|
||||
|
||||
/* Bit fields for CAN IF1IEN */
|
||||
#define _CAN_IF1IEN_RESETVALUE 0x00000001UL /**< Default value for CAN_IF1IEN */
|
||||
#define _CAN_IF1IEN_MASK 0x00000001UL /**< Mask for CAN_IF1IEN */
|
||||
#define CAN_IF1IEN_STATUS (0x1UL << 0) /**< STATUS Interrupt Enable */
|
||||
#define _CAN_IF1IEN_STATUS_SHIFT 0 /**< Shift value for CAN_STATUS */
|
||||
#define _CAN_IF1IEN_STATUS_MASK 0x1UL /**< Bit mask for CAN_STATUS */
|
||||
#define _CAN_IF1IEN_STATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_IF1IEN */
|
||||
#define CAN_IF1IEN_STATUS_DEFAULT (_CAN_IF1IEN_STATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_IF1IEN */
|
||||
|
||||
/* Bit fields for CAN ROUTE */
|
||||
#define _CAN_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_MASK 0x0000071DUL /**< Mask for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXPEN (0x1UL << 0) /**< TX Pin Enable */
|
||||
#define _CAN_ROUTE_TXPEN_SHIFT 0 /**< Shift value for CAN_TXPEN */
|
||||
#define _CAN_ROUTE_TXPEN_MASK 0x1UL /**< Bit mask for CAN_TXPEN */
|
||||
#define _CAN_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXPEN_DEFAULT (_CAN_ROUTE_TXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_SHIFT 2 /**< Shift value for CAN_RXLOC */
|
||||
#define _CAN_ROUTE_RXLOC_MASK 0x1CUL /**< Bit mask for CAN_RXLOC */
|
||||
#define _CAN_ROUTE_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC0 (_CAN_ROUTE_RXLOC_LOC0 << 2) /**< Shifted mode LOC0 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_DEFAULT (_CAN_ROUTE_RXLOC_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC1 (_CAN_ROUTE_RXLOC_LOC1 << 2) /**< Shifted mode LOC1 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC2 (_CAN_ROUTE_RXLOC_LOC2 << 2) /**< Shifted mode LOC2 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC3 (_CAN_ROUTE_RXLOC_LOC3 << 2) /**< Shifted mode LOC3 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC4 (_CAN_ROUTE_RXLOC_LOC4 << 2) /**< Shifted mode LOC4 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC5 (_CAN_ROUTE_RXLOC_LOC5 << 2) /**< Shifted mode LOC5 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC6 (_CAN_ROUTE_RXLOC_LOC6 << 2) /**< Shifted mode LOC6 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_RXLOC_LOC7 (_CAN_ROUTE_RXLOC_LOC7 << 2) /**< Shifted mode LOC7 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_SHIFT 8 /**< Shift value for CAN_TXLOC */
|
||||
#define _CAN_ROUTE_TXLOC_MASK 0x700UL /**< Bit mask for CAN_TXLOC */
|
||||
#define _CAN_ROUTE_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for CAN_ROUTE */
|
||||
#define _CAN_ROUTE_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC0 (_CAN_ROUTE_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_DEFAULT (_CAN_ROUTE_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC1 (_CAN_ROUTE_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC2 (_CAN_ROUTE_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC3 (_CAN_ROUTE_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC4 (_CAN_ROUTE_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC5 (_CAN_ROUTE_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC6 (_CAN_ROUTE_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for CAN_ROUTE */
|
||||
#define CAN_ROUTE_TXLOC_LOC7 (_CAN_ROUTE_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for CAN_ROUTE */
|
||||
|
||||
/* Bit fields for CAN MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_MASK 0x000000FFUL /**< Mask for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAB (0x1UL << 0) /**< CC Channel Mode */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_SHIFT 0 /**< Shift value for CAN_DATAB */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_MASK 0x1UL /**< Bit mask for CAN_DATAB */
|
||||
#define _CAN_MIR_CMDMASK_DATAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAB_DEFAULT (_CAN_MIR_CMDMASK_DATAB_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAA (0x1UL << 1) /**< Access Data Bytes 0-3 */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_SHIFT 1 /**< Shift value for CAN_DATAA */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_MASK 0x2UL /**< Bit mask for CAN_DATAA */
|
||||
#define _CAN_MIR_CMDMASK_DATAA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_DATAA_DEFAULT (_CAN_MIR_CMDMASK_DATAA_DEFAULT << 1) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_TXRQSTNEWDAT (0x1UL << 2) /**< Transmission Request Bit/ New Data Bit */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_SHIFT 2 /**< Shift value for CAN_TXRQSTNEWDAT */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_MASK 0x4UL /**< Bit mask for CAN_TXRQSTNEWDAT */
|
||||
#define _CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT (_CAN_MIR_CMDMASK_TXRQSTNEWDAT_DEFAULT << 2) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CLRINTPND (0x1UL << 3) /**< Clear Interrupt Pending Bit */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_SHIFT 3 /**< Shift value for CAN_CLRINTPND */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_MASK 0x8UL /**< Bit mask for CAN_CLRINTPND */
|
||||
#define _CAN_MIR_CMDMASK_CLRINTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CLRINTPND_DEFAULT (_CAN_MIR_CMDMASK_CLRINTPND_DEFAULT << 3) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CONTROL (0x1UL << 4) /**< Access Control Bits */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_SHIFT 4 /**< Shift value for CAN_CONTROL */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_MASK 0x10UL /**< Bit mask for CAN_CONTROL */
|
||||
#define _CAN_MIR_CMDMASK_CONTROL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_CONTROL_DEFAULT (_CAN_MIR_CMDMASK_CONTROL_DEFAULT << 4) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_ARBACC (0x1UL << 5) /**< Access Arbitration Bits */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_SHIFT 5 /**< Shift value for CAN_ARBACC */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_MASK 0x20UL /**< Bit mask for CAN_ARBACC */
|
||||
#define _CAN_MIR_CMDMASK_ARBACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_ARBACC_DEFAULT (_CAN_MIR_CMDMASK_ARBACC_DEFAULT << 5) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_MASKACC (0x1UL << 6) /**< Access Mask Bits */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_SHIFT 6 /**< Shift value for CAN_MASKACC */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_MASK 0x40UL /**< Bit mask for CAN_MASKACC */
|
||||
#define _CAN_MIR_CMDMASK_MASKACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_MASKACC_DEFAULT (_CAN_MIR_CMDMASK_MASKACC_DEFAULT << 6) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD (0x1UL << 7) /**< Write/Read RAM */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_SHIFT 7 /**< Shift value for CAN_WRRD */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_MASK 0x80UL /**< Bit mask for CAN_WRRD */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_READ 0x00000000UL /**< Mode READ for CAN_MIR_CMDMASK */
|
||||
#define _CAN_MIR_CMDMASK_WRRD_WRITE 0x00000001UL /**< Mode WRITE for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_DEFAULT (_CAN_MIR_CMDMASK_WRRD_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_READ (_CAN_MIR_CMDMASK_WRRD_READ << 7) /**< Shifted mode READ for CAN_MIR_CMDMASK */
|
||||
#define CAN_MIR_CMDMASK_WRRD_WRITE (_CAN_MIR_CMDMASK_WRRD_WRITE << 7) /**< Shifted mode WRITE for CAN_MIR_CMDMASK */
|
||||
|
||||
/* Bit fields for CAN MIR_MASK */
|
||||
#define _CAN_MIR_MASK_RESETVALUE 0xDFFFFFFFUL /**< Default value for CAN_MIR_MASK */
|
||||
#define _CAN_MIR_MASK_MASK 0xDFFFFFFFUL /**< Mask for CAN_MIR_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_SHIFT 0 /**< Shift value for CAN_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_MASK */
|
||||
#define _CAN_MIR_MASK_MASK_DEFAULT 0x1FFFFFFFUL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MASK_DEFAULT (_CAN_MIR_MASK_MASK_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MDIR (0x1UL << 30) /**< Mask Message Direction */
|
||||
#define _CAN_MIR_MASK_MDIR_SHIFT 30 /**< Shift value for CAN_MDIR */
|
||||
#define _CAN_MIR_MASK_MDIR_MASK 0x40000000UL /**< Bit mask for CAN_MDIR */
|
||||
#define _CAN_MIR_MASK_MDIR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MDIR_DEFAULT (_CAN_MIR_MASK_MDIR_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MXTD (0x1UL << 31) /**< Mask Extended Identifier */
|
||||
#define _CAN_MIR_MASK_MXTD_SHIFT 31 /**< Shift value for CAN_MXTD */
|
||||
#define _CAN_MIR_MASK_MXTD_MASK 0x80000000UL /**< Bit mask for CAN_MXTD */
|
||||
#define _CAN_MIR_MASK_MXTD_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_MASK */
|
||||
#define CAN_MIR_MASK_MXTD_DEFAULT (_CAN_MIR_MASK_MXTD_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_MASK */
|
||||
|
||||
/* Bit fields for CAN MIR_ARB */
|
||||
#define _CAN_MIR_ARB_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_ID_SHIFT 0 /**< Shift value for CAN_ID */
|
||||
#define _CAN_MIR_ARB_ID_MASK 0x1FFFFFFFUL /**< Bit mask for CAN_ID */
|
||||
#define _CAN_MIR_ARB_ID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_ID_DEFAULT (_CAN_MIR_ARB_ID_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR (0x1UL << 29) /**< Message Direction */
|
||||
#define _CAN_MIR_ARB_DIR_SHIFT 29 /**< Shift value for CAN_DIR */
|
||||
#define _CAN_MIR_ARB_DIR_MASK 0x20000000UL /**< Bit mask for CAN_DIR */
|
||||
#define _CAN_MIR_ARB_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_DIR_RX 0x00000000UL /**< Mode RX for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_DIR_TX 0x00000001UL /**< Mode TX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_DEFAULT (_CAN_MIR_ARB_DIR_DEFAULT << 29) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_RX (_CAN_MIR_ARB_DIR_RX << 29) /**< Shifted mode RX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_DIR_TX (_CAN_MIR_ARB_DIR_TX << 29) /**< Shifted mode TX for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD (0x1UL << 30) /**< Extended Identifier */
|
||||
#define _CAN_MIR_ARB_XTD_SHIFT 30 /**< Shift value for CAN_XTD */
|
||||
#define _CAN_MIR_ARB_XTD_MASK 0x40000000UL /**< Bit mask for CAN_XTD */
|
||||
#define _CAN_MIR_ARB_XTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_XTD_STD 0x00000000UL /**< Mode STD for CAN_MIR_ARB */
|
||||
#define _CAN_MIR_ARB_XTD_EXT 0x00000001UL /**< Mode EXT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_DEFAULT (_CAN_MIR_ARB_XTD_DEFAULT << 30) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_STD (_CAN_MIR_ARB_XTD_STD << 30) /**< Shifted mode STD for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_XTD_EXT (_CAN_MIR_ARB_XTD_EXT << 30) /**< Shifted mode EXT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_MSGVAL (0x1UL << 31) /**< Message Valid */
|
||||
#define _CAN_MIR_ARB_MSGVAL_SHIFT 31 /**< Shift value for CAN_MSGVAL */
|
||||
#define _CAN_MIR_ARB_MSGVAL_MASK 0x80000000UL /**< Bit mask for CAN_MSGVAL */
|
||||
#define _CAN_MIR_ARB_MSGVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_ARB */
|
||||
#define CAN_MIR_ARB_MSGVAL_DEFAULT (_CAN_MIR_ARB_MSGVAL_DEFAULT << 31) /**< Shifted mode DEFAULT for CAN_MIR_ARB */
|
||||
|
||||
/* Bit fields for CAN MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_MASK 0x0000FF8FUL /**< Mask for CAN_MIR_CTRL */
|
||||
#define _CAN_MIR_CTRL_DLC_SHIFT 0 /**< Shift value for CAN_DLC */
|
||||
#define _CAN_MIR_CTRL_DLC_MASK 0xFUL /**< Bit mask for CAN_DLC */
|
||||
#define _CAN_MIR_CTRL_DLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DLC_DEFAULT (_CAN_MIR_CTRL_DLC_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_EOB (0x1UL << 7) /**< End of Buffer */
|
||||
#define _CAN_MIR_CTRL_EOB_SHIFT 7 /**< Shift value for CAN_EOB */
|
||||
#define _CAN_MIR_CTRL_EOB_MASK 0x80UL /**< Bit mask for CAN_EOB */
|
||||
#define _CAN_MIR_CTRL_EOB_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_EOB_DEFAULT (_CAN_MIR_CTRL_EOB_DEFAULT << 7) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXRQST (0x1UL << 8) /**< Transmit Request */
|
||||
#define _CAN_MIR_CTRL_TXRQST_SHIFT 8 /**< Shift value for CAN_TXRQST */
|
||||
#define _CAN_MIR_CTRL_TXRQST_MASK 0x100UL /**< Bit mask for CAN_TXRQST */
|
||||
#define _CAN_MIR_CTRL_TXRQST_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXRQST_DEFAULT (_CAN_MIR_CTRL_TXRQST_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RMTEN (0x1UL << 9) /**< Remote Enable */
|
||||
#define _CAN_MIR_CTRL_RMTEN_SHIFT 9 /**< Shift value for CAN_RMTEN */
|
||||
#define _CAN_MIR_CTRL_RMTEN_MASK 0x200UL /**< Bit mask for CAN_RMTEN */
|
||||
#define _CAN_MIR_CTRL_RMTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RMTEN_DEFAULT (_CAN_MIR_CTRL_RMTEN_DEFAULT << 9) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RXIE (0x1UL << 10) /**< Receive Interrupt Enable */
|
||||
#define _CAN_MIR_CTRL_RXIE_SHIFT 10 /**< Shift value for CAN_RXIE */
|
||||
#define _CAN_MIR_CTRL_RXIE_MASK 0x400UL /**< Bit mask for CAN_RXIE */
|
||||
#define _CAN_MIR_CTRL_RXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_RXIE_DEFAULT (_CAN_MIR_CTRL_RXIE_DEFAULT << 10) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXIE (0x1UL << 11) /**< Transmit Interrupt Enable */
|
||||
#define _CAN_MIR_CTRL_TXIE_SHIFT 11 /**< Shift value for CAN_TXIE */
|
||||
#define _CAN_MIR_CTRL_TXIE_MASK 0x800UL /**< Bit mask for CAN_TXIE */
|
||||
#define _CAN_MIR_CTRL_TXIE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_TXIE_DEFAULT (_CAN_MIR_CTRL_TXIE_DEFAULT << 11) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_UMASK (0x1UL << 12) /**< Use Acceptance Mask */
|
||||
#define _CAN_MIR_CTRL_UMASK_SHIFT 12 /**< Shift value for CAN_UMASK */
|
||||
#define _CAN_MIR_CTRL_UMASK_MASK 0x1000UL /**< Bit mask for CAN_UMASK */
|
||||
#define _CAN_MIR_CTRL_UMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_UMASK_DEFAULT (_CAN_MIR_CTRL_UMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_INTPND (0x1UL << 13) /**< Interrupt Pending */
|
||||
#define _CAN_MIR_CTRL_INTPND_SHIFT 13 /**< Shift value for CAN_INTPND */
|
||||
#define _CAN_MIR_CTRL_INTPND_MASK 0x2000UL /**< Bit mask for CAN_INTPND */
|
||||
#define _CAN_MIR_CTRL_INTPND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_INTPND_DEFAULT (_CAN_MIR_CTRL_INTPND_DEFAULT << 13) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_MESSAGEOF (0x1UL << 14) /**< Message Lost (only Valid for Message Objects With Direction = Receive) */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_SHIFT 14 /**< Shift value for CAN_MESSAGEOF */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_MASK 0x4000UL /**< Bit mask for CAN_MESSAGEOF */
|
||||
#define _CAN_MIR_CTRL_MESSAGEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_MESSAGEOF_DEFAULT (_CAN_MIR_CTRL_MESSAGEOF_DEFAULT << 14) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DATAVALID (0x1UL << 15) /**< New Data */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_SHIFT 15 /**< Shift value for CAN_DATAVALID */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_MASK 0x8000UL /**< Bit mask for CAN_DATAVALID */
|
||||
#define _CAN_MIR_CTRL_DATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CTRL */
|
||||
#define CAN_MIR_CTRL_DATAVALID_DEFAULT (_CAN_MIR_CTRL_DATAVALID_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CTRL */
|
||||
|
||||
/* Bit fields for CAN MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA0_SHIFT 0 /**< Shift value for CAN_DATA0 */
|
||||
#define _CAN_MIR_DATAL_DATA0_MASK 0xFFUL /**< Bit mask for CAN_DATA0 */
|
||||
#define _CAN_MIR_DATAL_DATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA0_DEFAULT (_CAN_MIR_DATAL_DATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA1_SHIFT 8 /**< Shift value for CAN_DATA1 */
|
||||
#define _CAN_MIR_DATAL_DATA1_MASK 0xFF00UL /**< Bit mask for CAN_DATA1 */
|
||||
#define _CAN_MIR_DATAL_DATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA1_DEFAULT (_CAN_MIR_DATAL_DATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA2_SHIFT 16 /**< Shift value for CAN_DATA2 */
|
||||
#define _CAN_MIR_DATAL_DATA2_MASK 0xFF0000UL /**< Bit mask for CAN_DATA2 */
|
||||
#define _CAN_MIR_DATAL_DATA2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA2_DEFAULT (_CAN_MIR_DATAL_DATA2_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define _CAN_MIR_DATAL_DATA3_SHIFT 24 /**< Shift value for CAN_DATA3 */
|
||||
#define _CAN_MIR_DATAL_DATA3_MASK 0xFF000000UL /**< Bit mask for CAN_DATA3 */
|
||||
#define _CAN_MIR_DATAL_DATA3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAL */
|
||||
#define CAN_MIR_DATAL_DATA3_DEFAULT (_CAN_MIR_DATAL_DATA3_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAL */
|
||||
|
||||
/* Bit fields for CAN MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_RESETVALUE 0x00000000UL /**< Default value for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_MASK 0xFFFFFFFFUL /**< Mask for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA4_SHIFT 0 /**< Shift value for CAN_DATA4 */
|
||||
#define _CAN_MIR_DATAH_DATA4_MASK 0xFFUL /**< Bit mask for CAN_DATA4 */
|
||||
#define _CAN_MIR_DATAH_DATA4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA4_DEFAULT (_CAN_MIR_DATAH_DATA4_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA5_SHIFT 8 /**< Shift value for CAN_DATA5 */
|
||||
#define _CAN_MIR_DATAH_DATA5_MASK 0xFF00UL /**< Bit mask for CAN_DATA5 */
|
||||
#define _CAN_MIR_DATAH_DATA5_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA5_DEFAULT (_CAN_MIR_DATAH_DATA5_DEFAULT << 8) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA6_SHIFT 16 /**< Shift value for CAN_DATA6 */
|
||||
#define _CAN_MIR_DATAH_DATA6_MASK 0xFF0000UL /**< Bit mask for CAN_DATA6 */
|
||||
#define _CAN_MIR_DATAH_DATA6_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA6_DEFAULT (_CAN_MIR_DATAH_DATA6_DEFAULT << 16) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define _CAN_MIR_DATAH_DATA7_SHIFT 24 /**< Shift value for CAN_DATA7 */
|
||||
#define _CAN_MIR_DATAH_DATA7_MASK 0xFF000000UL /**< Bit mask for CAN_DATA7 */
|
||||
#define _CAN_MIR_DATAH_DATA7_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_DATAH */
|
||||
#define CAN_MIR_DATAH_DATA7_DEFAULT (_CAN_MIR_DATAH_DATA7_DEFAULT << 24) /**< Shifted mode DEFAULT for CAN_MIR_DATAH */
|
||||
|
||||
/* Bit fields for CAN MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_RESETVALUE 0x00000001UL /**< Default value for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_MASK 0x0000803FUL /**< Mask for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_SHIFT 0 /**< Shift value for CAN_MSGNUM */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_MASK 0x3FUL /**< Bit mask for CAN_MSGNUM */
|
||||
#define _CAN_MIR_CMDREQ_MSGNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_MSGNUM_DEFAULT (_CAN_MIR_CMDREQ_MSGNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY (0x1UL << 15) /**< Busy Flag */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_SHIFT 15 /**< Shift value for CAN_BUSY */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_MASK 0x8000UL /**< Bit mask for CAN_BUSY */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_FALSE 0x00000000UL /**< Mode FALSE for CAN_MIR_CMDREQ */
|
||||
#define _CAN_MIR_CMDREQ_BUSY_TRUE 0x00000001UL /**< Mode TRUE for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_DEFAULT (_CAN_MIR_CMDREQ_BUSY_DEFAULT << 15) /**< Shifted mode DEFAULT for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_FALSE (_CAN_MIR_CMDREQ_BUSY_FALSE << 15) /**< Shifted mode FALSE for CAN_MIR_CMDREQ */
|
||||
#define CAN_MIR_CMDREQ_BUSY_TRUE (_CAN_MIR_CMDREQ_BUSY_TRUE << 15) /**< Shifted mode TRUE for CAN_MIR_CMDREQ */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_CAN */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h
vendored
Normal file
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_can_mir.h
vendored
Normal file
@ -0,0 +1,65 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CAN_MIR register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief CAN_MIR CAN MIR Register
|
||||
* @ingroup EFM32GG11B_CAN
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CMDMASK; /**< Interface Command Mask Register */
|
||||
__IOM uint32_t MASK; /**< Interface Mask Register */
|
||||
__IOM uint32_t ARB; /**< Interface Arbitration Register */
|
||||
__IOM uint32_t CTRL; /**< Interface Message Control Register */
|
||||
__IOM uint32_t DATAL; /**< Interface Data a Register */
|
||||
__IOM uint32_t DATAH; /**< Interface Data B Register */
|
||||
__IOM uint32_t CMDREQ; /**< Interface Command Request Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved future */
|
||||
} CAN_MIR_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
2698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h
vendored
Normal file
2698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cmu.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
183
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h
vendored
Normal file
183
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_cryotimer.h
vendored
Normal file
@ -0,0 +1,183 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_CRYOTIMER register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_CRYOTIMER CRYOTIMER
|
||||
* @{
|
||||
* @brief EFM32GG11B_CRYOTIMER Register Declaration
|
||||
******************************************************************************/
|
||||
/** CRYOTIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t PERIODSEL; /**< Interrupt Duration */
|
||||
__IM uint32_t CNT; /**< Counter Value */
|
||||
__IOM uint32_t EM4WUEN; /**< Wake Up Enable */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} CRYOTIMER_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_CRYOTIMER
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_CRYOTIMER_BitFields CRYOTIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for CRYOTIMER CTRL */
|
||||
#define _CRYOTIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_MASK 0x000000EFUL /**< Mask for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_EN (0x1UL << 0) /**< Enable CRYOTIMER */
|
||||
#define _CRYOTIMER_CTRL_EN_SHIFT 0 /**< Shift value for CRYOTIMER_EN */
|
||||
#define _CRYOTIMER_CTRL_EN_MASK 0x1UL /**< Bit mask for CRYOTIMER_EN */
|
||||
#define _CRYOTIMER_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_EN_DEFAULT (_CRYOTIMER_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for CRYOTIMER_DEBUGRUN */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for CRYOTIMER_DEBUGRUN */
|
||||
#define _CRYOTIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_DEBUGRUN_DEFAULT (_CRYOTIMER_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_SHIFT 2 /**< Shift value for CRYOTIMER_OSCSEL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_MASK 0xCUL /**< Bit mask for CRYOTIMER_OSCSEL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_LFXO 0x00000002UL /**< Mode LFXO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_OSCSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_DEFAULT (_CRYOTIMER_CTRL_OSCSEL_DEFAULT << 2) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_DISABLED (_CRYOTIMER_CTRL_OSCSEL_DISABLED << 2) /**< Shifted mode DISABLED for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_LFRCO (_CRYOTIMER_CTRL_OSCSEL_LFRCO << 2) /**< Shifted mode LFRCO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_LFXO (_CRYOTIMER_CTRL_OSCSEL_LFXO << 2) /**< Shifted mode LFXO for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_OSCSEL_ULFRCO (_CRYOTIMER_CTRL_OSCSEL_ULFRCO << 2) /**< Shifted mode ULFRCO for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_SHIFT 5 /**< Shift value for CRYOTIMER_PRESC */
|
||||
#define _CRYOTIMER_CTRL_PRESC_MASK 0xE0UL /**< Bit mask for CRYOTIMER_PRESC */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for CRYOTIMER_CTRL */
|
||||
#define _CRYOTIMER_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DEFAULT (_CRYOTIMER_CTRL_PRESC_DEFAULT << 5) /**< Shifted mode DEFAULT for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV1 (_CRYOTIMER_CTRL_PRESC_DIV1 << 5) /**< Shifted mode DIV1 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV2 (_CRYOTIMER_CTRL_PRESC_DIV2 << 5) /**< Shifted mode DIV2 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV4 (_CRYOTIMER_CTRL_PRESC_DIV4 << 5) /**< Shifted mode DIV4 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV8 (_CRYOTIMER_CTRL_PRESC_DIV8 << 5) /**< Shifted mode DIV8 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV16 (_CRYOTIMER_CTRL_PRESC_DIV16 << 5) /**< Shifted mode DIV16 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV32 (_CRYOTIMER_CTRL_PRESC_DIV32 << 5) /**< Shifted mode DIV32 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV64 (_CRYOTIMER_CTRL_PRESC_DIV64 << 5) /**< Shifted mode DIV64 for CRYOTIMER_CTRL */
|
||||
#define CRYOTIMER_CTRL_PRESC_DIV128 (_CRYOTIMER_CTRL_PRESC_DIV128 << 5) /**< Shifted mode DIV128 for CRYOTIMER_CTRL */
|
||||
|
||||
/* Bit fields for CRYOTIMER PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_RESETVALUE 0x00000020UL /**< Default value for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_MASK 0x0000003FUL /**< Mask for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_SHIFT 0 /**< Shift value for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_MASK 0x3FUL /**< Bit mask for CRYOTIMER_PERIODSEL */
|
||||
#define _CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT 0x00000020UL /**< Mode DEFAULT for CRYOTIMER_PERIODSEL */
|
||||
#define CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT (_CRYOTIMER_PERIODSEL_PERIODSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_PERIODSEL */
|
||||
|
||||
/* Bit fields for CRYOTIMER CNT */
|
||||
#define _CRYOTIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_MASK 0xFFFFFFFFUL /**< Mask for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_SHIFT 0 /**< Shift value for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for CRYOTIMER_CNT */
|
||||
#define _CRYOTIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_CNT */
|
||||
#define CRYOTIMER_CNT_CNT_DEFAULT (_CRYOTIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_CNT */
|
||||
|
||||
/* Bit fields for CRYOTIMER EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_EM4WUEN */
|
||||
#define _CRYOTIMER_EM4WUEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_EM4WUEN */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU (0x1UL << 0) /**< EM4 Wake-up Enable */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_SHIFT 0 /**< Shift value for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_MASK 0x1UL /**< Bit mask for CRYOTIMER_EM4WU */
|
||||
#define _CRYOTIMER_EM4WUEN_EM4WU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_EM4WUEN */
|
||||
#define CRYOTIMER_EM4WUEN_EM4WU_DEFAULT (_CRYOTIMER_EM4WUEN_EM4WU_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_EM4WUEN */
|
||||
|
||||
/* Bit fields for CRYOTIMER IF */
|
||||
#define _CRYOTIMER_IF_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IF */
|
||||
#define _CRYOTIMER_IF_MASK 0x00000001UL /**< Mask for CRYOTIMER_IF */
|
||||
#define CRYOTIMER_IF_PERIOD (0x1UL << 0) /**< Wakeup Event/Interrupt */
|
||||
#define _CRYOTIMER_IF_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IF_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IF */
|
||||
#define CRYOTIMER_IF_PERIOD_DEFAULT (_CRYOTIMER_IF_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IF */
|
||||
|
||||
/* Bit fields for CRYOTIMER IFS */
|
||||
#define _CRYOTIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFS */
|
||||
#define _CRYOTIMER_IFS_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFS */
|
||||
#define CRYOTIMER_IFS_PERIOD (0x1UL << 0) /**< Set PERIOD Interrupt Flag */
|
||||
#define _CRYOTIMER_IFS_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFS_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFS_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFS */
|
||||
#define CRYOTIMER_IFS_PERIOD_DEFAULT (_CRYOTIMER_IFS_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFS */
|
||||
|
||||
/* Bit fields for CRYOTIMER IFC */
|
||||
#define _CRYOTIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IFC */
|
||||
#define _CRYOTIMER_IFC_MASK 0x00000001UL /**< Mask for CRYOTIMER_IFC */
|
||||
#define CRYOTIMER_IFC_PERIOD (0x1UL << 0) /**< Clear PERIOD Interrupt Flag */
|
||||
#define _CRYOTIMER_IFC_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFC_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IFC_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IFC */
|
||||
#define CRYOTIMER_IFC_PERIOD_DEFAULT (_CRYOTIMER_IFC_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IFC */
|
||||
|
||||
/* Bit fields for CRYOTIMER IEN */
|
||||
#define _CRYOTIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for CRYOTIMER_IEN */
|
||||
#define _CRYOTIMER_IEN_MASK 0x00000001UL /**< Mask for CRYOTIMER_IEN */
|
||||
#define CRYOTIMER_IEN_PERIOD (0x1UL << 0) /**< PERIOD Interrupt Enable */
|
||||
#define _CRYOTIMER_IEN_PERIOD_SHIFT 0 /**< Shift value for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IEN_PERIOD_MASK 0x1UL /**< Bit mask for CRYOTIMER_PERIOD */
|
||||
#define _CRYOTIMER_IEN_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CRYOTIMER_IEN */
|
||||
#define CRYOTIMER_IEN_PERIOD_DEFAULT (_CRYOTIMER_IEN_PERIOD_DEFAULT << 0) /**< Shifted mode DEFAULT for CRYOTIMER_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_CRYOTIMER */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1218
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h
vendored
Normal file
1218
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_crypto.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1010
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h
vendored
Normal file
1010
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_csen.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1798
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h
vendored
Normal file
1798
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_devinfo.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
64
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h
vendored
Normal file
64
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dma_descriptor.h
vendored
Normal file
@ -0,0 +1,64 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_DMA_DESCRIPTOR register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_DMA_DESCRIPTOR DMA Descriptor
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/** DMA_DESCRIPTOR Register Declaration */
|
||||
typedef struct {
|
||||
/* Note! Use of double __IOM (volatile) qualifier to ensure that both */
|
||||
/* pointer and referenced memory are declared volatile. */
|
||||
__IOM uint32_t CTRL; /**< DMA control register */
|
||||
__IOM void * __IOM SRC; /**< DMA source address */
|
||||
__IOM void * __IOM DST; /**< DMA destination address */
|
||||
__IOM void * __IOM LINK; /**< DMA link address */
|
||||
} DMA_DESCRIPTOR_TypeDef; /**< @} */
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
171
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h
vendored
Normal file
171
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_dmareq.h
vendored
Normal file
@ -0,0 +1,171 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_DMAREQ register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_DMAREQ DMAREQ
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_DMAREQ_BitFields DMAREQ Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
#define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
|
||||
#define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
|
||||
#define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
|
||||
#define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
|
||||
#define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) /**< DMA channel select for ADC1_SINGLE */
|
||||
#define DMAREQ_ADC1_SCAN ((9 << 16) + 1) /**< DMA channel select for ADC1_SCAN */
|
||||
#define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
|
||||
#define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
|
||||
#define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
|
||||
#define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
|
||||
#define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
|
||||
#define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
|
||||
#define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
|
||||
#define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
|
||||
#define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
|
||||
#define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
|
||||
#define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
|
||||
#define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
|
||||
#define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
|
||||
#define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
|
||||
#define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
|
||||
#define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
|
||||
#define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */
|
||||
#define DMAREQ_USART4_TXBL ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */
|
||||
#define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */
|
||||
#define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */
|
||||
#define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */
|
||||
#define DMAREQ_USART5_RXDATAV ((17 << 16) + 0) /**< DMA channel select for USART5_RXDATAV */
|
||||
#define DMAREQ_USART5_TXBL ((17 << 16) + 1) /**< DMA channel select for USART5_TXBL */
|
||||
#define DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for USART5_TXEMPTY */
|
||||
#define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
|
||||
#define DMAREQ_UART0_TXBL ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */
|
||||
#define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
|
||||
#define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
|
||||
#define DMAREQ_UART1_TXBL ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */
|
||||
#define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
|
||||
#define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
|
||||
#define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
|
||||
#define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
|
||||
#define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
|
||||
#define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
|
||||
#define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
|
||||
#define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
|
||||
#define DMAREQ_I2C0_TXBL ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
|
||||
#define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
|
||||
#define DMAREQ_I2C1_TXBL ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
|
||||
#define DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) /**< DMA channel select for I2C2_RXDATAV */
|
||||
#define DMAREQ_I2C2_TXBL ((24 << 16) + 1) /**< DMA channel select for I2C2_TXBL */
|
||||
#define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
|
||||
#define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
|
||||
#define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
|
||||
#define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
|
||||
#define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
|
||||
#define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
|
||||
#define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
|
||||
#define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
|
||||
#define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
|
||||
#define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
|
||||
#define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
|
||||
#define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
|
||||
#define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
|
||||
#define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
|
||||
#define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
|
||||
#define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
|
||||
#define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
|
||||
#define DMAREQ_TIMER4_UFOF ((29 << 16) + 0) /**< DMA channel select for TIMER4_UFOF */
|
||||
#define DMAREQ_TIMER4_CC0 ((29 << 16) + 1) /**< DMA channel select for TIMER4_CC0 */
|
||||
#define DMAREQ_TIMER4_CC1 ((29 << 16) + 2) /**< DMA channel select for TIMER4_CC1 */
|
||||
#define DMAREQ_TIMER4_CC2 ((29 << 16) + 3) /**< DMA channel select for TIMER4_CC2 */
|
||||
#define DMAREQ_TIMER5_UFOF ((30 << 16) + 0) /**< DMA channel select for TIMER5_UFOF */
|
||||
#define DMAREQ_TIMER5_CC0 ((30 << 16) + 1) /**< DMA channel select for TIMER5_CC0 */
|
||||
#define DMAREQ_TIMER5_CC1 ((30 << 16) + 2) /**< DMA channel select for TIMER5_CC1 */
|
||||
#define DMAREQ_TIMER5_CC2 ((30 << 16) + 3) /**< DMA channel select for TIMER5_CC2 */
|
||||
#define DMAREQ_TIMER6_UFOF ((31 << 16) + 0) /**< DMA channel select for TIMER6_UFOF */
|
||||
#define DMAREQ_TIMER6_CC0 ((31 << 16) + 1) /**< DMA channel select for TIMER6_CC0 */
|
||||
#define DMAREQ_TIMER6_CC1 ((31 << 16) + 2) /**< DMA channel select for TIMER6_CC1 */
|
||||
#define DMAREQ_TIMER6_CC2 ((31 << 16) + 3) /**< DMA channel select for TIMER6_CC2 */
|
||||
#define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
|
||||
#define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
|
||||
#define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
|
||||
#define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
|
||||
#define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
|
||||
#define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
|
||||
#define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
|
||||
#define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
|
||||
#define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
|
||||
#define DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) /**< DMA channel select for WTIMER2_UFOF */
|
||||
#define DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) /**< DMA channel select for WTIMER2_CC0 */
|
||||
#define DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) /**< DMA channel select for WTIMER2_CC1 */
|
||||
#define DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) /**< DMA channel select for WTIMER2_CC2 */
|
||||
#define DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) /**< DMA channel select for WTIMER3_UFOF */
|
||||
#define DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) /**< DMA channel select for WTIMER3_CC0 */
|
||||
#define DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) /**< DMA channel select for WTIMER3_CC1 */
|
||||
#define DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) /**< DMA channel select for WTIMER3_CC2 */
|
||||
#define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
|
||||
#define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
|
||||
#define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
|
||||
#define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
|
||||
#define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
|
||||
#define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
|
||||
#define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
|
||||
#define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
|
||||
#define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
|
||||
#define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
|
||||
#define DMAREQ_EBI_VSYNC ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */
|
||||
#define DMAREQ_EBI_HSYNC ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */
|
||||
#define DMAREQ_CSEN_DATA ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */
|
||||
#define DMAREQ_CSEN_BSLN ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
|
||||
#define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_DMAREQ */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1712
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h
vendored
Normal file
1712
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ebi.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
1978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h
vendored
Normal file
1978
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_emu.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
2365
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h
vendored
Normal file
2365
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_eth.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
797
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h
vendored
Normal file
797
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_etm.h
vendored
Normal file
@ -0,0 +1,797 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_ETM register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_ETM ETM
|
||||
* @{
|
||||
* @brief EFM32GG11B_ETM Register Declaration
|
||||
******************************************************************************/
|
||||
/** ETM Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t ETMCR; /**< Main Control Register */
|
||||
__IM uint32_t ETMCCR; /**< Configuration Code Register */
|
||||
__IOM uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSR; /**< ETM Status Register */
|
||||
__IM uint32_t ETMSCR; /**< ETM System Configuration Register */
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */
|
||||
__IOM uint32_t ETMTECR1; /**< ETM Trace control Register */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */
|
||||
uint32_t RESERVED3[68U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */
|
||||
uint32_t RESERVED4[39U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */
|
||||
__IM uint32_t ETMIDR; /**< ID Register */
|
||||
__IM uint32_t ETMCCER; /**< Configuration Code Extension Register */
|
||||
uint32_t RESERVED5[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */
|
||||
uint32_t RESERVED6[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTSEVR; /**< Timestamp Event Register */
|
||||
uint32_t RESERVED7[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */
|
||||
uint32_t RESERVED8[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMIDR2; /**< ETM ID Register 2 */
|
||||
uint32_t RESERVED9[66U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMPDSR; /**< Device Power-down Status Register */
|
||||
uint32_t RESERVED10[754U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */
|
||||
uint32_t RESERVED11[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */
|
||||
uint32_t RESERVED12[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */
|
||||
uint32_t RESERVED13[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */
|
||||
uint32_t RESERVED14[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMITCTRL; /**< ETM Integration Control Register */
|
||||
uint32_t RESERVED15[39U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */
|
||||
__IOM uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */
|
||||
uint32_t RESERVED16[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ETMLAR; /**< ETM Lock Access Register */
|
||||
__IM uint32_t ETMLSR; /**< Lock Status Register */
|
||||
__IM uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */
|
||||
uint32_t RESERVED17[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */
|
||||
__IM uint32_t ETMPIDR4; /**< Peripheral ID4 Register */
|
||||
__OM uint32_t ETMPIDR5; /**< Peripheral ID5 Register */
|
||||
__OM uint32_t ETMPIDR6; /**< Peripheral ID6 Register */
|
||||
__OM uint32_t ETMPIDR7; /**< Peripheral ID7 Register */
|
||||
__IM uint32_t ETMPIDR0; /**< Peripheral ID0 Register */
|
||||
__IM uint32_t ETMPIDR1; /**< Peripheral ID1 Register */
|
||||
__IM uint32_t ETMPIDR2; /**< Peripheral ID2 Register */
|
||||
__IM uint32_t ETMPIDR3; /**< Peripheral ID3 Register */
|
||||
__IM uint32_t ETMCIDR0; /**< Component ID0 Register */
|
||||
__IM uint32_t ETMCIDR1; /**< Component ID1 Register */
|
||||
__IM uint32_t ETMCIDR2; /**< Component ID2 Register */
|
||||
__IM uint32_t ETMCIDR3; /**< Component ID3 Register */
|
||||
} ETM_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_ETM
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_ETM_BitFields ETM Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for ETM ETMCR */
|
||||
#define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */
|
||||
#define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */
|
||||
#define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */
|
||||
#define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */
|
||||
#define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */
|
||||
#define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */
|
||||
#define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */
|
||||
#define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */
|
||||
#define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */
|
||||
#define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */
|
||||
#define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */
|
||||
#define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */
|
||||
#define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */
|
||||
#define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */
|
||||
#define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */
|
||||
#define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */
|
||||
#define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */
|
||||
#define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */
|
||||
#define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */
|
||||
#define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */
|
||||
#define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */
|
||||
#define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */
|
||||
#define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */
|
||||
#define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */
|
||||
#define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */
|
||||
#define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */
|
||||
#define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */
|
||||
|
||||
/* Bit fields for ETM ETMCCR */
|
||||
#define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */
|
||||
#define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */
|
||||
#define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */
|
||||
#define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */
|
||||
#define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */
|
||||
#define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */
|
||||
#define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */
|
||||
#define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */
|
||||
#define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */
|
||||
#define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */
|
||||
#define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */
|
||||
#define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */
|
||||
#define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */
|
||||
#define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */
|
||||
#define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */
|
||||
#define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */
|
||||
#define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */
|
||||
#define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */
|
||||
#define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */
|
||||
#define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */
|
||||
#define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */
|
||||
#define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */
|
||||
#define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */
|
||||
|
||||
/* Bit fields for ETM ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
|
||||
#define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
|
||||
#define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
|
||||
#define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
|
||||
#define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */
|
||||
#define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */
|
||||
#define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */
|
||||
|
||||
/* Bit fields for ETM ETMSR */
|
||||
#define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */
|
||||
#define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */
|
||||
#define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */
|
||||
#define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */
|
||||
#define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */
|
||||
#define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */
|
||||
#define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */
|
||||
#define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */
|
||||
#define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */
|
||||
#define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */
|
||||
#define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */
|
||||
#define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */
|
||||
#define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */
|
||||
|
||||
/* Bit fields for ETM ETMSCR */
|
||||
#define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */
|
||||
#define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */
|
||||
#define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */
|
||||
#define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */
|
||||
#define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */
|
||||
#define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */
|
||||
#define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */
|
||||
#define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */
|
||||
#define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */
|
||||
#define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */
|
||||
#define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */
|
||||
#define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */
|
||||
#define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */
|
||||
#define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */
|
||||
#define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */
|
||||
|
||||
/* Bit fields for ETM ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */
|
||||
#define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */
|
||||
#define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */
|
||||
#define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */
|
||||
#define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */
|
||||
#define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */
|
||||
#define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */
|
||||
|
||||
/* Bit fields for ETM ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */
|
||||
#define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */
|
||||
#define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */
|
||||
#define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */
|
||||
#define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */
|
||||
#define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */
|
||||
#define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */
|
||||
#define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */
|
||||
#define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */
|
||||
#define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */
|
||||
|
||||
/* Bit fields for ETM ETMFFLR */
|
||||
#define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */
|
||||
#define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */
|
||||
#define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */
|
||||
#define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */
|
||||
#define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */
|
||||
#define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */
|
||||
|
||||
/* Bit fields for ETM ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */
|
||||
#define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */
|
||||
#define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */
|
||||
|
||||
/* Bit fields for ETM ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */
|
||||
#define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */
|
||||
#define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */
|
||||
#define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */
|
||||
#define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */
|
||||
|
||||
/* Bit fields for ETM ETMIDR */
|
||||
#define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */
|
||||
#define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */
|
||||
#define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */
|
||||
#define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */
|
||||
#define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */
|
||||
#define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */
|
||||
#define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */
|
||||
#define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */
|
||||
#define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */
|
||||
#define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */
|
||||
#define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */
|
||||
#define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */
|
||||
#define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */
|
||||
#define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */
|
||||
#define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */
|
||||
#define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */
|
||||
#define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */
|
||||
#define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */
|
||||
#define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */
|
||||
#define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
#define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */
|
||||
#define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */
|
||||
#define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */
|
||||
#define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */
|
||||
|
||||
/* Bit fields for ETM ETMCCER */
|
||||
#define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */
|
||||
#define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */
|
||||
#define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */
|
||||
#define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */
|
||||
#define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */
|
||||
#define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */
|
||||
#define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */
|
||||
#define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */
|
||||
#define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */
|
||||
#define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */
|
||||
#define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */
|
||||
#define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */
|
||||
#define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */
|
||||
#define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */
|
||||
#define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */
|
||||
#define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */
|
||||
#define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */
|
||||
#define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */
|
||||
#define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */
|
||||
#define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */
|
||||
#define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */
|
||||
#define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */
|
||||
#define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */
|
||||
#define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */
|
||||
#define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */
|
||||
#define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */
|
||||
#define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */
|
||||
#define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */
|
||||
#define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */
|
||||
#define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */
|
||||
|
||||
/* Bit fields for ETM ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */
|
||||
#define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */
|
||||
#define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */
|
||||
#define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */
|
||||
|
||||
/* Bit fields for ETM ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */
|
||||
#define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */
|
||||
#define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */
|
||||
#define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */
|
||||
#define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */
|
||||
|
||||
/* Bit fields for ETM ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */
|
||||
#define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */
|
||||
#define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */
|
||||
|
||||
/* Bit fields for ETM ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */
|
||||
#define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */
|
||||
#define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */
|
||||
#define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */
|
||||
#define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */
|
||||
#define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */
|
||||
#define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */
|
||||
#define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */
|
||||
#define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMPDSR */
|
||||
#define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */
|
||||
#define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */
|
||||
#define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */
|
||||
#define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */
|
||||
#define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */
|
||||
#define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */
|
||||
#define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */
|
||||
|
||||
/* Bit fields for ETM ETMISCIN */
|
||||
#define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */
|
||||
#define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */
|
||||
#define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */
|
||||
#define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */
|
||||
#define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */
|
||||
#define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */
|
||||
#define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */
|
||||
|
||||
/* Bit fields for ETM ITTRIGOUT */
|
||||
#define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */
|
||||
#define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */
|
||||
#define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */
|
||||
#define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */
|
||||
#define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */
|
||||
|
||||
/* Bit fields for ETM ETMITATBCTR2 */
|
||||
#define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */
|
||||
#define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */
|
||||
#define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */
|
||||
#define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */
|
||||
#define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */
|
||||
|
||||
/* Bit fields for ETM ETMITATBCTR0 */
|
||||
#define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */
|
||||
#define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */
|
||||
#define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */
|
||||
#define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */
|
||||
#define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */
|
||||
|
||||
/* Bit fields for ETM ETMITCTRL */
|
||||
#define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */
|
||||
#define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */
|
||||
#define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */
|
||||
#define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */
|
||||
#define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */
|
||||
#define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */
|
||||
#define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */
|
||||
|
||||
/* Bit fields for ETM ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */
|
||||
#define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */
|
||||
#define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */
|
||||
|
||||
/* Bit fields for ETM ETMCLAIMCLR */
|
||||
#define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */
|
||||
#define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */
|
||||
#define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */
|
||||
#define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */
|
||||
#define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */
|
||||
|
||||
/* Bit fields for ETM ETMLAR */
|
||||
#define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */
|
||||
#define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */
|
||||
#define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */
|
||||
#define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */
|
||||
#define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */
|
||||
#define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */
|
||||
#define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */
|
||||
|
||||
/* Bit fields for ETM ETMLSR */
|
||||
#define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */
|
||||
#define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */
|
||||
#define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */
|
||||
#define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */
|
||||
#define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */
|
||||
#define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */
|
||||
#define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */
|
||||
#define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */
|
||||
#define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */
|
||||
|
||||
/* Bit fields for ETM ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */
|
||||
#define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
#define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */
|
||||
|
||||
/* Bit fields for ETM ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */
|
||||
#define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */
|
||||
#define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
#define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */
|
||||
#define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */
|
||||
#define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */
|
||||
#define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */
|
||||
#define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR5 */
|
||||
#define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */
|
||||
#define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR6 */
|
||||
#define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */
|
||||
#define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR7 */
|
||||
#define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */
|
||||
#define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_RESETVALUE 0x00000025UL /**< Default value for ETM_ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000025UL /**< Mode DEFAULT for ETM_ETMPIDR0 */
|
||||
#define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */
|
||||
#define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */
|
||||
#define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_RESETVALUE 0x0000000BUL /**< Default value for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */
|
||||
#define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */
|
||||
#define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */
|
||||
#define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */
|
||||
#define _ETM_ETMPIDR2_REV_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR2 */
|
||||
#define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */
|
||||
#define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */
|
||||
#define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */
|
||||
#define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */
|
||||
#define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */
|
||||
#define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */
|
||||
#define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */
|
||||
#define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */
|
||||
#define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */
|
||||
#define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */
|
||||
#define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */
|
||||
|
||||
/* Bit fields for ETM ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */
|
||||
#define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */
|
||||
#define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */
|
||||
#define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_ETM */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
208
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h
vendored
Normal file
208
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_fpueh.h
vendored
Normal file
@ -0,0 +1,208 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_FPUEH register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_FPUEH FPUEH
|
||||
* @{
|
||||
* @brief EFM32GG11B_FPUEH Register Declaration
|
||||
******************************************************************************/
|
||||
/** FPUEH Register Declaration */
|
||||
typedef struct {
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
} FPUEH_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_FPUEH
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_FPUEH_BitFields FPUEH Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for FPUEH IF */
|
||||
#define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
|
||||
#define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
|
||||
#define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
|
||||
#define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
|
||||
#define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
|
||||
#define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
|
||||
#define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
|
||||
#define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
|
||||
#define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
|
||||
|
||||
/* Bit fields for FPUEH IFS */
|
||||
#define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
|
||||
#define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
|
||||
#define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
|
||||
#define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
|
||||
|
||||
/* Bit fields for FPUEH IFC */
|
||||
#define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
|
||||
#define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
|
||||
#define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
|
||||
#define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
|
||||
|
||||
/* Bit fields for FPUEH IEN */
|
||||
#define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
|
||||
#define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
|
||||
#define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
|
||||
#define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
|
||||
#define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
|
||||
#define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
|
||||
#define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
|
||||
#define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
|
||||
#define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
|
||||
#define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
|
||||
#define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
|
||||
#define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
|
||||
#define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
|
||||
#define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
|
||||
#define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
|
||||
#define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_FPUEH */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
201
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h
vendored
Normal file
201
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpcrc.h
vendored
Normal file
@ -0,0 +1,201 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_GPCRC register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_GPCRC GPCRC
|
||||
* @{
|
||||
* @brief EFM32GG11B_GPCRC Register Declaration
|
||||
******************************************************************************/
|
||||
/** GPCRC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IOM uint32_t INIT; /**< CRC Init Value */
|
||||
__IOM uint32_t POLY; /**< CRC Polynomial Value */
|
||||
__IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */
|
||||
__IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */
|
||||
__IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */
|
||||
__IM uint32_t DATA; /**< CRC Data Register */
|
||||
__IM uint32_t DATAREV; /**< CRC Data Reverse Register */
|
||||
__IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */
|
||||
} GPCRC_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_GPCRC
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_GPCRC_BitFields GPCRC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for GPCRC CTRL */
|
||||
#define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_MASK 0x00002711UL /**< Mask for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN (0x1UL << 0) /**< CRC Functionality Enable */
|
||||
#define _GPCRC_CTRL_EN_SHIFT 0 /**< Shift value for GPCRC_EN */
|
||||
#define _GPCRC_CTRL_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */
|
||||
#define _GPCRC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_DEFAULT (_GPCRC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_DISABLE (_GPCRC_CTRL_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_EN_ENABLE (_GPCRC_CTRL_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */
|
||||
#define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */
|
||||
#define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */
|
||||
#define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_POLYSEL_16 0x00000001UL /**< Mode 16 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_POLYSEL_16 (_GPCRC_CTRL_POLYSEL_16 << 4) /**< Shifted mode 16 for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */
|
||||
#define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */
|
||||
#define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */
|
||||
#define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */
|
||||
#define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */
|
||||
#define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */
|
||||
#define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */
|
||||
#define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */
|
||||
#define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */
|
||||
#define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */
|
||||
#define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */
|
||||
#define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */
|
||||
|
||||
/* Bit fields for GPCRC CMD */
|
||||
#define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */
|
||||
#define _GPCRC_CMD_MASK 0x00000001UL /**< Mask for GPCRC_CMD */
|
||||
#define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */
|
||||
#define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
|
||||
#define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */
|
||||
#define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */
|
||||
#define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */
|
||||
|
||||
/* Bit fields for GPCRC INIT */
|
||||
#define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */
|
||||
#define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */
|
||||
#define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */
|
||||
|
||||
/* Bit fields for GPCRC POLY */
|
||||
#define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */
|
||||
#define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */
|
||||
#define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */
|
||||
#define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */
|
||||
#define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */
|
||||
#define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */
|
||||
#define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD */
|
||||
|
||||
/* Bit fields for GPCRC INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */
|
||||
#define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */
|
||||
#define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE */
|
||||
|
||||
/* Bit fields for GPCRC DATA */
|
||||
#define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */
|
||||
#define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */
|
||||
#define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */
|
||||
|
||||
/* Bit fields for GPCRC DATAREV */
|
||||
#define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */
|
||||
#define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */
|
||||
#define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */
|
||||
|
||||
/* Bit fields for GPCRC DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */
|
||||
#define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
#define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_GPCRC */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1557
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h
vendored
Normal file
1557
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
68
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h
vendored
Normal file
68
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_gpio_p.h
vendored
Normal file
@ -0,0 +1,68 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_GPIO_P register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief GPIO_P GPIO P Register
|
||||
* @ingroup EFM32GG11B_GPIO
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Port Control Register */
|
||||
__IOM uint32_t MODEL; /**< Port Pin Mode Low Register */
|
||||
__IOM uint32_t MODEH; /**< Port Pin Mode High Register */
|
||||
__IOM uint32_t DOUT; /**< Port Data Out Register */
|
||||
uint32_t RESERVED0[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DOUTTGL; /**< Port Data Out Toggle Register */
|
||||
__IM uint32_t DIN; /**< Port Data in Register */
|
||||
__IOM uint32_t PINLOCKN; /**< Port Unlocked Pins Register */
|
||||
uint32_t RESERVED1[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t OVTDIS; /**< Over Voltage Disable for All Modes */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved future */
|
||||
} GPIO_P_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
841
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h
vendored
Normal file
841
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_i2c.h
vendored
Normal file
@ -0,0 +1,841 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_I2C register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_I2C I2C
|
||||
* @{
|
||||
* @brief EFM32GG11B_I2C Register Declaration
|
||||
******************************************************************************/
|
||||
/** I2C Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATE; /**< State Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Division Register */
|
||||
__IOM uint32_t SADDR; /**< Slave Address Register */
|
||||
__IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
|
||||
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__IM uint32_t RXDOUBLE; /**< Receive Buffer Double Data Register */
|
||||
__IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
|
||||
__IM uint32_t RXDOUBLEP; /**< Receive Buffer Double Data Peek Register */
|
||||
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__IOM uint32_t TXDOUBLE; /**< Transmit Buffer Double Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
} I2C_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_I2C
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_I2C_BitFields I2C Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for I2C CTRL */
|
||||
#define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
|
||||
#define _I2C_CTRL_MASK 0x0007B3FFUL /**< Mask for I2C_CTRL */
|
||||
#define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
|
||||
#define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
|
||||
#define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
|
||||
#define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
|
||||
#define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
|
||||
#define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
|
||||
#define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
|
||||
#define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP When Empty */
|
||||
#define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
|
||||
#define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
|
||||
#define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
|
||||
#define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
|
||||
#define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
|
||||
#define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
|
||||
#define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
|
||||
#define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL (0x1UL << 7) /**< TX Buffer Interrupt Level */
|
||||
#define _I2C_CTRL_TXBIL_SHIFT 7 /**< Shift value for I2C_TXBIL */
|
||||
#define _I2C_CTRL_TXBIL_MASK 0x80UL /**< Bit mask for I2C_TXBIL */
|
||||
#define _I2C_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for I2C_CTRL */
|
||||
#define _I2C_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_DEFAULT (_I2C_CTRL_TXBIL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_EMPTY (_I2C_CTRL_TXBIL_EMPTY << 7) /**< Shifted mode EMPTY for I2C_CTRL */
|
||||
#define I2C_CTRL_TXBIL_HALFFULL (_I2C_CTRL_TXBIL_HALFFULL << 7) /**< Shifted mode HALFFULL for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
|
||||
#define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
|
||||
#define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
|
||||
#define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_320PCC 0x00000004UL /**< Mode 320PCC for I2C_CTRL */
|
||||
#define _I2C_CTRL_CLTO_1024PCC 0x00000005UL /**< Mode 1024PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_320PCC (_I2C_CTRL_CLTO_320PCC << 16) /**< Shifted mode 320PCC for I2C_CTRL */
|
||||
#define I2C_CTRL_CLTO_1024PCC (_I2C_CTRL_CLTO_1024PCC << 16) /**< Shifted mode 1024PCC for I2C_CTRL */
|
||||
|
||||
/* Bit fields for I2C CMD */
|
||||
#define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
|
||||
#define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
|
||||
#define I2C_CMD_START (0x1UL << 0) /**< Send Start Condition */
|
||||
#define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP (0x1UL << 1) /**< Send Stop Condition */
|
||||
#define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
|
||||
#define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
|
||||
#define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
|
||||
#define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT (0x1UL << 4) /**< Continue Transmission */
|
||||
#define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
|
||||
#define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT (0x1UL << 5) /**< Abort Transmission */
|
||||
#define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
|
||||
#define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
|
||||
#define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
|
||||
#define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
|
||||
#define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
|
||||
#define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
|
||||
#define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
|
||||
|
||||
/* Bit fields for I2C STATE */
|
||||
#define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
|
||||
#define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
|
||||
#define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
|
||||
#define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
|
||||
#define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
|
||||
#define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
|
||||
#define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
|
||||
#define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
|
||||
#define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
|
||||
#define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
|
||||
#define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
|
||||
#define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
|
||||
#define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
|
||||
#define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
|
||||
#define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
|
||||
#define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
|
||||
#define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
|
||||
|
||||
/* Bit fields for I2C STATUS */
|
||||
#define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
|
||||
#define _I2C_STATUS_MASK 0x000003FFUL /**< Mask for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
|
||||
#define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
|
||||
#define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
|
||||
#define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
|
||||
#define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
|
||||
#define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
|
||||
#define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
|
||||
#define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
|
||||
#define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending Continue */
|
||||
#define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
|
||||
#define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending Abort */
|
||||
#define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
|
||||
#define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
|
||||
#define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
|
||||
#define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
|
||||
#define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXFULL (0x1UL << 9) /**< RX FIFO Full */
|
||||
#define _I2C_STATUS_RXFULL_SHIFT 9 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_STATUS_RXFULL_MASK 0x200UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
|
||||
#define I2C_STATUS_RXFULL_DEFAULT (_I2C_STATUS_RXFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_STATUS */
|
||||
|
||||
/* Bit fields for I2C CLKDIV */
|
||||
#define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
|
||||
#define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
|
||||
#define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
|
||||
#define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
|
||||
|
||||
/* Bit fields for I2C SADDR */
|
||||
#define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
|
||||
#define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
|
||||
#define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
|
||||
#define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
|
||||
|
||||
/* Bit fields for I2C SADDRMASK */
|
||||
#define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
|
||||
#define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
|
||||
#define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
|
||||
#define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
|
||||
|
||||
/* Bit fields for I2C RXDATA */
|
||||
#define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
|
||||
#define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
|
||||
#define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
|
||||
|
||||
/* Bit fields for I2C RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for I2C_RXDATA0 */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for I2C_RXDATA0 */
|
||||
#define _I2C_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define I2C_RXDOUBLE_RXDATA0_DEFAULT (_I2C_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for I2C_RXDATA1 */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATA1 */
|
||||
#define _I2C_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLE */
|
||||
#define I2C_RXDOUBLE_RXDATA1_DEFAULT (_I2C_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLE */
|
||||
|
||||
/* Bit fields for I2C RXDATAP */
|
||||
#define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
|
||||
#define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
|
||||
#define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
|
||||
|
||||
/* Bit fields for I2C RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_MASK 0x0000FFFFUL /**< Mask for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_SHIFT 0 /**< Shift value for I2C_RXDATAP0 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP0 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define I2C_RXDOUBLEP_RXDATAP0_DEFAULT (_I2C_RXDOUBLEP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_SHIFT 8 /**< Shift value for I2C_RXDATAP1 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_MASK 0xFF00UL /**< Bit mask for I2C_RXDATAP1 */
|
||||
#define _I2C_RXDOUBLEP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDOUBLEP */
|
||||
#define I2C_RXDOUBLEP_RXDATAP1_DEFAULT (_I2C_RXDOUBLEP_RXDATAP1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_RXDOUBLEP */
|
||||
|
||||
/* Bit fields for I2C TXDATA */
|
||||
#define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
|
||||
#define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
|
||||
#define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
|
||||
|
||||
/* Bit fields for I2C TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for I2C_TXDATA0 */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for I2C_TXDATA0 */
|
||||
#define _I2C_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define I2C_TXDOUBLE_TXDATA0_DEFAULT (_I2C_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for I2C_TXDATA1 */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for I2C_TXDATA1 */
|
||||
#define _I2C_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDOUBLE */
|
||||
#define I2C_TXDOUBLE_TXDATA1_DEFAULT (_I2C_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_TXDOUBLE */
|
||||
|
||||
/* Bit fields for I2C IF */
|
||||
#define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
|
||||
#define _I2C_IF_MASK 0x0007FFFFUL /**< Mask for I2C_IF */
|
||||
#define I2C_IF_START (0x1UL << 0) /**< START Condition Interrupt Flag */
|
||||
#define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START Condition Interrupt Flag */
|
||||
#define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
|
||||
#define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
|
||||
#define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
|
||||
#define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
|
||||
#define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
|
||||
#define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
|
||||
#define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
|
||||
#define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
|
||||
#define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
|
||||
#define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
|
||||
#define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
|
||||
#define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
|
||||
#define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP Condition Interrupt Flag */
|
||||
#define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXFULL (0x1UL << 17) /**< Receive Buffer Full Interrupt Flag */
|
||||
#define _I2C_IF_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IF_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_RXFULL_DEFAULT (_I2C_IF_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLERR (0x1UL << 18) /**< Clock Low Error Interrupt Flag */
|
||||
#define _I2C_IF_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IF_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IF_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
|
||||
#define I2C_IF_CLERR_DEFAULT (_I2C_IF_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IF */
|
||||
|
||||
/* Bit fields for I2C IFS */
|
||||
#define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
|
||||
#define _I2C_IFS_MASK 0x0007FFCFUL /**< Mask for I2C_IFS */
|
||||
#define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
|
||||
#define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART (0x1UL << 1) /**< Set RSTART Interrupt Flag */
|
||||
#define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR (0x1UL << 2) /**< Set ADDR Interrupt Flag */
|
||||
#define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC (0x1UL << 3) /**< Set TXC Interrupt Flag */
|
||||
#define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK (0x1UL << 6) /**< Set ACK Interrupt Flag */
|
||||
#define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK (0x1UL << 7) /**< Set NACK Interrupt Flag */
|
||||
#define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set ARBLOST Interrupt Flag */
|
||||
#define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR (0x1UL << 10) /**< Set BUSERR Interrupt Flag */
|
||||
#define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set BUSHOLD Interrupt Flag */
|
||||
#define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF (0x1UL << 12) /**< Set TXOF Interrupt Flag */
|
||||
#define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF (0x1UL << 13) /**< Set RXUF Interrupt Flag */
|
||||
#define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO (0x1UL << 14) /**< Set BITO Interrupt Flag */
|
||||
#define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO (0x1UL << 15) /**< Set CLTO Interrupt Flag */
|
||||
#define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
|
||||
#define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXFULL (0x1UL << 17) /**< Set RXFULL Interrupt Flag */
|
||||
#define _I2C_IFS_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IFS_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_RXFULL_DEFAULT (_I2C_IFS_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLERR (0x1UL << 18) /**< Set CLERR Interrupt Flag */
|
||||
#define _I2C_IFS_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IFS_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IFS_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
|
||||
#define I2C_IFS_CLERR_DEFAULT (_I2C_IFS_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFS */
|
||||
|
||||
/* Bit fields for I2C IFC */
|
||||
#define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
|
||||
#define _I2C_IFC_MASK 0x0007FFCFUL /**< Mask for I2C_IFC */
|
||||
#define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
|
||||
#define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART (0x1UL << 1) /**< Clear RSTART Interrupt Flag */
|
||||
#define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR (0x1UL << 2) /**< Clear ADDR Interrupt Flag */
|
||||
#define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC (0x1UL << 3) /**< Clear TXC Interrupt Flag */
|
||||
#define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK (0x1UL << 6) /**< Clear ACK Interrupt Flag */
|
||||
#define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK (0x1UL << 7) /**< Clear NACK Interrupt Flag */
|
||||
#define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear ARBLOST Interrupt Flag */
|
||||
#define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear BUSERR Interrupt Flag */
|
||||
#define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear BUSHOLD Interrupt Flag */
|
||||
#define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF (0x1UL << 12) /**< Clear TXOF Interrupt Flag */
|
||||
#define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF (0x1UL << 13) /**< Clear RXUF Interrupt Flag */
|
||||
#define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO (0x1UL << 14) /**< Clear BITO Interrupt Flag */
|
||||
#define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO (0x1UL << 15) /**< Clear CLTO Interrupt Flag */
|
||||
#define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
|
||||
#define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXFULL (0x1UL << 17) /**< Clear RXFULL Interrupt Flag */
|
||||
#define _I2C_IFC_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IFC_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_RXFULL_DEFAULT (_I2C_IFC_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLERR (0x1UL << 18) /**< Clear CLERR Interrupt Flag */
|
||||
#define _I2C_IFC_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IFC_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IFC_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
|
||||
#define I2C_IFC_CLERR_DEFAULT (_I2C_IFC_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IFC */
|
||||
|
||||
/* Bit fields for I2C IEN */
|
||||
#define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
|
||||
#define _I2C_IEN_MASK 0x0007FFFFUL /**< Mask for I2C_IEN */
|
||||
#define I2C_IEN_START (0x1UL << 0) /**< START Interrupt Enable */
|
||||
#define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
|
||||
#define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
|
||||
#define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART (0x1UL << 1) /**< RSTART Interrupt Enable */
|
||||
#define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
|
||||
#define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR (0x1UL << 2) /**< ADDR Interrupt Enable */
|
||||
#define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
|
||||
#define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC (0x1UL << 3) /**< TXC Interrupt Enable */
|
||||
#define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
|
||||
#define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL (0x1UL << 4) /**< TXBL Interrupt Enable */
|
||||
#define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
|
||||
#define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV (0x1UL << 5) /**< RXDATAV Interrupt Enable */
|
||||
#define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
|
||||
#define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK (0x1UL << 6) /**< ACK Interrupt Enable */
|
||||
#define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
|
||||
#define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK (0x1UL << 7) /**< NACK Interrupt Enable */
|
||||
#define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
|
||||
#define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
|
||||
#define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST (0x1UL << 9) /**< ARBLOST Interrupt Enable */
|
||||
#define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
|
||||
#define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR (0x1UL << 10) /**< BUSERR Interrupt Enable */
|
||||
#define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
|
||||
#define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD (0x1UL << 11) /**< BUSHOLD Interrupt Enable */
|
||||
#define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
|
||||
#define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF (0x1UL << 12) /**< TXOF Interrupt Enable */
|
||||
#define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
|
||||
#define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF (0x1UL << 13) /**< RXUF Interrupt Enable */
|
||||
#define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
|
||||
#define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO (0x1UL << 14) /**< BITO Interrupt Enable */
|
||||
#define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
|
||||
#define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO (0x1UL << 15) /**< CLTO Interrupt Enable */
|
||||
#define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
|
||||
#define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
|
||||
#define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
|
||||
#define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXFULL (0x1UL << 17) /**< RXFULL Interrupt Enable */
|
||||
#define _I2C_IEN_RXFULL_SHIFT 17 /**< Shift value for I2C_RXFULL */
|
||||
#define _I2C_IEN_RXFULL_MASK 0x20000UL /**< Bit mask for I2C_RXFULL */
|
||||
#define _I2C_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_RXFULL_DEFAULT (_I2C_IEN_RXFULL_DEFAULT << 17) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLERR (0x1UL << 18) /**< CLERR Interrupt Enable */
|
||||
#define _I2C_IEN_CLERR_SHIFT 18 /**< Shift value for I2C_CLERR */
|
||||
#define _I2C_IEN_CLERR_MASK 0x40000UL /**< Bit mask for I2C_CLERR */
|
||||
#define _I2C_IEN_CLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
|
||||
#define I2C_IEN_CLERR_DEFAULT (_I2C_IEN_CLERR_DEFAULT << 18) /**< Shifted mode DEFAULT for I2C_IEN */
|
||||
|
||||
/* Bit fields for I2C ROUTEPEN */
|
||||
#define _I2C_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTEPEN */
|
||||
#define _I2C_ROUTEPEN_MASK 0x00000003UL /**< Mask for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
|
||||
#define _I2C_ROUTEPEN_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SDAPEN_DEFAULT (_I2C_ROUTEPEN_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
|
||||
#define _I2C_ROUTEPEN_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTEPEN */
|
||||
#define I2C_ROUTEPEN_SCLPEN_DEFAULT (_I2C_ROUTEPEN_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTEPEN */
|
||||
|
||||
/* Bit fields for I2C ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_MASK 0x00000707UL /**< Mask for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_SHIFT 0 /**< Shift value for I2C_SDALOC */
|
||||
#define _I2C_ROUTELOC0_SDALOC_MASK 0x7UL /**< Bit mask for I2C_SDALOC */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SDALOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC0 (_I2C_ROUTELOC0_SDALOC_LOC0 << 0) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_DEFAULT (_I2C_ROUTELOC0_SDALOC_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC1 (_I2C_ROUTELOC0_SDALOC_LOC1 << 0) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC2 (_I2C_ROUTELOC0_SDALOC_LOC2 << 0) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC3 (_I2C_ROUTELOC0_SDALOC_LOC3 << 0) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC4 (_I2C_ROUTELOC0_SDALOC_LOC4 << 0) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC5 (_I2C_ROUTELOC0_SDALOC_LOC5 << 0) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC6 (_I2C_ROUTELOC0_SDALOC_LOC6 << 0) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SDALOC_LOC7 (_I2C_ROUTELOC0_SDALOC_LOC7 << 0) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_SHIFT 8 /**< Shift value for I2C_SCLLOC */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_MASK 0x700UL /**< Bit mask for I2C_SCLLOC */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define _I2C_ROUTELOC0_SCLLOC_LOC7 0x00000007UL /**< Mode LOC7 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC0 (_I2C_ROUTELOC0_SCLLOC_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_DEFAULT (_I2C_ROUTELOC0_SCLLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC1 (_I2C_ROUTELOC0_SCLLOC_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC2 (_I2C_ROUTELOC0_SCLLOC_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC3 (_I2C_ROUTELOC0_SCLLOC_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC4 (_I2C_ROUTELOC0_SCLLOC_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC5 (_I2C_ROUTELOC0_SCLLOC_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC6 (_I2C_ROUTELOC0_SCLLOC_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTELOC0 */
|
||||
#define I2C_ROUTELOC0_SCLLOC_LOC7 (_I2C_ROUTELOC0_SCLLOC_LOC7 << 8) /**< Shifted mode LOC7 for I2C_ROUTELOC0 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_I2C */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
392
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h
vendored
Normal file
392
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_idac.h
vendored
Normal file
@ -0,0 +1,392 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_IDAC register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_IDAC IDAC
|
||||
* @{
|
||||
* @brief EFM32GG11B_IDAC Register Declaration
|
||||
******************************************************************************/
|
||||
/** IDAC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CURPROG; /**< Current Programming Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t DUTYCONFIG; /**< Duty Cycle Configuration Register */
|
||||
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t APORTREQ; /**< APORT Request Status Register */
|
||||
__IM uint32_t APORTCONFLICT; /**< APORT Request Status Register */
|
||||
} IDAC_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_IDAC
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_IDAC_BitFields IDAC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for IDAC CTRL */
|
||||
#define _IDAC_CTRL_RESETVALUE 0x00000000UL /**< Default value for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_MASK 0x01FD7FFFUL /**< Mask for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EN (0x1UL << 0) /**< Current DAC Enable */
|
||||
#define _IDAC_CTRL_EN_SHIFT 0 /**< Shift value for IDAC_EN */
|
||||
#define _IDAC_CTRL_EN_MASK 0x1UL /**< Bit mask for IDAC_EN */
|
||||
#define _IDAC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EN_DEFAULT (_IDAC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_CURSINK (0x1UL << 1) /**< Current Sink Enable */
|
||||
#define _IDAC_CTRL_CURSINK_SHIFT 1 /**< Shift value for IDAC_CURSINK */
|
||||
#define _IDAC_CTRL_CURSINK_MASK 0x2UL /**< Bit mask for IDAC_CURSINK */
|
||||
#define _IDAC_CTRL_CURSINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_CURSINK_DEFAULT (_IDAC_CTRL_CURSINK_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MINOUTTRANS (0x1UL << 2) /**< Minimum Output Transition Enable */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_SHIFT 2 /**< Shift value for IDAC_MINOUTTRANS */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_MASK 0x4UL /**< Bit mask for IDAC_MINOUTTRANS */
|
||||
#define _IDAC_CTRL_MINOUTTRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MINOUTTRANS_DEFAULT (_IDAC_CTRL_MINOUTTRANS_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTEN (0x1UL << 3) /**< APORT Output Enable */
|
||||
#define _IDAC_CTRL_APORTOUTEN_SHIFT 3 /**< Shift value for IDAC_APORTOUTEN */
|
||||
#define _IDAC_CTRL_APORTOUTEN_MASK 0x8UL /**< Bit mask for IDAC_APORTOUTEN */
|
||||
#define _IDAC_CTRL_APORTOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTEN_DEFAULT (_IDAC_CTRL_APORTOUTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_SHIFT 4 /**< Shift value for IDAC_APORTOUTSEL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_MASK 0xFF0UL /**< Bit mask for IDAC_APORTOUTSEL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH0 0x00000020UL /**< Mode APORT1XCH0 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH1 0x00000021UL /**< Mode APORT1YCH1 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH2 0x00000022UL /**< Mode APORT1XCH2 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH3 0x00000023UL /**< Mode APORT1YCH3 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH4 0x00000024UL /**< Mode APORT1XCH4 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH5 0x00000025UL /**< Mode APORT1YCH5 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH6 0x00000026UL /**< Mode APORT1XCH6 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH7 0x00000027UL /**< Mode APORT1YCH7 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH8 0x00000028UL /**< Mode APORT1XCH8 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH9 0x00000029UL /**< Mode APORT1YCH9 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH10 0x0000002AUL /**< Mode APORT1XCH10 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH11 0x0000002BUL /**< Mode APORT1YCH11 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH12 0x0000002CUL /**< Mode APORT1XCH12 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH13 0x0000002DUL /**< Mode APORT1YCH13 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH14 0x0000002EUL /**< Mode APORT1XCH14 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH15 0x0000002FUL /**< Mode APORT1YCH15 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH16 0x00000030UL /**< Mode APORT1XCH16 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH17 0x00000031UL /**< Mode APORT1YCH17 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH18 0x00000032UL /**< Mode APORT1XCH18 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH19 0x00000033UL /**< Mode APORT1YCH19 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH20 0x00000034UL /**< Mode APORT1XCH20 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH21 0x00000035UL /**< Mode APORT1YCH21 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH22 0x00000036UL /**< Mode APORT1XCH22 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH23 0x00000037UL /**< Mode APORT1YCH23 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH24 0x00000038UL /**< Mode APORT1XCH24 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH25 0x00000039UL /**< Mode APORT1YCH25 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH26 0x0000003AUL /**< Mode APORT1XCH26 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH27 0x0000003BUL /**< Mode APORT1YCH27 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH28 0x0000003CUL /**< Mode APORT1XCH28 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH29 0x0000003DUL /**< Mode APORT1YCH29 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1XCH30 0x0000003EUL /**< Mode APORT1XCH30 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_APORTOUTSEL_APORT1YCH31 0x0000003FUL /**< Mode APORT1YCH31 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_DEFAULT (_IDAC_CTRL_APORTOUTSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH0 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH0 << 4) /**< Shifted mode APORT1XCH0 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH1 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH1 << 4) /**< Shifted mode APORT1YCH1 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH2 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH2 << 4) /**< Shifted mode APORT1XCH2 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH3 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH3 << 4) /**< Shifted mode APORT1YCH3 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH4 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH4 << 4) /**< Shifted mode APORT1XCH4 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH5 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH5 << 4) /**< Shifted mode APORT1YCH5 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH6 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH6 << 4) /**< Shifted mode APORT1XCH6 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH7 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH7 << 4) /**< Shifted mode APORT1YCH7 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH8 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH8 << 4) /**< Shifted mode APORT1XCH8 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH9 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH9 << 4) /**< Shifted mode APORT1YCH9 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH10 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH10 << 4) /**< Shifted mode APORT1XCH10 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH11 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH11 << 4) /**< Shifted mode APORT1YCH11 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH12 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH12 << 4) /**< Shifted mode APORT1XCH12 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH13 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH13 << 4) /**< Shifted mode APORT1YCH13 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH14 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH14 << 4) /**< Shifted mode APORT1XCH14 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH15 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH15 << 4) /**< Shifted mode APORT1YCH15 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH16 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH16 << 4) /**< Shifted mode APORT1XCH16 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH17 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH17 << 4) /**< Shifted mode APORT1YCH17 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH18 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH18 << 4) /**< Shifted mode APORT1XCH18 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH19 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH19 << 4) /**< Shifted mode APORT1YCH19 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH20 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH20 << 4) /**< Shifted mode APORT1XCH20 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH21 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH21 << 4) /**< Shifted mode APORT1YCH21 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH22 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH22 << 4) /**< Shifted mode APORT1XCH22 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH23 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH23 << 4) /**< Shifted mode APORT1YCH23 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH24 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH24 << 4) /**< Shifted mode APORT1XCH24 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH25 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH25 << 4) /**< Shifted mode APORT1YCH25 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH26 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH26 << 4) /**< Shifted mode APORT1XCH26 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH27 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH27 << 4) /**< Shifted mode APORT1YCH27 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH28 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH28 << 4) /**< Shifted mode APORT1XCH28 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH29 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH29 << 4) /**< Shifted mode APORT1YCH29 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1XCH30 (_IDAC_CTRL_APORTOUTSEL_APORT1XCH30 << 4) /**< Shifted mode APORT1XCH30 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTSEL_APORT1YCH31 (_IDAC_CTRL_APORTOUTSEL_APORT1YCH31 << 4) /**< Shifted mode APORT1YCH31 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL (0x1UL << 12) /**< Power Select */
|
||||
#define _IDAC_CTRL_PWRSEL_SHIFT 12 /**< Shift value for IDAC_PWRSEL */
|
||||
#define _IDAC_CTRL_PWRSEL_MASK 0x1000UL /**< Bit mask for IDAC_PWRSEL */
|
||||
#define _IDAC_CTRL_PWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PWRSEL_ANA 0x00000000UL /**< Mode ANA for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PWRSEL_IO 0x00000001UL /**< Mode IO for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_DEFAULT (_IDAC_CTRL_PWRSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_ANA (_IDAC_CTRL_PWRSEL_ANA << 12) /**< Shifted mode ANA for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PWRSEL_IO (_IDAC_CTRL_PWRSEL_IO << 12) /**< Shifted mode IO for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EM2DELAY (0x1UL << 13) /**< EM2 Delay */
|
||||
#define _IDAC_CTRL_EM2DELAY_SHIFT 13 /**< Shift value for IDAC_EM2DELAY */
|
||||
#define _IDAC_CTRL_EM2DELAY_MASK 0x2000UL /**< Bit mask for IDAC_EM2DELAY */
|
||||
#define _IDAC_CTRL_EM2DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_EM2DELAY_DEFAULT (_IDAC_CTRL_EM2DELAY_DEFAULT << 13) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTMASTERDIS (0x1UL << 14) /**< APORT Bus Master Disable */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_SHIFT 14 /**< Shift value for IDAC_APORTMASTERDIS */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_MASK 0x4000UL /**< Bit mask for IDAC_APORTMASTERDIS */
|
||||
#define _IDAC_CTRL_APORTMASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTMASTERDIS_DEFAULT (_IDAC_CTRL_APORTMASTERDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTENPRS (0x1UL << 16) /**< PRS Controlled APORT Output Enable */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_SHIFT 16 /**< Shift value for IDAC_APORTOUTENPRS */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_MASK 0x10000UL /**< Bit mask for IDAC_APORTOUTENPRS */
|
||||
#define _IDAC_CTRL_APORTOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_APORTOUTENPRS_DEFAULT (_IDAC_CTRL_APORTOUTENPRS_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTEN (0x1UL << 18) /**< Output Enable */
|
||||
#define _IDAC_CTRL_MAINOUTEN_SHIFT 18 /**< Shift value for IDAC_MAINOUTEN */
|
||||
#define _IDAC_CTRL_MAINOUTEN_MASK 0x40000UL /**< Bit mask for IDAC_MAINOUTEN */
|
||||
#define _IDAC_CTRL_MAINOUTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTEN_DEFAULT (_IDAC_CTRL_MAINOUTEN_DEFAULT << 18) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTENPRS (0x1UL << 19) /**< PRS Controlled Main Pad Output Enable */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_SHIFT 19 /**< Shift value for IDAC_MAINOUTENPRS */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_MASK 0x80000UL /**< Bit mask for IDAC_MAINOUTENPRS */
|
||||
#define _IDAC_CTRL_MAINOUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_MAINOUTENPRS_DEFAULT (_IDAC_CTRL_MAINOUTENPRS_DEFAULT << 19) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_SHIFT 20 /**< Shift value for IDAC_PRSSEL */
|
||||
#define _IDAC_CTRL_PRSSEL_MASK 0x1F00000UL /**< Bit mask for IDAC_PRSSEL */
|
||||
#define _IDAC_CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for IDAC_CTRL */
|
||||
#define _IDAC_CTRL_PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_DEFAULT (_IDAC_CTRL_PRSSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH0 (_IDAC_CTRL_PRSSEL_PRSCH0 << 20) /**< Shifted mode PRSCH0 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH1 (_IDAC_CTRL_PRSSEL_PRSCH1 << 20) /**< Shifted mode PRSCH1 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH2 (_IDAC_CTRL_PRSSEL_PRSCH2 << 20) /**< Shifted mode PRSCH2 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH3 (_IDAC_CTRL_PRSSEL_PRSCH3 << 20) /**< Shifted mode PRSCH3 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH4 (_IDAC_CTRL_PRSSEL_PRSCH4 << 20) /**< Shifted mode PRSCH4 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH5 (_IDAC_CTRL_PRSSEL_PRSCH5 << 20) /**< Shifted mode PRSCH5 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH6 (_IDAC_CTRL_PRSSEL_PRSCH6 << 20) /**< Shifted mode PRSCH6 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH7 (_IDAC_CTRL_PRSSEL_PRSCH7 << 20) /**< Shifted mode PRSCH7 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH8 (_IDAC_CTRL_PRSSEL_PRSCH8 << 20) /**< Shifted mode PRSCH8 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH9 (_IDAC_CTRL_PRSSEL_PRSCH9 << 20) /**< Shifted mode PRSCH9 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH10 (_IDAC_CTRL_PRSSEL_PRSCH10 << 20) /**< Shifted mode PRSCH10 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH11 (_IDAC_CTRL_PRSSEL_PRSCH11 << 20) /**< Shifted mode PRSCH11 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH12 (_IDAC_CTRL_PRSSEL_PRSCH12 << 20) /**< Shifted mode PRSCH12 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH13 (_IDAC_CTRL_PRSSEL_PRSCH13 << 20) /**< Shifted mode PRSCH13 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH14 (_IDAC_CTRL_PRSSEL_PRSCH14 << 20) /**< Shifted mode PRSCH14 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH15 (_IDAC_CTRL_PRSSEL_PRSCH15 << 20) /**< Shifted mode PRSCH15 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH16 (_IDAC_CTRL_PRSSEL_PRSCH16 << 20) /**< Shifted mode PRSCH16 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH17 (_IDAC_CTRL_PRSSEL_PRSCH17 << 20) /**< Shifted mode PRSCH17 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH18 (_IDAC_CTRL_PRSSEL_PRSCH18 << 20) /**< Shifted mode PRSCH18 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH19 (_IDAC_CTRL_PRSSEL_PRSCH19 << 20) /**< Shifted mode PRSCH19 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH20 (_IDAC_CTRL_PRSSEL_PRSCH20 << 20) /**< Shifted mode PRSCH20 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH21 (_IDAC_CTRL_PRSSEL_PRSCH21 << 20) /**< Shifted mode PRSCH21 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH22 (_IDAC_CTRL_PRSSEL_PRSCH22 << 20) /**< Shifted mode PRSCH22 for IDAC_CTRL */
|
||||
#define IDAC_CTRL_PRSSEL_PRSCH23 (_IDAC_CTRL_PRSSEL_PRSCH23 << 20) /**< Shifted mode PRSCH23 for IDAC_CTRL */
|
||||
|
||||
/* Bit fields for IDAC CURPROG */
|
||||
#define _IDAC_CURPROG_RESETVALUE 0x009B0000UL /**< Default value for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_MASK 0x00FF1F03UL /**< Mask for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_SHIFT 0 /**< Shift value for IDAC_RANGESEL */
|
||||
#define _IDAC_CURPROG_RANGESEL_MASK 0x3UL /**< Bit mask for IDAC_RANGESEL */
|
||||
#define _IDAC_CURPROG_RANGESEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE0 0x00000000UL /**< Mode RANGE0 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE1 0x00000001UL /**< Mode RANGE1 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE2 0x00000002UL /**< Mode RANGE2 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_RANGESEL_RANGE3 0x00000003UL /**< Mode RANGE3 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_DEFAULT (_IDAC_CURPROG_RANGESEL_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE0 (_IDAC_CURPROG_RANGESEL_RANGE0 << 0) /**< Shifted mode RANGE0 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE1 (_IDAC_CURPROG_RANGESEL_RANGE1 << 0) /**< Shifted mode RANGE1 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE2 (_IDAC_CURPROG_RANGESEL_RANGE2 << 0) /**< Shifted mode RANGE2 for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_RANGESEL_RANGE3 (_IDAC_CURPROG_RANGESEL_RANGE3 << 0) /**< Shifted mode RANGE3 for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_STEPSEL_SHIFT 8 /**< Shift value for IDAC_STEPSEL */
|
||||
#define _IDAC_CURPROG_STEPSEL_MASK 0x1F00UL /**< Bit mask for IDAC_STEPSEL */
|
||||
#define _IDAC_CURPROG_STEPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_STEPSEL_DEFAULT (_IDAC_CURPROG_STEPSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
#define _IDAC_CURPROG_TUNING_SHIFT 16 /**< Shift value for IDAC_TUNING */
|
||||
#define _IDAC_CURPROG_TUNING_MASK 0xFF0000UL /**< Bit mask for IDAC_TUNING */
|
||||
#define _IDAC_CURPROG_TUNING_DEFAULT 0x0000009BUL /**< Mode DEFAULT for IDAC_CURPROG */
|
||||
#define IDAC_CURPROG_TUNING_DEFAULT (_IDAC_CURPROG_TUNING_DEFAULT << 16) /**< Shifted mode DEFAULT for IDAC_CURPROG */
|
||||
|
||||
/* Bit fields for IDAC DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_RESETVALUE 0x00000000UL /**< Default value for IDAC_DUTYCONFIG */
|
||||
#define _IDAC_DUTYCONFIG_MASK 0x00000002UL /**< Mask for IDAC_DUTYCONFIG */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS (0x1UL << 1) /**< Duty Cycle Enable */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_SHIFT 1 /**< Shift value for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_MASK 0x2UL /**< Bit mask for IDAC_EM2DUTYCYCLEDIS */
|
||||
#define _IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_DUTYCONFIG */
|
||||
#define IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT (_IDAC_DUTYCONFIG_EM2DUTYCYCLEDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_DUTYCONFIG */
|
||||
|
||||
/* Bit fields for IDAC STATUS */
|
||||
#define _IDAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for IDAC_STATUS */
|
||||
#define _IDAC_STATUS_MASK 0x00000003UL /**< Mask for IDAC_STATUS */
|
||||
#define IDAC_STATUS_CURSTABLE (0x1UL << 0) /**< IDAC Output Current Stable */
|
||||
#define _IDAC_STATUS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_STATUS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_STATUS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_CURSTABLE_DEFAULT (_IDAC_STATUS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Output */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_STATUS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_STATUS */
|
||||
#define IDAC_STATUS_APORTCONFLICT_DEFAULT (_IDAC_STATUS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_STATUS */
|
||||
|
||||
/* Bit fields for IDAC IF */
|
||||
#define _IDAC_IF_RESETVALUE 0x00000000UL /**< Default value for IDAC_IF */
|
||||
#define _IDAC_IF_MASK 0x00000003UL /**< Mask for IDAC_IF */
|
||||
#define IDAC_IF_CURSTABLE (0x1UL << 0) /**< Edge Triggered Interrupt Flag */
|
||||
#define _IDAC_IF_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IF_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IF_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_CURSTABLE_DEFAULT (_IDAC_IF_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_APORTCONFLICT (0x1UL << 1) /**< APORT Conflict Interrupt Flag */
|
||||
#define _IDAC_IF_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IF_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IF_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IF */
|
||||
#define IDAC_IF_APORTCONFLICT_DEFAULT (_IDAC_IF_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IF */
|
||||
|
||||
/* Bit fields for IDAC IFS */
|
||||
#define _IDAC_IFS_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFS */
|
||||
#define _IDAC_IFS_MASK 0x00000003UL /**< Mask for IDAC_IFS */
|
||||
#define IDAC_IFS_CURSTABLE (0x1UL << 0) /**< Set CURSTABLE Interrupt Flag */
|
||||
#define _IDAC_IFS_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFS_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFS_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_CURSTABLE_DEFAULT (_IDAC_IFS_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_APORTCONFLICT (0x1UL << 1) /**< Set APORTCONFLICT Interrupt Flag */
|
||||
#define _IDAC_IFS_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFS_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFS_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFS */
|
||||
#define IDAC_IFS_APORTCONFLICT_DEFAULT (_IDAC_IFS_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFS */
|
||||
|
||||
/* Bit fields for IDAC IFC */
|
||||
#define _IDAC_IFC_RESETVALUE 0x00000000UL /**< Default value for IDAC_IFC */
|
||||
#define _IDAC_IFC_MASK 0x00000003UL /**< Mask for IDAC_IFC */
|
||||
#define IDAC_IFC_CURSTABLE (0x1UL << 0) /**< Clear CURSTABLE Interrupt Flag */
|
||||
#define _IDAC_IFC_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFC_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IFC_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_CURSTABLE_DEFAULT (_IDAC_IFC_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_APORTCONFLICT (0x1UL << 1) /**< Clear APORTCONFLICT Interrupt Flag */
|
||||
#define _IDAC_IFC_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFC_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IFC_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IFC */
|
||||
#define IDAC_IFC_APORTCONFLICT_DEFAULT (_IDAC_IFC_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IFC */
|
||||
|
||||
/* Bit fields for IDAC IEN */
|
||||
#define _IDAC_IEN_RESETVALUE 0x00000000UL /**< Default value for IDAC_IEN */
|
||||
#define _IDAC_IEN_MASK 0x00000003UL /**< Mask for IDAC_IEN */
|
||||
#define IDAC_IEN_CURSTABLE (0x1UL << 0) /**< CURSTABLE Interrupt Enable */
|
||||
#define _IDAC_IEN_CURSTABLE_SHIFT 0 /**< Shift value for IDAC_CURSTABLE */
|
||||
#define _IDAC_IEN_CURSTABLE_MASK 0x1UL /**< Bit mask for IDAC_CURSTABLE */
|
||||
#define _IDAC_IEN_CURSTABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_CURSTABLE_DEFAULT (_IDAC_IEN_CURSTABLE_DEFAULT << 0) /**< Shifted mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_APORTCONFLICT (0x1UL << 1) /**< APORTCONFLICT Interrupt Enable */
|
||||
#define _IDAC_IEN_APORTCONFLICT_SHIFT 1 /**< Shift value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IEN_APORTCONFLICT_MASK 0x2UL /**< Bit mask for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_IEN_APORTCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_IEN */
|
||||
#define IDAC_IEN_APORTCONFLICT_DEFAULT (_IDAC_IEN_APORTCONFLICT_DEFAULT << 1) /**< Shifted mode DEFAULT for IDAC_IEN */
|
||||
|
||||
/* Bit fields for IDAC APORTREQ */
|
||||
#define _IDAC_APORTREQ_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTREQ */
|
||||
#define _IDAC_APORTREQ_MASK 0x0000000CUL /**< Mask for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ (0x1UL << 2) /**< 1 If the APORT Bus Connected to APORT1X is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_SHIFT 2 /**< Shift value for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_MASK 0x4UL /**< Bit mask for IDAC_APORT1XREQ */
|
||||
#define _IDAC_APORTREQ_APORT1XREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1XREQ_DEFAULT (_IDAC_APORTREQ_APORT1XREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1YREQ (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is Requested */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_SHIFT 3 /**< Shift value for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_MASK 0x8UL /**< Bit mask for IDAC_APORT1YREQ */
|
||||
#define _IDAC_APORTREQ_APORT1YREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTREQ */
|
||||
#define IDAC_APORTREQ_APORT1YREQ_DEFAULT (_IDAC_APORTREQ_APORT1YREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTREQ */
|
||||
|
||||
/* Bit fields for IDAC APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_RESETVALUE 0x00000000UL /**< Default value for IDAC_APORTCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_MASK 0x0000000CUL /**< Mask for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT (0x1UL << 2) /**< 1 If the Bus Connected to APORT1X is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_SHIFT 2 /**< Shift value for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_MASK 0x4UL /**< Bit mask for IDAC_APORT1XCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1XCONFLICT_DEFAULT << 2) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT (0x1UL << 3) /**< 1 If the Bus Connected to APORT1Y is in Conflict With Another Peripheral */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_SHIFT 3 /**< Shift value for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_MASK 0x8UL /**< Bit mask for IDAC_APORT1YCONFLICT */
|
||||
#define _IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT 0x00000000UL /**< Mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
#define IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT (_IDAC_APORTCONFLICT_APORT1YCONFLICT_DEFAULT << 3) /**< Shifted mode DEFAULT for IDAC_APORTCONFLICT */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_IDAC */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
636
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h
vendored
Normal file
636
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lcd.h
vendored
Normal file
@ -0,0 +1,636 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LCD register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LCD LCD
|
||||
* @{
|
||||
* @brief EFM32GG11B_LCD Register Declaration
|
||||
******************************************************************************/
|
||||
/** LCD Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t DISPCTRL; /**< Display Control Register */
|
||||
__IOM uint32_t SEGEN; /**< Segment Enable Register */
|
||||
__IOM uint32_t BACTRL; /**< Blink and Animation Control Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t AREGA; /**< Animation Register a */
|
||||
__IOM uint32_t AREGB; /**< Animation Register B */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BIASCTRL; /**< Analog BIAS Control */
|
||||
|
||||
uint32_t RESERVED1[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t SEGD0L; /**< Segment Data Low Register 0 */
|
||||
__IOM uint32_t SEGD1L; /**< Segment Data Low Register 1 */
|
||||
__IOM uint32_t SEGD2L; /**< Segment Data Low Register 2 */
|
||||
__IOM uint32_t SEGD3L; /**< Segment Data Low Register 3 */
|
||||
__IOM uint32_t SEGD0H; /**< Segment Data High Register 0 */
|
||||
__IOM uint32_t SEGD1H; /**< Segment Data High Register 1 */
|
||||
__IOM uint32_t SEGD2H; /**< Segment Data High Register 2 */
|
||||
__IOM uint32_t SEGD3H; /**< Segment Data High Register 3 */
|
||||
__IOM uint32_t SEGD4L; /**< Segment Data Low Register 4 */
|
||||
__IOM uint32_t SEGD5L; /**< Segment Data Low Register 5 */
|
||||
__IOM uint32_t SEGD6L; /**< Segment Data Low Register 6 */
|
||||
__IOM uint32_t SEGD7L; /**< Segment Data Low Register 7 */
|
||||
__IOM uint32_t SEGD4H; /**< Segment Data High Register 4 */
|
||||
__IOM uint32_t SEGD5H; /**< Segment Data High Register 5 */
|
||||
__IOM uint32_t SEGD6H; /**< Segment Data High Register 6 */
|
||||
__IOM uint32_t SEGD7H; /**< Segment Data High Register 7 */
|
||||
uint32_t RESERVED2[16U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
uint32_t RESERVED3[10U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FRAMERATE; /**< Frame Rate */
|
||||
__IOM uint32_t SEGEN2; /**< Segment Enable (32 to 39) */
|
||||
} LCD_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LCD
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LCD_BitFields LCD Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LCD CTRL */
|
||||
#define _LCD_CTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_CTRL */
|
||||
#define _LCD_CTRL_MASK 0x00800007UL /**< Mask for LCD_CTRL */
|
||||
#define LCD_CTRL_EN (0x1UL << 0) /**< LCD Enable */
|
||||
#define _LCD_CTRL_EN_SHIFT 0 /**< Shift value for LCD_EN */
|
||||
#define _LCD_CTRL_EN_MASK 0x1UL /**< Bit mask for LCD_EN */
|
||||
#define _LCD_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_EN_DEFAULT (_LCD_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_SHIFT 1 /**< Shift value for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_MASK 0x6UL /**< Bit mask for LCD_UDCTRL */
|
||||
#define _LCD_CTRL_UDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_REGULAR 0x00000000UL /**< Mode REGULAR for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FCEVENT 0x00000001UL /**< Mode FCEVENT for LCD_CTRL */
|
||||
#define _LCD_CTRL_UDCTRL_FRAMESTART 0x00000002UL /**< Mode FRAMESTART for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_DEFAULT (_LCD_CTRL_UDCTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_REGULAR (_LCD_CTRL_UDCTRL_REGULAR << 1) /**< Shifted mode REGULAR for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FCEVENT (_LCD_CTRL_UDCTRL_FCEVENT << 1) /**< Shifted mode FCEVENT for LCD_CTRL */
|
||||
#define LCD_CTRL_UDCTRL_FRAMESTART (_LCD_CTRL_UDCTRL_FRAMESTART << 1) /**< Shifted mode FRAMESTART for LCD_CTRL */
|
||||
#define LCD_CTRL_DSC (0x1UL << 23) /**< Direct Segment Control */
|
||||
#define _LCD_CTRL_DSC_SHIFT 23 /**< Shift value for LCD_DSC */
|
||||
#define _LCD_CTRL_DSC_MASK 0x800000UL /**< Bit mask for LCD_DSC */
|
||||
#define _LCD_CTRL_DSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_CTRL */
|
||||
#define LCD_CTRL_DSC_DEFAULT (_LCD_CTRL_DSC_DEFAULT << 23) /**< Shifted mode DEFAULT for LCD_CTRL */
|
||||
|
||||
/* Bit fields for LCD DISPCTRL */
|
||||
#define _LCD_DISPCTRL_RESETVALUE 0x00103F00UL /**< Default value for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MASK 0x33703F17UL /**< Mask for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_SHIFT 0 /**< Shift value for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_MASK 0x7UL /**< Bit mask for LCD_MUX */
|
||||
#define _LCD_DISPCTRL_MUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_DUPLEX 0x00000001UL /**< Mode DUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_TRIPLEX 0x00000002UL /**< Mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_QUADRUPLEX 0x00000003UL /**< Mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_SEXTAPLEX 0x00000005UL /**< Mode SEXTAPLEX for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MUX_OCTAPLEX 0x00000007UL /**< Mode OCTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DEFAULT (_LCD_DISPCTRL_MUX_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_STATIC (_LCD_DISPCTRL_MUX_STATIC << 0) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_DUPLEX (_LCD_DISPCTRL_MUX_DUPLEX << 0) /**< Shifted mode DUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_TRIPLEX (_LCD_DISPCTRL_MUX_TRIPLEX << 0) /**< Shifted mode TRIPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_QUADRUPLEX (_LCD_DISPCTRL_MUX_QUADRUPLEX << 0) /**< Shifted mode QUADRUPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_SEXTAPLEX (_LCD_DISPCTRL_MUX_SEXTAPLEX << 0) /**< Shifted mode SEXTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MUX_OCTAPLEX (_LCD_DISPCTRL_MUX_OCTAPLEX << 0) /**< Shifted mode OCTAPLEX for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE (0x1UL << 4) /**< Waveform Selection */
|
||||
#define _LCD_DISPCTRL_WAVE_SHIFT 4 /**< Shift value for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_MASK 0x10UL /**< Bit mask for LCD_WAVE */
|
||||
#define _LCD_DISPCTRL_WAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_LOWPOWER 0x00000000UL /**< Mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_WAVE_NORMAL 0x00000001UL /**< Mode NORMAL for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_DEFAULT (_LCD_DISPCTRL_WAVE_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_LOWPOWER (_LCD_DISPCTRL_WAVE_LOWPOWER << 4) /**< Shifted mode LOWPOWER for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_WAVE_NORMAL (_LCD_DISPCTRL_WAVE_NORMAL << 4) /**< Shifted mode NORMAL for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CONTRAST_SHIFT 8 /**< Shift value for LCD_CONTRAST */
|
||||
#define _LCD_DISPCTRL_CONTRAST_MASK 0x3F00UL /**< Bit mask for LCD_CONTRAST */
|
||||
#define _LCD_DISPCTRL_CONTRAST_DEFAULT 0x0000003FUL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CONTRAST_DEFAULT (_LCD_DISPCTRL_CONTRAST_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_SHIFT 20 /**< Shift value for LCD_CHGRDST */
|
||||
#define _LCD_DISPCTRL_CHGRDST_MASK 0x700000UL /**< Bit mask for LCD_CHGRDST */
|
||||
#define _LCD_DISPCTRL_CHGRDST_DISABLE 0x00000000UL /**< Mode DISABLE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_DEFAULT 0x00000001UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_ONE 0x00000001UL /**< Mode ONE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_TWO 0x00000002UL /**< Mode TWO for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_THREE 0x00000003UL /**< Mode THREE for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_CHGRDST_FOUR 0x00000004UL /**< Mode FOUR for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_DISABLE (_LCD_DISPCTRL_CHGRDST_DISABLE << 20) /**< Shifted mode DISABLE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_DEFAULT (_LCD_DISPCTRL_CHGRDST_DEFAULT << 20) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_ONE (_LCD_DISPCTRL_CHGRDST_ONE << 20) /**< Shifted mode ONE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_TWO (_LCD_DISPCTRL_CHGRDST_TWO << 20) /**< Shifted mode TWO for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_THREE (_LCD_DISPCTRL_CHGRDST_THREE << 20) /**< Shifted mode THREE for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_CHGRDST_FOUR (_LCD_DISPCTRL_CHGRDST_FOUR << 20) /**< Shifted mode FOUR for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_SHIFT 24 /**< Shift value for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_MASK 0x3000000UL /**< Bit mask for LCD_BIAS */
|
||||
#define _LCD_DISPCTRL_BIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_STATIC 0x00000000UL /**< Mode STATIC for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONEHALF 0x00000001UL /**< Mode ONEHALF for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONETHIRD 0x00000002UL /**< Mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_BIAS_ONEFOURTH 0x00000003UL /**< Mode ONEFOURTH for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_DEFAULT (_LCD_DISPCTRL_BIAS_DEFAULT << 24) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_STATIC (_LCD_DISPCTRL_BIAS_STATIC << 24) /**< Shifted mode STATIC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONEHALF (_LCD_DISPCTRL_BIAS_ONEHALF << 24) /**< Shifted mode ONEHALF for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONETHIRD (_LCD_DISPCTRL_BIAS_ONETHIRD << 24) /**< Shifted mode ONETHIRD for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_BIAS_ONEFOURTH (_LCD_DISPCTRL_BIAS_ONEFOURTH << 24) /**< Shifted mode ONEFOURTH for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_SHIFT 28 /**< Shift value for LCD_MODE */
|
||||
#define _LCD_DISPCTRL_MODE_MASK 0x30000000UL /**< Bit mask for LCD_MODE */
|
||||
#define _LCD_DISPCTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_NOEXTCAP 0x00000000UL /**< Mode NOEXTCAP for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_STEPDOWN 0x00000001UL /**< Mode STEPDOWN for LCD_DISPCTRL */
|
||||
#define _LCD_DISPCTRL_MODE_CPINTOSC 0x00000002UL /**< Mode CPINTOSC for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_DEFAULT (_LCD_DISPCTRL_MODE_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_NOEXTCAP (_LCD_DISPCTRL_MODE_NOEXTCAP << 28) /**< Shifted mode NOEXTCAP for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_STEPDOWN (_LCD_DISPCTRL_MODE_STEPDOWN << 28) /**< Shifted mode STEPDOWN for LCD_DISPCTRL */
|
||||
#define LCD_DISPCTRL_MODE_CPINTOSC (_LCD_DISPCTRL_MODE_CPINTOSC << 28) /**< Shifted mode CPINTOSC for LCD_DISPCTRL */
|
||||
|
||||
/* Bit fields for LCD SEGEN */
|
||||
#define _LCD_SEGEN_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_SHIFT 0 /**< Shift value for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGEN */
|
||||
#define _LCD_SEGEN_SEGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN */
|
||||
#define LCD_SEGEN_SEGEN_DEFAULT (_LCD_SEGEN_SEGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN */
|
||||
|
||||
/* Bit fields for LCD BACTRL */
|
||||
#define _LCD_BACTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_MASK 0x10FF01FFUL /**< Mask for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN (0x1UL << 0) /**< Blink Enable */
|
||||
#define _LCD_BACTRL_BLINKEN_SHIFT 0 /**< Shift value for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_MASK 0x1UL /**< Bit mask for LCD_BLINKEN */
|
||||
#define _LCD_BACTRL_BLINKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLINKEN_DEFAULT (_LCD_BACTRL_BLINKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK (0x1UL << 1) /**< Blank Display */
|
||||
#define _LCD_BACTRL_BLANK_SHIFT 1 /**< Shift value for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_MASK 0x2UL /**< Bit mask for LCD_BLANK */
|
||||
#define _LCD_BACTRL_BLANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_BLANK_DEFAULT (_LCD_BACTRL_BLANK_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN (0x1UL << 2) /**< Animation Enable */
|
||||
#define _LCD_BACTRL_AEN_SHIFT 2 /**< Shift value for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_MASK 0x4UL /**< Bit mask for LCD_AEN */
|
||||
#define _LCD_BACTRL_AEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AEN_DEFAULT (_LCD_BACTRL_AEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFT 3 /**< Shift value for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_MASK 0x18UL /**< Bit mask for LCD_AREGASC */
|
||||
#define _LCD_BACTRL_AREGASC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGASC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_DEFAULT (_LCD_BACTRL_AREGASC_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_NOSHIFT (_LCD_BACTRL_AREGASC_NOSHIFT << 3) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTLEFT (_LCD_BACTRL_AREGASC_SHIFTLEFT << 3) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGASC_SHIFTRIGHT (_LCD_BACTRL_AREGASC_SHIFTRIGHT << 3) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFT 5 /**< Shift value for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_MASK 0x60UL /**< Bit mask for LCD_AREGBSC */
|
||||
#define _LCD_BACTRL_AREGBSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_NOSHIFT 0x00000000UL /**< Mode NOSHIFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTLEFT 0x00000001UL /**< Mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_AREGBSC_SHIFTRIGHT 0x00000002UL /**< Mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_DEFAULT (_LCD_BACTRL_AREGBSC_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_NOSHIFT (_LCD_BACTRL_AREGBSC_NOSHIFT << 5) /**< Shifted mode NOSHIFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTLEFT (_LCD_BACTRL_AREGBSC_SHIFTLEFT << 5) /**< Shifted mode SHIFTLEFT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_AREGBSC_SHIFTRIGHT (_LCD_BACTRL_AREGBSC_SHIFTRIGHT << 5) /**< Shifted mode SHIFTRIGHT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL (0x1UL << 7) /**< Animate Logic Function Select */
|
||||
#define _LCD_BACTRL_ALOGSEL_SHIFT 7 /**< Shift value for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_MASK 0x80UL /**< Bit mask for LCD_ALOGSEL */
|
||||
#define _LCD_BACTRL_ALOGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_AND 0x00000000UL /**< Mode AND for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOGSEL_OR 0x00000001UL /**< Mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_DEFAULT (_LCD_BACTRL_ALOGSEL_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_AND (_LCD_BACTRL_ALOGSEL_AND << 7) /**< Shifted mode AND for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOGSEL_OR (_LCD_BACTRL_ALOGSEL_OR << 7) /**< Shifted mode OR for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN (0x1UL << 8) /**< Frame Counter Enable */
|
||||
#define _LCD_BACTRL_FCEN_SHIFT 8 /**< Shift value for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_MASK 0x100UL /**< Bit mask for LCD_FCEN */
|
||||
#define _LCD_BACTRL_FCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCEN_DEFAULT (_LCD_BACTRL_FCEN_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_SHIFT 16 /**< Shift value for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_MASK 0x30000UL /**< Bit mask for LCD_FCPRESC */
|
||||
#define _LCD_BACTRL_FCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DEFAULT (_LCD_BACTRL_FCPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV1 (_LCD_BACTRL_FCPRESC_DIV1 << 16) /**< Shifted mode DIV1 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV2 (_LCD_BACTRL_FCPRESC_DIV2 << 16) /**< Shifted mode DIV2 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV4 (_LCD_BACTRL_FCPRESC_DIV4 << 16) /**< Shifted mode DIV4 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCPRESC_DIV8 (_LCD_BACTRL_FCPRESC_DIV8 << 16) /**< Shifted mode DIV8 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_FCTOP_SHIFT 18 /**< Shift value for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_MASK 0xFC0000UL /**< Bit mask for LCD_FCTOP */
|
||||
#define _LCD_BACTRL_FCTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_FCTOP_DEFAULT (_LCD_BACTRL_FCTOP_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC (0x1UL << 28) /**< Animation Location */
|
||||
#define _LCD_BACTRL_ALOC_SHIFT 28 /**< Shift value for LCD_ALOC */
|
||||
#define _LCD_BACTRL_ALOC_MASK 0x10000000UL /**< Bit mask for LCD_ALOC */
|
||||
#define _LCD_BACTRL_ALOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOC_SEG0TO7 0x00000000UL /**< Mode SEG0TO7 for LCD_BACTRL */
|
||||
#define _LCD_BACTRL_ALOC_SEG8TO15 0x00000001UL /**< Mode SEG8TO15 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_DEFAULT (_LCD_BACTRL_ALOC_DEFAULT << 28) /**< Shifted mode DEFAULT for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_SEG0TO7 (_LCD_BACTRL_ALOC_SEG0TO7 << 28) /**< Shifted mode SEG0TO7 for LCD_BACTRL */
|
||||
#define LCD_BACTRL_ALOC_SEG8TO15 (_LCD_BACTRL_ALOC_SEG8TO15 << 28) /**< Shifted mode SEG8TO15 for LCD_BACTRL */
|
||||
|
||||
/* Bit fields for LCD STATUS */
|
||||
#define _LCD_STATUS_RESETVALUE 0x00000000UL /**< Default value for LCD_STATUS */
|
||||
#define _LCD_STATUS_MASK 0x0000010FUL /**< Mask for LCD_STATUS */
|
||||
#define _LCD_STATUS_ASTATE_SHIFT 0 /**< Shift value for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_MASK 0xFUL /**< Bit mask for LCD_ASTATE */
|
||||
#define _LCD_STATUS_ASTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_ASTATE_DEFAULT (_LCD_STATUS_ASTATE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK (0x1UL << 8) /**< Blink State */
|
||||
#define _LCD_STATUS_BLINK_SHIFT 8 /**< Shift value for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_MASK 0x100UL /**< Bit mask for LCD_BLINK */
|
||||
#define _LCD_STATUS_BLINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_STATUS */
|
||||
#define LCD_STATUS_BLINK_DEFAULT (_LCD_STATUS_BLINK_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_STATUS */
|
||||
|
||||
/* Bit fields for LCD AREGA */
|
||||
#define _LCD_AREGA_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGA */
|
||||
#define _LCD_AREGA_MASK 0x000000FFUL /**< Mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_SHIFT 0 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_MASK 0xFFUL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_AREGA_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGA */
|
||||
#define LCD_AREGA_AREGA_DEFAULT (_LCD_AREGA_AREGA_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGA */
|
||||
|
||||
/* Bit fields for LCD AREGB */
|
||||
#define _LCD_AREGB_RESETVALUE 0x00000000UL /**< Default value for LCD_AREGB */
|
||||
#define _LCD_AREGB_MASK 0x000000FFUL /**< Mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_SHIFT 0 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_MASK 0xFFUL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_AREGB_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_AREGB */
|
||||
#define LCD_AREGB_AREGB_DEFAULT (_LCD_AREGB_AREGB_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_AREGB */
|
||||
|
||||
/* Bit fields for LCD IF */
|
||||
#define _LCD_IF_RESETVALUE 0x00000000UL /**< Default value for LCD_IF */
|
||||
#define _LCD_IF_MASK 0x00000001UL /**< Mask for LCD_IF */
|
||||
#define LCD_IF_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag */
|
||||
#define _LCD_IF_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IF_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IF_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IF */
|
||||
#define LCD_IF_FC_DEFAULT (_LCD_IF_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IF */
|
||||
|
||||
/* Bit fields for LCD IFS */
|
||||
#define _LCD_IFS_RESETVALUE 0x00000000UL /**< Default value for LCD_IFS */
|
||||
#define _LCD_IFS_MASK 0x00000001UL /**< Mask for LCD_IFS */
|
||||
#define LCD_IFS_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Set */
|
||||
#define _LCD_IFS_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFS_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFS_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFS */
|
||||
#define LCD_IFS_FC_DEFAULT (_LCD_IFS_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFS */
|
||||
|
||||
/* Bit fields for LCD IFC */
|
||||
#define _LCD_IFC_RESETVALUE 0x00000000UL /**< Default value for LCD_IFC */
|
||||
#define _LCD_IFC_MASK 0x00000001UL /**< Mask for LCD_IFC */
|
||||
#define LCD_IFC_FC (0x1UL << 0) /**< Frame Counter Interrupt Flag Clear */
|
||||
#define _LCD_IFC_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IFC_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IFC_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IFC */
|
||||
#define LCD_IFC_FC_DEFAULT (_LCD_IFC_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IFC */
|
||||
|
||||
/* Bit fields for LCD IEN */
|
||||
#define _LCD_IEN_RESETVALUE 0x00000000UL /**< Default value for LCD_IEN */
|
||||
#define _LCD_IEN_MASK 0x00000001UL /**< Mask for LCD_IEN */
|
||||
#define LCD_IEN_FC (0x1UL << 0) /**< Frame Counter Interrupt Enable */
|
||||
#define _LCD_IEN_FC_SHIFT 0 /**< Shift value for LCD_FC */
|
||||
#define _LCD_IEN_FC_MASK 0x1UL /**< Bit mask for LCD_FC */
|
||||
#define _LCD_IEN_FC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_IEN */
|
||||
#define LCD_IEN_FC_DEFAULT (_LCD_IEN_FC_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_IEN */
|
||||
|
||||
/* Bit fields for LCD BIASCTRL */
|
||||
#define _LCD_BIASCTRL_RESETVALUE 0x00000000UL /**< Default value for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_MASK 0x00001CF7UL /**< Mask for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_SPEED_SHIFT 0 /**< Shift value for LCD_SPEED */
|
||||
#define _LCD_BIASCTRL_SPEED_MASK 0x7UL /**< Bit mask for LCD_SPEED */
|
||||
#define _LCD_BIASCTRL_SPEED_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_SPEED_DEFAULT (_LCD_BIASCTRL_SPEED_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_BUFDRV_SHIFT 4 /**< Shift value for LCD_BUFDRV */
|
||||
#define _LCD_BIASCTRL_BUFDRV_MASK 0xF0UL /**< Bit mask for LCD_BUFDRV */
|
||||
#define _LCD_BIASCTRL_BUFDRV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_BUFDRV_DEFAULT (_LCD_BIASCTRL_BUFDRV_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_SHIFT 10 /**< Shift value for LCD_BUFBIAS */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_MASK 0x1C00UL /**< Bit mask for LCD_BUFBIAS */
|
||||
#define _LCD_BIASCTRL_BUFBIAS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_BIASCTRL */
|
||||
#define LCD_BIASCTRL_BUFBIAS_DEFAULT (_LCD_BIASCTRL_BUFBIAS_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_BIASCTRL */
|
||||
|
||||
/* Bit fields for LCD SEGD0L */
|
||||
#define _LCD_SEGD0L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_SHIFT 0 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SEGD0L_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0L */
|
||||
#define LCD_SEGD0L_SEGD0L_DEFAULT (_LCD_SEGD0L_SEGD0L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0L */
|
||||
|
||||
/* Bit fields for LCD SEGD1L */
|
||||
#define _LCD_SEGD1L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_SHIFT 0 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SEGD1L_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1L */
|
||||
#define LCD_SEGD1L_SEGD1L_DEFAULT (_LCD_SEGD1L_SEGD1L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1L */
|
||||
|
||||
/* Bit fields for LCD SEGD2L */
|
||||
#define _LCD_SEGD2L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_SHIFT 0 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SEGD2L_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2L */
|
||||
#define LCD_SEGD2L_SEGD2L_DEFAULT (_LCD_SEGD2L_SEGD2L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2L */
|
||||
|
||||
/* Bit fields for LCD SEGD3L */
|
||||
#define _LCD_SEGD3L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_SHIFT 0 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SEGD3L_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3L */
|
||||
#define LCD_SEGD3L_SEGD3L_DEFAULT (_LCD_SEGD3L_SEGD3L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3L */
|
||||
|
||||
/* Bit fields for LCD SEGD0H */
|
||||
#define _LCD_SEGD0H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_MASK 0x000000FFUL /**< Mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_SHIFT 0 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_MASK 0xFFUL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SEGD0H_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD0H */
|
||||
#define LCD_SEGD0H_SEGD0H_DEFAULT (_LCD_SEGD0H_SEGD0H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD0H */
|
||||
|
||||
/* Bit fields for LCD SEGD1H */
|
||||
#define _LCD_SEGD1H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_MASK 0x000000FFUL /**< Mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_SHIFT 0 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_MASK 0xFFUL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SEGD1H_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD1H */
|
||||
#define LCD_SEGD1H_SEGD1H_DEFAULT (_LCD_SEGD1H_SEGD1H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD1H */
|
||||
|
||||
/* Bit fields for LCD SEGD2H */
|
||||
#define _LCD_SEGD2H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_MASK 0x000000FFUL /**< Mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_SHIFT 0 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_MASK 0xFFUL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SEGD2H_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD2H */
|
||||
#define LCD_SEGD2H_SEGD2H_DEFAULT (_LCD_SEGD2H_SEGD2H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD2H */
|
||||
|
||||
/* Bit fields for LCD SEGD3H */
|
||||
#define _LCD_SEGD3H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_MASK 0x000000FFUL /**< Mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_SHIFT 0 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_MASK 0xFFUL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SEGD3H_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD3H */
|
||||
#define LCD_SEGD3H_SEGD3H_DEFAULT (_LCD_SEGD3H_SEGD3H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD3H */
|
||||
|
||||
/* Bit fields for LCD SEGD4L */
|
||||
#define _LCD_SEGD4L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_SHIFT 0 /**< Shift value for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD4L */
|
||||
#define _LCD_SEGD4L_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4L */
|
||||
#define LCD_SEGD4L_SEGD4L_DEFAULT (_LCD_SEGD4L_SEGD4L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4L */
|
||||
|
||||
/* Bit fields for LCD SEGD5L */
|
||||
#define _LCD_SEGD5L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_SHIFT 0 /**< Shift value for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD5L */
|
||||
#define _LCD_SEGD5L_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5L */
|
||||
#define LCD_SEGD5L_SEGD5L_DEFAULT (_LCD_SEGD5L_SEGD5L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5L */
|
||||
|
||||
/* Bit fields for LCD SEGD6L */
|
||||
#define _LCD_SEGD6L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_SHIFT 0 /**< Shift value for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD6L */
|
||||
#define _LCD_SEGD6L_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6L */
|
||||
#define LCD_SEGD6L_SEGD6L_DEFAULT (_LCD_SEGD6L_SEGD6L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6L */
|
||||
|
||||
/* Bit fields for LCD SEGD7L */
|
||||
#define _LCD_SEGD7L_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_MASK 0xFFFFFFFFUL /**< Mask for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_SHIFT 0 /**< Shift value for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_MASK 0xFFFFFFFFUL /**< Bit mask for LCD_SEGD7L */
|
||||
#define _LCD_SEGD7L_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7L */
|
||||
#define LCD_SEGD7L_SEGD7L_DEFAULT (_LCD_SEGD7L_SEGD7L_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7L */
|
||||
|
||||
/* Bit fields for LCD SEGD4H */
|
||||
#define _LCD_SEGD4H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_MASK 0x000000FFUL /**< Mask for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_SHIFT 0 /**< Shift value for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_MASK 0xFFUL /**< Bit mask for LCD_SEGD4H */
|
||||
#define _LCD_SEGD4H_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD4H */
|
||||
#define LCD_SEGD4H_SEGD4H_DEFAULT (_LCD_SEGD4H_SEGD4H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD4H */
|
||||
|
||||
/* Bit fields for LCD SEGD5H */
|
||||
#define _LCD_SEGD5H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_MASK 0x000000FFUL /**< Mask for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_SHIFT 0 /**< Shift value for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_MASK 0xFFUL /**< Bit mask for LCD_SEGD5H */
|
||||
#define _LCD_SEGD5H_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD5H */
|
||||
#define LCD_SEGD5H_SEGD5H_DEFAULT (_LCD_SEGD5H_SEGD5H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD5H */
|
||||
|
||||
/* Bit fields for LCD SEGD6H */
|
||||
#define _LCD_SEGD6H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_MASK 0x000000FFUL /**< Mask for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_SHIFT 0 /**< Shift value for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_MASK 0xFFUL /**< Bit mask for LCD_SEGD6H */
|
||||
#define _LCD_SEGD6H_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD6H */
|
||||
#define LCD_SEGD6H_SEGD6H_DEFAULT (_LCD_SEGD6H_SEGD6H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD6H */
|
||||
|
||||
/* Bit fields for LCD SEGD7H */
|
||||
#define _LCD_SEGD7H_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_MASK 0x000000FFUL /**< Mask for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_SHIFT 0 /**< Shift value for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_MASK 0xFFUL /**< Bit mask for LCD_SEGD7H */
|
||||
#define _LCD_SEGD7H_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGD7H */
|
||||
#define LCD_SEGD7H_SEGD7H_DEFAULT (_LCD_SEGD7H_SEGD7H_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGD7H */
|
||||
|
||||
/* Bit fields for LCD FREEZE */
|
||||
#define _LCD_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_MASK 0x00000003UL /**< Mask for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LCD_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LCD_REGFREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_DEFAULT (_LCD_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_UPDATE (_LCD_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_REGFREEZE_FREEZE (_LCD_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE (0x1UL << 1) /**< LCD Gate */
|
||||
#define _LCD_FREEZE_LCDGATE_SHIFT 1 /**< Shift value for LCD_LCDGATE */
|
||||
#define _LCD_FREEZE_LCDGATE_MASK 0x2UL /**< Bit mask for LCD_LCDGATE */
|
||||
#define _LCD_FREEZE_LCDGATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_LCDGATE_UNGATE 0x00000000UL /**< Mode UNGATE for LCD_FREEZE */
|
||||
#define _LCD_FREEZE_LCDGATE_GATE 0x00000001UL /**< Mode GATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_DEFAULT (_LCD_FREEZE_LCDGATE_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_UNGATE (_LCD_FREEZE_LCDGATE_UNGATE << 1) /**< Shifted mode UNGATE for LCD_FREEZE */
|
||||
#define LCD_FREEZE_LCDGATE_GATE (_LCD_FREEZE_LCDGATE_GATE << 1) /**< Shifted mode GATE for LCD_FREEZE */
|
||||
|
||||
/* Bit fields for LCD SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LCD_SYNCBUSY */
|
||||
#define _LCD_SYNCBUSY_MASK 0x000FFFFFUL /**< Mask for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LCD_CTRL */
|
||||
#define _LCD_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_CTRL_DEFAULT (_LCD_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL (0x1UL << 1) /**< BACTRL Register Busy */
|
||||
#define _LCD_SYNCBUSY_BACTRL_SHIFT 1 /**< Shift value for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_MASK 0x2UL /**< Bit mask for LCD_BACTRL */
|
||||
#define _LCD_SYNCBUSY_BACTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_BACTRL_DEFAULT (_LCD_SYNCBUSY_BACTRL_DEFAULT << 1) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA (0x1UL << 2) /**< AREGA Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGA_SHIFT 2 /**< Shift value for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_MASK 0x4UL /**< Bit mask for LCD_AREGA */
|
||||
#define _LCD_SYNCBUSY_AREGA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGA_DEFAULT (_LCD_SYNCBUSY_AREGA_DEFAULT << 2) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB (0x1UL << 3) /**< AREGB Register Busy */
|
||||
#define _LCD_SYNCBUSY_AREGB_SHIFT 3 /**< Shift value for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_MASK 0x8UL /**< Bit mask for LCD_AREGB */
|
||||
#define _LCD_SYNCBUSY_AREGB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_AREGB_DEFAULT (_LCD_SYNCBUSY_AREGB_DEFAULT << 3) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L (0x1UL << 4) /**< SEGD0L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_SHIFT 4 /**< Shift value for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_MASK 0x10UL /**< Bit mask for LCD_SEGD0L */
|
||||
#define _LCD_SYNCBUSY_SEGD0L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0L_DEFAULT (_LCD_SYNCBUSY_SEGD0L_DEFAULT << 4) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L (0x1UL << 5) /**< SEGD1L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_SHIFT 5 /**< Shift value for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_MASK 0x20UL /**< Bit mask for LCD_SEGD1L */
|
||||
#define _LCD_SYNCBUSY_SEGD1L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1L_DEFAULT (_LCD_SYNCBUSY_SEGD1L_DEFAULT << 5) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L (0x1UL << 6) /**< SEGD2L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_SHIFT 6 /**< Shift value for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_MASK 0x40UL /**< Bit mask for LCD_SEGD2L */
|
||||
#define _LCD_SYNCBUSY_SEGD2L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2L_DEFAULT (_LCD_SYNCBUSY_SEGD2L_DEFAULT << 6) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L (0x1UL << 7) /**< SEGD3L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_SHIFT 7 /**< Shift value for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_MASK 0x80UL /**< Bit mask for LCD_SEGD3L */
|
||||
#define _LCD_SYNCBUSY_SEGD3L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3L_DEFAULT (_LCD_SYNCBUSY_SEGD3L_DEFAULT << 7) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H (0x1UL << 8) /**< SEGD0H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_SHIFT 8 /**< Shift value for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_MASK 0x100UL /**< Bit mask for LCD_SEGD0H */
|
||||
#define _LCD_SYNCBUSY_SEGD0H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD0H_DEFAULT (_LCD_SYNCBUSY_SEGD0H_DEFAULT << 8) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H (0x1UL << 9) /**< SEGD1H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_SHIFT 9 /**< Shift value for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_MASK 0x200UL /**< Bit mask for LCD_SEGD1H */
|
||||
#define _LCD_SYNCBUSY_SEGD1H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD1H_DEFAULT (_LCD_SYNCBUSY_SEGD1H_DEFAULT << 9) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H (0x1UL << 10) /**< SEGD2H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_SHIFT 10 /**< Shift value for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_MASK 0x400UL /**< Bit mask for LCD_SEGD2H */
|
||||
#define _LCD_SYNCBUSY_SEGD2H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD2H_DEFAULT (_LCD_SYNCBUSY_SEGD2H_DEFAULT << 10) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H (0x1UL << 11) /**< SEGD3H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_SHIFT 11 /**< Shift value for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_MASK 0x800UL /**< Bit mask for LCD_SEGD3H */
|
||||
#define _LCD_SYNCBUSY_SEGD3H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD3H_DEFAULT (_LCD_SYNCBUSY_SEGD3H_DEFAULT << 11) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4L (0x1UL << 12) /**< SEGD4L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_SHIFT 12 /**< Shift value for LCD_SEGD4L */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_MASK 0x1000UL /**< Bit mask for LCD_SEGD4L */
|
||||
#define _LCD_SYNCBUSY_SEGD4L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4L_DEFAULT (_LCD_SYNCBUSY_SEGD4L_DEFAULT << 12) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5L (0x1UL << 13) /**< SEGD5L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_SHIFT 13 /**< Shift value for LCD_SEGD5L */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_MASK 0x2000UL /**< Bit mask for LCD_SEGD5L */
|
||||
#define _LCD_SYNCBUSY_SEGD5L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5L_DEFAULT (_LCD_SYNCBUSY_SEGD5L_DEFAULT << 13) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6L (0x1UL << 14) /**< SEGD6L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_SHIFT 14 /**< Shift value for LCD_SEGD6L */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_MASK 0x4000UL /**< Bit mask for LCD_SEGD6L */
|
||||
#define _LCD_SYNCBUSY_SEGD6L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6L_DEFAULT (_LCD_SYNCBUSY_SEGD6L_DEFAULT << 14) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7L (0x1UL << 15) /**< SEGD7L Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_SHIFT 15 /**< Shift value for LCD_SEGD7L */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_MASK 0x8000UL /**< Bit mask for LCD_SEGD7L */
|
||||
#define _LCD_SYNCBUSY_SEGD7L_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7L_DEFAULT (_LCD_SYNCBUSY_SEGD7L_DEFAULT << 15) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4H (0x1UL << 16) /**< SEGD4H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_SHIFT 16 /**< Shift value for LCD_SEGD4H */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_MASK 0x10000UL /**< Bit mask for LCD_SEGD4H */
|
||||
#define _LCD_SYNCBUSY_SEGD4H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD4H_DEFAULT (_LCD_SYNCBUSY_SEGD4H_DEFAULT << 16) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5H (0x1UL << 17) /**< SEGD5H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_SHIFT 17 /**< Shift value for LCD_SEGD5H */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_MASK 0x20000UL /**< Bit mask for LCD_SEGD5H */
|
||||
#define _LCD_SYNCBUSY_SEGD5H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD5H_DEFAULT (_LCD_SYNCBUSY_SEGD5H_DEFAULT << 17) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6H (0x1UL << 18) /**< SEGD6H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_SHIFT 18 /**< Shift value for LCD_SEGD6H */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_MASK 0x40000UL /**< Bit mask for LCD_SEGD6H */
|
||||
#define _LCD_SYNCBUSY_SEGD6H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD6H_DEFAULT (_LCD_SYNCBUSY_SEGD6H_DEFAULT << 18) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7H (0x1UL << 19) /**< SEGD7H Register Busy */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_SHIFT 19 /**< Shift value for LCD_SEGD7H */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_MASK 0x80000UL /**< Bit mask for LCD_SEGD7H */
|
||||
#define _LCD_SYNCBUSY_SEGD7H_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SYNCBUSY */
|
||||
#define LCD_SYNCBUSY_SEGD7H_DEFAULT (_LCD_SYNCBUSY_SEGD7H_DEFAULT << 19) /**< Shifted mode DEFAULT for LCD_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LCD FRAMERATE */
|
||||
#define _LCD_FRAMERATE_RESETVALUE 0x00000000UL /**< Default value for LCD_FRAMERATE */
|
||||
#define _LCD_FRAMERATE_MASK 0x000001FFUL /**< Mask for LCD_FRAMERATE */
|
||||
#define _LCD_FRAMERATE_FRDIV_SHIFT 0 /**< Shift value for LCD_FRDIV */
|
||||
#define _LCD_FRAMERATE_FRDIV_MASK 0x1FFUL /**< Bit mask for LCD_FRDIV */
|
||||
#define _LCD_FRAMERATE_FRDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_FRAMERATE */
|
||||
#define LCD_FRAMERATE_FRDIV_DEFAULT (_LCD_FRAMERATE_FRDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_FRAMERATE */
|
||||
|
||||
/* Bit fields for LCD SEGEN2 */
|
||||
#define _LCD_SEGEN2_RESETVALUE 0x00000000UL /**< Default value for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_MASK 0x000000FFUL /**< Mask for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_SHIFT 0 /**< Shift value for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_MASK 0xFFUL /**< Bit mask for LCD_SEGEN2 */
|
||||
#define _LCD_SEGEN2_SEGEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for LCD_SEGEN2 */
|
||||
#define LCD_SEGEN2_SEGEN2_DEFAULT (_LCD_SEGEN2_SEGEN2_DEFAULT << 0) /**< Shifted mode DEFAULT for LCD_SEGEN2 */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LCD */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
781
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h
vendored
Normal file
781
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma.h
vendored
Normal file
@ -0,0 +1,781 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LDMA register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LDMA LDMA
|
||||
* @{
|
||||
* @brief EFM32GG11B_LDMA Register Declaration
|
||||
******************************************************************************/
|
||||
/** LDMA Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< DMA Control Register */
|
||||
__IM uint32_t STATUS; /**< DMA Status Register */
|
||||
__IOM uint32_t SYNC; /**< DMA Synchronization Trigger Register (Single-Cycle RMW) */
|
||||
uint32_t RESERVED0[5U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t CHEN; /**< DMA Channel Enable Register (Single-Cycle RMW) */
|
||||
__IM uint32_t CHBUSY; /**< DMA Channel Busy Register */
|
||||
__IOM uint32_t CHDONE; /**< DMA Channel Linking Done Register (Single-Cycle RMW) */
|
||||
__IOM uint32_t DBGHALT; /**< DMA Channel Debug Halt Register */
|
||||
__IOM uint32_t SWREQ; /**< DMA Channel Software Transfer Request Register */
|
||||
__IOM uint32_t REQDIS; /**< DMA Channel Request Disable Register */
|
||||
__IM uint32_t REQPEND; /**< DMA Channel Requests Pending Register */
|
||||
__IOM uint32_t LINKLOAD; /**< DMA Channel Link Load Register */
|
||||
__IOM uint32_t REQCLEAR; /**< DMA Channel Request Clear Register */
|
||||
uint32_t RESERVED1[7U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED2[4U]; /**< Reserved registers */
|
||||
LDMA_CH_TypeDef CH[24U]; /**< DMA Channel Registers */
|
||||
} LDMA_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LDMA
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LDMA_BitFields LDMA Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LDMA CTRL */
|
||||
#define _LDMA_CTRL_RESETVALUE 0x17000000UL /**< Default value for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_MASK 0x1F00FFFFUL /**< Mask for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_SHIFT 0 /**< Shift value for LDMA_SYNCPRSSETEN */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_MASK 0xFFUL /**< Bit mask for LDMA_SYNCPRSSETEN */
|
||||
#define _LDMA_CTRL_SYNCPRSSETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_SYNCPRSSETEN_DEFAULT (_LDMA_CTRL_SYNCPRSSETEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_SHIFT 8 /**< Shift value for LDMA_SYNCPRSCLREN */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_MASK 0xFF00UL /**< Bit mask for LDMA_SYNCPRSCLREN */
|
||||
#define _LDMA_CTRL_SYNCPRSCLREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_SYNCPRSCLREN_DEFAULT (_LDMA_CTRL_SYNCPRSCLREN_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
#define _LDMA_CTRL_NUMFIXED_SHIFT 24 /**< Shift value for LDMA_NUMFIXED */
|
||||
#define _LDMA_CTRL_NUMFIXED_MASK 0x1F000000UL /**< Bit mask for LDMA_NUMFIXED */
|
||||
#define _LDMA_CTRL_NUMFIXED_DEFAULT 0x00000017UL /**< Mode DEFAULT for LDMA_CTRL */
|
||||
#define LDMA_CTRL_NUMFIXED_DEFAULT (_LDMA_CTRL_NUMFIXED_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CTRL */
|
||||
|
||||
/* Bit fields for LDMA STATUS */
|
||||
#define _LDMA_STATUS_RESETVALUE 0x18100000UL /**< Default value for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_MASK 0x1F1F1FFBUL /**< Mask for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYBUSY (0x1UL << 0) /**< Any DMA Channel Busy */
|
||||
#define _LDMA_STATUS_ANYBUSY_SHIFT 0 /**< Shift value for LDMA_ANYBUSY */
|
||||
#define _LDMA_STATUS_ANYBUSY_MASK 0x1UL /**< Bit mask for LDMA_ANYBUSY */
|
||||
#define _LDMA_STATUS_ANYBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYBUSY_DEFAULT (_LDMA_STATUS_ANYBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYREQ (0x1UL << 1) /**< Any DMA Channel Request Pending */
|
||||
#define _LDMA_STATUS_ANYREQ_SHIFT 1 /**< Shift value for LDMA_ANYREQ */
|
||||
#define _LDMA_STATUS_ANYREQ_MASK 0x2UL /**< Bit mask for LDMA_ANYREQ */
|
||||
#define _LDMA_STATUS_ANYREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_ANYREQ_DEFAULT (_LDMA_STATUS_ANYREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHGRANT_SHIFT 3 /**< Shift value for LDMA_CHGRANT */
|
||||
#define _LDMA_STATUS_CHGRANT_MASK 0xF8UL /**< Bit mask for LDMA_CHGRANT */
|
||||
#define _LDMA_STATUS_CHGRANT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHGRANT_DEFAULT (_LDMA_STATUS_CHGRANT_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHERROR_SHIFT 8 /**< Shift value for LDMA_CHERROR */
|
||||
#define _LDMA_STATUS_CHERROR_MASK 0x1F00UL /**< Bit mask for LDMA_CHERROR */
|
||||
#define _LDMA_STATUS_CHERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHERROR_DEFAULT (_LDMA_STATUS_CHERROR_DEFAULT << 8) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_SHIFT 16 /**< Shift value for LDMA_FIFOLEVEL */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_MASK 0x1F0000UL /**< Bit mask for LDMA_FIFOLEVEL */
|
||||
#define _LDMA_STATUS_FIFOLEVEL_DEFAULT 0x00000010UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_FIFOLEVEL_DEFAULT (_LDMA_STATUS_FIFOLEVEL_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
#define _LDMA_STATUS_CHNUM_SHIFT 24 /**< Shift value for LDMA_CHNUM */
|
||||
#define _LDMA_STATUS_CHNUM_MASK 0x1F000000UL /**< Bit mask for LDMA_CHNUM */
|
||||
#define _LDMA_STATUS_CHNUM_DEFAULT 0x00000018UL /**< Mode DEFAULT for LDMA_STATUS */
|
||||
#define LDMA_STATUS_CHNUM_DEFAULT (_LDMA_STATUS_CHNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_STATUS */
|
||||
|
||||
/* Bit fields for LDMA SYNC */
|
||||
#define _LDMA_SYNC_RESETVALUE 0x00000000UL /**< Default value for LDMA_SYNC */
|
||||
#define _LDMA_SYNC_MASK 0x000000FFUL /**< Mask for LDMA_SYNC */
|
||||
#define _LDMA_SYNC_SYNCTRIG_SHIFT 0 /**< Shift value for LDMA_SYNCTRIG */
|
||||
#define _LDMA_SYNC_SYNCTRIG_MASK 0xFFUL /**< Bit mask for LDMA_SYNCTRIG */
|
||||
#define _LDMA_SYNC_SYNCTRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SYNC */
|
||||
#define LDMA_SYNC_SYNCTRIG_DEFAULT (_LDMA_SYNC_SYNCTRIG_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SYNC */
|
||||
|
||||
/* Bit fields for LDMA CHEN */
|
||||
#define _LDMA_CHEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_SHIFT 0 /**< Shift value for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHEN */
|
||||
#define _LDMA_CHEN_CHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHEN */
|
||||
#define LDMA_CHEN_CHEN_DEFAULT (_LDMA_CHEN_CHEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHEN */
|
||||
|
||||
/* Bit fields for LDMA CHBUSY */
|
||||
#define _LDMA_CHBUSY_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHBUSY */
|
||||
#define _LDMA_CHBUSY_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHBUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_SHIFT 0 /**< Shift value for LDMA_BUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_MASK 0xFFFFFFUL /**< Bit mask for LDMA_BUSY */
|
||||
#define _LDMA_CHBUSY_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHBUSY */
|
||||
#define LDMA_CHBUSY_BUSY_DEFAULT (_LDMA_CHBUSY_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHBUSY */
|
||||
|
||||
/* Bit fields for LDMA CHDONE */
|
||||
#define _LDMA_CHDONE_RESETVALUE 0x00000000UL /**< Default value for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_MASK 0x00FFFFFFUL /**< Mask for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_SHIFT 0 /**< Shift value for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_CHDONE */
|
||||
#define _LDMA_CHDONE_CHDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CHDONE */
|
||||
#define LDMA_CHDONE_CHDONE_DEFAULT (_LDMA_CHDONE_CHDONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CHDONE */
|
||||
|
||||
/* Bit fields for LDMA DBGHALT */
|
||||
#define _LDMA_DBGHALT_RESETVALUE 0x00000000UL /**< Default value for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_MASK 0x00FFFFFFUL /**< Mask for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_SHIFT 0 /**< Shift value for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DBGHALT */
|
||||
#define _LDMA_DBGHALT_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_DBGHALT */
|
||||
#define LDMA_DBGHALT_DBGHALT_DEFAULT (_LDMA_DBGHALT_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_DBGHALT */
|
||||
|
||||
/* Bit fields for LDMA SWREQ */
|
||||
#define _LDMA_SWREQ_RESETVALUE 0x00000000UL /**< Default value for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_MASK 0x00FFFFFFUL /**< Mask for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_SHIFT 0 /**< Shift value for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_MASK 0xFFFFFFUL /**< Bit mask for LDMA_SWREQ */
|
||||
#define _LDMA_SWREQ_SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_SWREQ */
|
||||
#define LDMA_SWREQ_SWREQ_DEFAULT (_LDMA_SWREQ_SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_SWREQ */
|
||||
|
||||
/* Bit fields for LDMA REQDIS */
|
||||
#define _LDMA_REQDIS_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_SHIFT 0 /**< Shift value for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQDIS */
|
||||
#define _LDMA_REQDIS_REQDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQDIS */
|
||||
#define LDMA_REQDIS_REQDIS_DEFAULT (_LDMA_REQDIS_REQDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQDIS */
|
||||
|
||||
/* Bit fields for LDMA REQPEND */
|
||||
#define _LDMA_REQPEND_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_SHIFT 0 /**< Shift value for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQPEND */
|
||||
#define _LDMA_REQPEND_REQPEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQPEND */
|
||||
#define LDMA_REQPEND_REQPEND_DEFAULT (_LDMA_REQPEND_REQPEND_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQPEND */
|
||||
|
||||
/* Bit fields for LDMA LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_RESETVALUE 0x00000000UL /**< Default value for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_MASK 0x00FFFFFFUL /**< Mask for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_SHIFT 0 /**< Shift value for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_MASK 0xFFFFFFUL /**< Bit mask for LDMA_LINKLOAD */
|
||||
#define _LDMA_LINKLOAD_LINKLOAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_LINKLOAD */
|
||||
#define LDMA_LINKLOAD_LINKLOAD_DEFAULT (_LDMA_LINKLOAD_LINKLOAD_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_LINKLOAD */
|
||||
|
||||
/* Bit fields for LDMA REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_RESETVALUE 0x00000000UL /**< Default value for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_MASK 0x00FFFFFFUL /**< Mask for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_SHIFT 0 /**< Shift value for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_MASK 0xFFFFFFUL /**< Bit mask for LDMA_REQCLEAR */
|
||||
#define _LDMA_REQCLEAR_REQCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_REQCLEAR */
|
||||
#define LDMA_REQCLEAR_REQCLEAR_DEFAULT (_LDMA_REQCLEAR_REQCLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_REQCLEAR */
|
||||
|
||||
/* Bit fields for LDMA IF */
|
||||
#define _LDMA_IF_RESETVALUE 0x00000000UL /**< Default value for LDMA_IF */
|
||||
#define _LDMA_IF_MASK 0x80FFFFFFUL /**< Mask for LDMA_IF */
|
||||
#define _LDMA_IF_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IF_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_DONE_DEFAULT (_LDMA_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_ERROR (0x1UL << 31) /**< Transfer Error Interrupt Flag */
|
||||
#define _LDMA_IF_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IF_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IF_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IF */
|
||||
#define LDMA_IF_ERROR_DEFAULT (_LDMA_IF_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IF */
|
||||
|
||||
/* Bit fields for LDMA IFS */
|
||||
#define _LDMA_IFS_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFS */
|
||||
#define _LDMA_IFS_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFS */
|
||||
#define _LDMA_IFS_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IFS_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_DONE_DEFAULT (_LDMA_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_ERROR (0x1UL << 31) /**< Set ERROR Interrupt Flag */
|
||||
#define _LDMA_IFS_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IFS_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IFS_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFS */
|
||||
#define LDMA_IFS_ERROR_DEFAULT (_LDMA_IFS_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFS */
|
||||
|
||||
/* Bit fields for LDMA IFC */
|
||||
#define _LDMA_IFC_RESETVALUE 0x00000000UL /**< Default value for LDMA_IFC */
|
||||
#define _LDMA_IFC_MASK 0x80FFFFFFUL /**< Mask for LDMA_IFC */
|
||||
#define _LDMA_IFC_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IFC_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_DONE_DEFAULT (_LDMA_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_ERROR (0x1UL << 31) /**< Clear ERROR Interrupt Flag */
|
||||
#define _LDMA_IFC_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IFC_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IFC_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IFC */
|
||||
#define LDMA_IFC_ERROR_DEFAULT (_LDMA_IFC_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IFC */
|
||||
|
||||
/* Bit fields for LDMA IEN */
|
||||
#define _LDMA_IEN_RESETVALUE 0x00000000UL /**< Default value for LDMA_IEN */
|
||||
#define _LDMA_IEN_MASK 0x80FFFFFFUL /**< Mask for LDMA_IEN */
|
||||
#define _LDMA_IEN_DONE_SHIFT 0 /**< Shift value for LDMA_DONE */
|
||||
#define _LDMA_IEN_DONE_MASK 0xFFFFFFUL /**< Bit mask for LDMA_DONE */
|
||||
#define _LDMA_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_DONE_DEFAULT (_LDMA_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_ERROR (0x1UL << 31) /**< ERROR Interrupt Enable */
|
||||
#define _LDMA_IEN_ERROR_SHIFT 31 /**< Shift value for LDMA_ERROR */
|
||||
#define _LDMA_IEN_ERROR_MASK 0x80000000UL /**< Bit mask for LDMA_ERROR */
|
||||
#define _LDMA_IEN_ERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_IEN */
|
||||
#define LDMA_IEN_ERROR_DEFAULT (_LDMA_IEN_ERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_IEN */
|
||||
|
||||
/* Bit fields for LDMA CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_MASK 0x003F000FUL /**< Mask for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_SHIFT 0 /**< Shift value for LDMA_SIGSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_MASK 0xFUL /**< Bit mask for LDMA_SIGSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ0 0x00000000UL /**< Mode PRSREQ0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE 0x00000000UL /**< Mode ADC1SINGLE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 0x00000000UL /**< Mode VDAC0CH0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV 0x00000000UL /**< Mode USART3RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV 0x00000000UL /**< Mode USART4RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV 0x00000000UL /**< Mode USART5RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV 0x00000000UL /**< Mode UART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV 0x00000000UL /**< Mode UART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV 0x00000000UL /**< Mode I2C2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF 0x00000000UL /**< Mode TIMER4UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF 0x00000000UL /**< Mode TIMER5UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF 0x00000000UL /**< Mode TIMER6UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF 0x00000000UL /**< Mode WTIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF 0x00000000UL /**< Mode WTIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF 0x00000000UL /**< Mode WTIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF 0x00000000UL /**< Mode WTIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR 0x00000000UL /**< Mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY 0x00000000UL /**< Mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CSENDATA 0x00000000UL /**< Mode CSENDATA for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_PRSREQ1 0x00000001UL /**< Mode PRSREQ1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_ADC1SCAN 0x00000001UL /**< Mode ADC1SCAN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 0x00000001UL /**< Mode VDAC0CH1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBL 0x00000001UL /**< Mode USART3TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBL 0x00000001UL /**< Mode USART4TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5TXBL 0x00000001UL /**< Mode USART5TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0TXBL 0x00000001UL /**< Mode UART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1TXBL 0x00000001UL /**< Mode UART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_I2C2TXBL 0x00000001UL /**< Mode I2C2TXBL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 0x00000001UL /**< Mode TIMER4CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 0x00000001UL /**< Mode TIMER5CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 0x00000001UL /**< Mode TIMER6CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 0x00000001UL /**< Mode WTIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 0x00000001UL /**< Mode WTIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 0x00000001UL /**< Mode WTIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 0x00000001UL /**< Mode WTIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR 0x00000001UL /**< Mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY 0x00000001UL /**< Mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CSENBSLN 0x00000001UL /**< Mode CSENBSLN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY 0x00000002UL /**< Mode USART3TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY 0x00000002UL /**< Mode USART4TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY 0x00000002UL /**< Mode USART5TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY 0x00000002UL /**< Mode UART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY 0x00000002UL /**< Mode UART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 0x00000002UL /**< Mode TIMER4CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 0x00000002UL /**< Mode TIMER5CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 0x00000002UL /**< Mode TIMER6CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 0x00000002UL /**< Mode WTIMER0CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 0x00000002UL /**< Mode WTIMER1CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 0x00000002UL /**< Mode WTIMER2CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 0x00000002UL /**< Mode WTIMER3CC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD 0x00000002UL /**< Mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL 0x00000002UL /**< Mode EBIPXLFULL for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT 0x00000003UL /**< Mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT 0x00000003UL /**< Mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 0x00000003UL /**< Mode TIMER4CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 0x00000003UL /**< Mode TIMER5CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 0x00000003UL /**< Mode TIMER6CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 0x00000003UL /**< Mode WTIMER0CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 0x00000003UL /**< Mode WTIMER1CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 0x00000003UL /**< Mode WTIMER2CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 0x00000003UL /**< Mode WTIMER3CC2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR 0x00000003UL /**< Mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY 0x00000003UL /**< Mode EBIDDEMPTY for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT 0x00000004UL /**< Mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT 0x00000004UL /**< Mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 0x00000004UL /**< Mode TIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 0x00000004UL /**< Mode WTIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD 0x00000004UL /**< Mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIVSYNC 0x00000004UL /**< Mode EBIVSYNC for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SIGSEL_EBIHSYNC 0x00000005UL /**< Mode EBIHSYNC for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ0 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ0 << 0) /**< Shifted mode PRSREQ0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE (_LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE << 0) /**< Shifted mode ADC1SINGLE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 << 0) /**< Shifted mode VDAC0CH0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV << 0) /**< Shifted mode USART3RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV << 0) /**< Shifted mode USART4RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV (_LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV << 0) /**< Shifted mode USART5RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV << 0) /**< Shifted mode UART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV << 0) /**< Shifted mode UART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV (_LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV << 0) /**< Shifted mode I2C2RXDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF << 0) /**< Shifted mode TIMER4UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF << 0) /**< Shifted mode TIMER5UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF (_LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF << 0) /**< Shifted mode TIMER6UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF << 0) /**< Shifted mode WTIMER0UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF << 0) /**< Shifted mode WTIMER1UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF << 0) /**< Shifted mode WTIMER2UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF (_LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF << 0) /**< Shifted mode WTIMER3UFOF for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_MSCWDATA (_LDMA_CH_REQSEL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR << 0) /**< Shifted mode CRYPTO0DATA0WR for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY << 0) /**< Shifted mode EBIPXL0EMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CSENDATA (_LDMA_CH_REQSEL_SIGSEL_CSENDATA << 0) /**< Shifted mode CSENDATA for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV (_LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_PRSREQ1 (_LDMA_CH_REQSEL_SIGSEL_PRSREQ1 << 0) /**< Shifted mode PRSREQ1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_ADC0SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_ADC1SCAN (_LDMA_CH_REQSEL_SIGSEL_ADC1SCAN << 0) /**< Shifted mode ADC1SCAN for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 (_LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 << 0) /**< Shifted mode VDAC0CH1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART0TXBL (_LDMA_CH_REQSEL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBL (_LDMA_CH_REQSEL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART2TXBL (_LDMA_CH_REQSEL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3TXBL (_LDMA_CH_REQSEL_SIGSEL_USART3TXBL << 0) /**< Shifted mode USART3TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4TXBL (_LDMA_CH_REQSEL_SIGSEL_USART4TXBL << 0) /**< Shifted mode USART4TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART5TXBL (_LDMA_CH_REQSEL_SIGSEL_USART5TXBL << 0) /**< Shifted mode USART5TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART0TXBL (_LDMA_CH_REQSEL_SIGSEL_UART0TXBL << 0) /**< Shifted mode UART0TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART1TXBL (_LDMA_CH_REQSEL_SIGSEL_UART1TXBL << 0) /**< Shifted mode UART1TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C0TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C1TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_I2C2TXBL (_LDMA_CH_REQSEL_SIGSEL_I2C2TXBL << 0) /**< Shifted mode I2C2TXBL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 << 0) /**< Shifted mode TIMER4CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 << 0) /**< Shifted mode TIMER5CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 << 0) /**< Shifted mode TIMER6CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 << 0) /**< Shifted mode WTIMER0CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 << 0) /**< Shifted mode WTIMER1CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 << 0) /**< Shifted mode WTIMER2CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 << 0) /**< Shifted mode WTIMER3CC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR << 0) /**< Shifted mode CRYPTO0DATA0XWR for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY << 0) /**< Shifted mode EBIPXL1EMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CSENBSLN (_LDMA_CH_REQSEL_SIGSEL_CSENBSLN << 0) /**< Shifted mode CSENBSLN for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY << 0) /**< Shifted mode USART3TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY << 0) /**< Shifted mode USART4TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY << 0) /**< Shifted mode USART5TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY << 0) /**< Shifted mode UART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY << 0) /**< Shifted mode UART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY (_LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 << 0) /**< Shifted mode TIMER4CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 << 0) /**< Shifted mode TIMER5CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 << 0) /**< Shifted mode TIMER6CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 << 0) /**< Shifted mode WTIMER0CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 << 0) /**< Shifted mode WTIMER1CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 << 0) /**< Shifted mode WTIMER2CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 << 0) /**< Shifted mode WTIMER3CC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD << 0) /**< Shifted mode CRYPTO0DATA0RD for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL (_LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL << 0) /**< Shifted mode EBIPXLFULL for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT << 0) /**< Shifted mode USART3RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT << 0) /**< Shifted mode USART4RXDATAVRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 << 0) /**< Shifted mode TIMER4CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 << 0) /**< Shifted mode TIMER5CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 (_LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 << 0) /**< Shifted mode TIMER6CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 << 0) /**< Shifted mode WTIMER0CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 << 0) /**< Shifted mode WTIMER1CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 << 0) /**< Shifted mode WTIMER2CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 (_LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 << 0) /**< Shifted mode WTIMER3CC2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR << 0) /**< Shifted mode CRYPTO0DATA1WR for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY (_LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY << 0) /**< Shifted mode EBIDDEMPTY for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT << 0) /**< Shifted mode USART3TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT (_LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT << 0) /**< Shifted mode USART4TXBLRIGHT for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 << 0) /**< Shifted mode TIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 (_LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 << 0) /**< Shifted mode WTIMER1CC3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD (_LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD << 0) /**< Shifted mode CRYPTO0DATA1RD for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIVSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIVSYNC << 0) /**< Shifted mode EBIVSYNC for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SIGSEL_EBIHSYNC (_LDMA_CH_REQSEL_SIGSEL_EBIHSYNC << 0) /**< Shifted mode EBIHSYNC for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_SHIFT 16 /**< Shift value for LDMA_SOURCESEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for LDMA_SOURCESEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_PRS 0x00000001UL /**< Mode PRS for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_ADC1 0x00000009UL /**< Mode ADC1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_VDAC0 0x0000000AUL /**< Mode VDAC0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART3 0x0000000FUL /**< Mode USART3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART4 0x00000010UL /**< Mode USART4 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_USART5 0x00000011UL /**< Mode USART5 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_UART0 0x00000012UL /**< Mode UART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_UART1 0x00000013UL /**< Mode UART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LEUART0 0x00000014UL /**< Mode LEUART0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LEUART1 0x00000015UL /**< Mode LEUART1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C0 0x00000016UL /**< Mode I2C0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C1 0x00000017UL /**< Mode I2C1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_I2C2 0x00000018UL /**< Mode I2C2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER0 0x00000019UL /**< Mode TIMER0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER1 0x0000001AUL /**< Mode TIMER1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER2 0x0000001BUL /**< Mode TIMER2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER3 0x0000001CUL /**< Mode TIMER3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER4 0x0000001DUL /**< Mode TIMER4 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER5 0x0000001EUL /**< Mode TIMER5 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_TIMER6 0x0000001FUL /**< Mode TIMER6 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER0 0x00000020UL /**< Mode WTIMER0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER1 0x00000021UL /**< Mode WTIMER1 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER2 0x00000022UL /**< Mode WTIMER2 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_WTIMER3 0x00000023UL /**< Mode WTIMER3 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 0x00000031UL /**< Mode CRYPTO0 for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_EBI 0x00000032UL /**< Mode EBI for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_CSEN 0x0000003DUL /**< Mode CSEN for LDMA_CH_REQSEL */
|
||||
#define _LDMA_CH_REQSEL_SOURCESEL_LESENSE 0x0000003EUL /**< Mode LESENSE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_NONE (_LDMA_CH_REQSEL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_PRS (_LDMA_CH_REQSEL_SOURCESEL_PRS << 16) /**< Shifted mode PRS for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_ADC0 (_LDMA_CH_REQSEL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_ADC1 (_LDMA_CH_REQSEL_SOURCESEL_ADC1 << 16) /**< Shifted mode ADC1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_VDAC0 (_LDMA_CH_REQSEL_SOURCESEL_VDAC0 << 16) /**< Shifted mode VDAC0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART0 (_LDMA_CH_REQSEL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART1 (_LDMA_CH_REQSEL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART2 (_LDMA_CH_REQSEL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART3 (_LDMA_CH_REQSEL_SOURCESEL_USART3 << 16) /**< Shifted mode USART3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART4 (_LDMA_CH_REQSEL_SOURCESEL_USART4 << 16) /**< Shifted mode USART4 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_USART5 (_LDMA_CH_REQSEL_SOURCESEL_USART5 << 16) /**< Shifted mode USART5 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_UART0 (_LDMA_CH_REQSEL_SOURCESEL_UART0 << 16) /**< Shifted mode UART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_UART1 (_LDMA_CH_REQSEL_SOURCESEL_UART1 << 16) /**< Shifted mode UART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LEUART0 (_LDMA_CH_REQSEL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LEUART1 (_LDMA_CH_REQSEL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C0 (_LDMA_CH_REQSEL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C1 (_LDMA_CH_REQSEL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_I2C2 (_LDMA_CH_REQSEL_SOURCESEL_I2C2 << 16) /**< Shifted mode I2C2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER0 (_LDMA_CH_REQSEL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER1 (_LDMA_CH_REQSEL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER2 (_LDMA_CH_REQSEL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER3 (_LDMA_CH_REQSEL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER4 (_LDMA_CH_REQSEL_SOURCESEL_TIMER4 << 16) /**< Shifted mode TIMER4 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER5 (_LDMA_CH_REQSEL_SOURCESEL_TIMER5 << 16) /**< Shifted mode TIMER5 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_TIMER6 (_LDMA_CH_REQSEL_SOURCESEL_TIMER6 << 16) /**< Shifted mode TIMER6 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER0 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER0 << 16) /**< Shifted mode WTIMER0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER1 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER1 << 16) /**< Shifted mode WTIMER1 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER2 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER2 << 16) /**< Shifted mode WTIMER2 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_WTIMER3 (_LDMA_CH_REQSEL_SOURCESEL_WTIMER3 << 16) /**< Shifted mode WTIMER3 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_MSC (_LDMA_CH_REQSEL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 (_LDMA_CH_REQSEL_SOURCESEL_CRYPTO0 << 16) /**< Shifted mode CRYPTO0 for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_EBI (_LDMA_CH_REQSEL_SOURCESEL_EBI << 16) /**< Shifted mode EBI for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_CSEN (_LDMA_CH_REQSEL_SOURCESEL_CSEN << 16) /**< Shifted mode CSEN for LDMA_CH_REQSEL */
|
||||
#define LDMA_CH_REQSEL_SOURCESEL_LESENSE (_LDMA_CH_REQSEL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for LDMA_CH_REQSEL */
|
||||
|
||||
/* Bit fields for LDMA CH_CFG */
|
||||
#define _LDMA_CH_CFG_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_MASK 0x00330000UL /**< Mask for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_SHIFT 16 /**< Shift value for LDMA_ARBSLOTS */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_MASK 0x30000UL /**< Bit mask for LDMA_ARBSLOTS */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_ARBSLOTS_EIGHT 0x00000003UL /**< Mode EIGHT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_DEFAULT (_LDMA_CH_CFG_ARBSLOTS_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_ONE (_LDMA_CH_CFG_ARBSLOTS_ONE << 16) /**< Shifted mode ONE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_TWO (_LDMA_CH_CFG_ARBSLOTS_TWO << 16) /**< Shifted mode TWO for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_FOUR (_LDMA_CH_CFG_ARBSLOTS_FOUR << 16) /**< Shifted mode FOUR for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_ARBSLOTS_EIGHT (_LDMA_CH_CFG_ARBSLOTS_EIGHT << 16) /**< Shifted mode EIGHT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN (0x1UL << 20) /**< Source Address Increment Sign */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_SHIFT 20 /**< Shift value for LDMA_SRCINCSIGN */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_MASK 0x100000UL /**< Bit mask for LDMA_SRCINCSIGN */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_DEFAULT (_LDMA_CH_CFG_SRCINCSIGN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_POSITIVE (_LDMA_CH_CFG_SRCINCSIGN_POSITIVE << 20) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_SRCINCSIGN_NEGATIVE (_LDMA_CH_CFG_SRCINCSIGN_NEGATIVE << 20) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN (0x1UL << 21) /**< Destination Address Increment Sign */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_SHIFT 21 /**< Shift value for LDMA_DSTINCSIGN */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_MASK 0x200000UL /**< Bit mask for LDMA_DSTINCSIGN */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_POSITIVE 0x00000000UL /**< Mode POSITIVE for LDMA_CH_CFG */
|
||||
#define _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE 0x00000001UL /**< Mode NEGATIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_DEFAULT (_LDMA_CH_CFG_DSTINCSIGN_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_POSITIVE (_LDMA_CH_CFG_DSTINCSIGN_POSITIVE << 21) /**< Shifted mode POSITIVE for LDMA_CH_CFG */
|
||||
#define LDMA_CH_CFG_DSTINCSIGN_NEGATIVE (_LDMA_CH_CFG_DSTINCSIGN_NEGATIVE << 21) /**< Shifted mode NEGATIVE for LDMA_CH_CFG */
|
||||
|
||||
/* Bit fields for LDMA CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_MASK 0x000000FFUL /**< Mask for LDMA_CH_LOOP */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_SHIFT 0 /**< Shift value for LDMA_LOOPCNT */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_MASK 0xFFUL /**< Bit mask for LDMA_LOOPCNT */
|
||||
#define _LDMA_CH_LOOP_LOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LOOP */
|
||||
#define LDMA_CH_LOOP_LOOPCNT_DEFAULT (_LDMA_CH_LOOP_LOOPCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LOOP */
|
||||
|
||||
/* Bit fields for LDMA CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_MASK 0xFFFFFFFBUL /**< Mask for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_SHIFT 0 /**< Shift value for LDMA_STRUCTTYPE */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_MASK 0x3UL /**< Bit mask for LDMA_STRUCTTYPE */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER 0x00000000UL /**< Mode TRANSFER for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE 0x00000001UL /**< Mode SYNCHRONIZE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_STRUCTTYPE_WRITE 0x00000002UL /**< Mode WRITE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_DEFAULT (_LDMA_CH_CTRL_STRUCTTYPE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_TRANSFER (_LDMA_CH_CTRL_STRUCTTYPE_TRANSFER << 0) /**< Shifted mode TRANSFER for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE (_LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE << 0) /**< Shifted mode SYNCHRONIZE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTTYPE_WRITE (_LDMA_CH_CTRL_STRUCTTYPE_WRITE << 0) /**< Shifted mode WRITE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTREQ (0x1UL << 3) /**< Structure DMA Transfer Request */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_SHIFT 3 /**< Shift value for LDMA_STRUCTREQ */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_MASK 0x8UL /**< Bit mask for LDMA_STRUCTREQ */
|
||||
#define _LDMA_CH_CTRL_STRUCTREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_STRUCTREQ_DEFAULT (_LDMA_CH_CTRL_STRUCTREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_SHIFT 4 /**< Shift value for LDMA_XFERCNT */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_MASK 0x7FF0UL /**< Bit mask for LDMA_XFERCNT */
|
||||
#define _LDMA_CH_CTRL_XFERCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_XFERCNT_DEFAULT (_LDMA_CH_CTRL_XFERCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BYTESWAP (0x1UL << 15) /**< Endian Byte Swap */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_SHIFT 15 /**< Shift value for LDMA_BYTESWAP */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_MASK 0x8000UL /**< Bit mask for LDMA_BYTESWAP */
|
||||
#define _LDMA_CH_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BYTESWAP_DEFAULT (_LDMA_CH_CTRL_BYTESWAP_DEFAULT << 15) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_SHIFT 16 /**< Shift value for LDMA_BLOCKSIZE */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_MASK 0xF0000UL /**< Bit mask for LDMA_BLOCKSIZE */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1 0x00000000UL /**< Mode UNIT1 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT2 0x00000001UL /**< Mode UNIT2 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT3 0x00000002UL /**< Mode UNIT3 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT4 0x00000003UL /**< Mode UNIT4 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT6 0x00000004UL /**< Mode UNIT6 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT8 0x00000005UL /**< Mode UNIT8 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT16 0x00000007UL /**< Mode UNIT16 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT32 0x00000009UL /**< Mode UNIT32 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT64 0x0000000AUL /**< Mode UNIT64 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT128 0x0000000BUL /**< Mode UNIT128 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT256 0x0000000CUL /**< Mode UNIT256 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT512 0x0000000DUL /**< Mode UNIT512 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 0x0000000EUL /**< Mode UNIT1024 for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_BLOCKSIZE_ALL 0x0000000FUL /**< Mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_DEFAULT (_LDMA_CH_CTRL_BLOCKSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1 << 16) /**< Shifted mode UNIT1 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT2 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT2 << 16) /**< Shifted mode UNIT2 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT3 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT3 << 16) /**< Shifted mode UNIT3 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT4 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT4 << 16) /**< Shifted mode UNIT4 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT6 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT6 << 16) /**< Shifted mode UNIT6 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT8 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT8 << 16) /**< Shifted mode UNIT8 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT16 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT16 << 16) /**< Shifted mode UNIT16 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT32 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT32 << 16) /**< Shifted mode UNIT32 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT64 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT64 << 16) /**< Shifted mode UNIT64 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT128 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT128 << 16) /**< Shifted mode UNIT128 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT256 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT256 << 16) /**< Shifted mode UNIT256 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT512 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT512 << 16) /**< Shifted mode UNIT512 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 (_LDMA_CH_CTRL_BLOCKSIZE_UNIT1024 << 16) /**< Shifted mode UNIT1024 for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_BLOCKSIZE_ALL (_LDMA_CH_CTRL_BLOCKSIZE_ALL << 16) /**< Shifted mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DONEIFSEN (0x1UL << 20) /**< DMA Operation Done Interrupt Flag Set Enable */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_SHIFT 20 /**< Shift value for LDMA_DONEIFSEN */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_MASK 0x100000UL /**< Bit mask for LDMA_DONEIFSEN */
|
||||
#define _LDMA_CH_CTRL_DONEIFSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DONEIFSEN_DEFAULT (_LDMA_CH_CTRL_DONEIFSEN_DEFAULT << 20) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE (0x1UL << 21) /**< DMA Request Transfer Mode Select */
|
||||
#define _LDMA_CH_CTRL_REQMODE_SHIFT 21 /**< Shift value for LDMA_REQMODE */
|
||||
#define _LDMA_CH_CTRL_REQMODE_MASK 0x200000UL /**< Bit mask for LDMA_REQMODE */
|
||||
#define _LDMA_CH_CTRL_REQMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_REQMODE_BLOCK 0x00000000UL /**< Mode BLOCK for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_REQMODE_ALL 0x00000001UL /**< Mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_DEFAULT (_LDMA_CH_CTRL_REQMODE_DEFAULT << 21) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_BLOCK (_LDMA_CH_CTRL_REQMODE_BLOCK << 21) /**< Shifted mode BLOCK for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_REQMODE_ALL (_LDMA_CH_CTRL_REQMODE_ALL << 21) /**< Shifted mode ALL for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DECLOOPCNT (0x1UL << 22) /**< Decrement Loop Count */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_SHIFT 22 /**< Shift value for LDMA_DECLOOPCNT */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_MASK 0x400000UL /**< Bit mask for LDMA_DECLOOPCNT */
|
||||
#define _LDMA_CH_CTRL_DECLOOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DECLOOPCNT_DEFAULT (_LDMA_CH_CTRL_DECLOOPCNT_DEFAULT << 22) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_IGNORESREQ (0x1UL << 23) /**< Ignore Sreq */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_SHIFT 23 /**< Shift value for LDMA_IGNORESREQ */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_MASK 0x800000UL /**< Bit mask for LDMA_IGNORESREQ */
|
||||
#define _LDMA_CH_CTRL_IGNORESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_IGNORESREQ_DEFAULT (_LDMA_CH_CTRL_IGNORESREQ_DEFAULT << 23) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_SHIFT 24 /**< Shift value for LDMA_SRCINC */
|
||||
#define _LDMA_CH_CTRL_SRCINC_MASK 0x3000000UL /**< Bit mask for LDMA_SRCINC */
|
||||
#define _LDMA_CH_CTRL_SRCINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_DEFAULT (_LDMA_CH_CTRL_SRCINC_DEFAULT << 24) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_ONE (_LDMA_CH_CTRL_SRCINC_ONE << 24) /**< Shifted mode ONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_TWO (_LDMA_CH_CTRL_SRCINC_TWO << 24) /**< Shifted mode TWO for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_FOUR (_LDMA_CH_CTRL_SRCINC_FOUR << 24) /**< Shifted mode FOUR for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCINC_NONE (_LDMA_CH_CTRL_SRCINC_NONE << 24) /**< Shifted mode NONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_SHIFT 26 /**< Shift value for LDMA_SIZE */
|
||||
#define _LDMA_CH_CTRL_SIZE_MASK 0xC000000UL /**< Bit mask for LDMA_SIZE */
|
||||
#define _LDMA_CH_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_BYTE 0x00000000UL /**< Mode BYTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_HALFWORD 0x00000001UL /**< Mode HALFWORD for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SIZE_WORD 0x00000002UL /**< Mode WORD for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_DEFAULT (_LDMA_CH_CTRL_SIZE_DEFAULT << 26) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_BYTE (_LDMA_CH_CTRL_SIZE_BYTE << 26) /**< Shifted mode BYTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_HALFWORD (_LDMA_CH_CTRL_SIZE_HALFWORD << 26) /**< Shifted mode HALFWORD for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SIZE_WORD (_LDMA_CH_CTRL_SIZE_WORD << 26) /**< Shifted mode WORD for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_SHIFT 28 /**< Shift value for LDMA_DSTINC */
|
||||
#define _LDMA_CH_CTRL_DSTINC_MASK 0x30000000UL /**< Bit mask for LDMA_DSTINC */
|
||||
#define _LDMA_CH_CTRL_DSTINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_ONE 0x00000000UL /**< Mode ONE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_TWO 0x00000001UL /**< Mode TWO for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_FOUR 0x00000002UL /**< Mode FOUR for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTINC_NONE 0x00000003UL /**< Mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_DEFAULT (_LDMA_CH_CTRL_DSTINC_DEFAULT << 28) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_ONE (_LDMA_CH_CTRL_DSTINC_ONE << 28) /**< Shifted mode ONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_TWO (_LDMA_CH_CTRL_DSTINC_TWO << 28) /**< Shifted mode TWO for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_FOUR (_LDMA_CH_CTRL_DSTINC_FOUR << 28) /**< Shifted mode FOUR for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTINC_NONE (_LDMA_CH_CTRL_DSTINC_NONE << 28) /**< Shifted mode NONE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE (0x1UL << 30) /**< Source Addressing Mode */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_SHIFT 30 /**< Shift value for LDMA_SRCMODE */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_MASK 0x40000000UL /**< Bit mask for LDMA_SRCMODE */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_SRCMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_DEFAULT (_LDMA_CH_CTRL_SRCMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_ABSOLUTE (_LDMA_CH_CTRL_SRCMODE_ABSOLUTE << 30) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_SRCMODE_RELATIVE (_LDMA_CH_CTRL_SRCMODE_RELATIVE << 30) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE (0x1UL << 31) /**< Destination Addressing Mode */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_SHIFT 31 /**< Shift value for LDMA_DSTMODE */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_MASK 0x80000000UL /**< Bit mask for LDMA_DSTMODE */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define _LDMA_CH_CTRL_DSTMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_DEFAULT (_LDMA_CH_CTRL_DSTMODE_DEFAULT << 31) /**< Shifted mode DEFAULT for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_ABSOLUTE (_LDMA_CH_CTRL_DSTMODE_ABSOLUTE << 31) /**< Shifted mode ABSOLUTE for LDMA_CH_CTRL */
|
||||
#define LDMA_CH_CTRL_DSTMODE_RELATIVE (_LDMA_CH_CTRL_DSTMODE_RELATIVE << 31) /**< Shifted mode RELATIVE for LDMA_CH_CTRL */
|
||||
|
||||
/* Bit fields for LDMA CH_SRC */
|
||||
#define _LDMA_CH_SRC_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_SRC */
|
||||
#define _LDMA_CH_SRC_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_SRC */
|
||||
#define _LDMA_CH_SRC_SRCADDR_SHIFT 0 /**< Shift value for LDMA_SRCADDR */
|
||||
#define _LDMA_CH_SRC_SRCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_SRCADDR */
|
||||
#define _LDMA_CH_SRC_SRCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_SRC */
|
||||
#define LDMA_CH_SRC_SRCADDR_DEFAULT (_LDMA_CH_SRC_SRCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_SRC */
|
||||
|
||||
/* Bit fields for LDMA CH_DST */
|
||||
#define _LDMA_CH_DST_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_DST */
|
||||
#define _LDMA_CH_DST_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_DST */
|
||||
#define _LDMA_CH_DST_DSTADDR_SHIFT 0 /**< Shift value for LDMA_DSTADDR */
|
||||
#define _LDMA_CH_DST_DSTADDR_MASK 0xFFFFFFFFUL /**< Bit mask for LDMA_DSTADDR */
|
||||
#define _LDMA_CH_DST_DSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_DST */
|
||||
#define LDMA_CH_DST_DSTADDR_DEFAULT (_LDMA_CH_DST_DSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_DST */
|
||||
|
||||
/* Bit fields for LDMA CH_LINK */
|
||||
#define _LDMA_CH_LINK_RESETVALUE 0x00000000UL /**< Default value for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_MASK 0xFFFFFFFFUL /**< Mask for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE (0x1UL << 0) /**< Link Structure Addressing Mode */
|
||||
#define _LDMA_CH_LINK_LINKMODE_SHIFT 0 /**< Shift value for LDMA_LINKMODE */
|
||||
#define _LDMA_CH_LINK_LINKMODE_MASK 0x1UL /**< Bit mask for LDMA_LINKMODE */
|
||||
#define _LDMA_CH_LINK_LINKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKMODE_ABSOLUTE 0x00000000UL /**< Mode ABSOLUTE for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKMODE_RELATIVE 0x00000001UL /**< Mode RELATIVE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_DEFAULT (_LDMA_CH_LINK_LINKMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_ABSOLUTE (_LDMA_CH_LINK_LINKMODE_ABSOLUTE << 0) /**< Shifted mode ABSOLUTE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKMODE_RELATIVE (_LDMA_CH_LINK_LINKMODE_RELATIVE << 0) /**< Shifted mode RELATIVE for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINK (0x1UL << 1) /**< Link Next Structure */
|
||||
#define _LDMA_CH_LINK_LINK_SHIFT 1 /**< Shift value for LDMA_LINK */
|
||||
#define _LDMA_CH_LINK_LINK_MASK 0x2UL /**< Bit mask for LDMA_LINK */
|
||||
#define _LDMA_CH_LINK_LINK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINK_DEFAULT (_LDMA_CH_LINK_LINK_DEFAULT << 1) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
#define _LDMA_CH_LINK_LINKADDR_SHIFT 2 /**< Shift value for LDMA_LINKADDR */
|
||||
#define _LDMA_CH_LINK_LINKADDR_MASK 0xFFFFFFFCUL /**< Bit mask for LDMA_LINKADDR */
|
||||
#define _LDMA_CH_LINK_LINKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LDMA_CH_LINK */
|
||||
#define LDMA_CH_LINK_LINKADDR_DEFAULT (_LDMA_CH_LINK_LINKADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for LDMA_CH_LINK */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LDMA */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h
vendored
Normal file
65
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_ldma_ch.h
vendored
Normal file
@ -0,0 +1,65 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LDMA_CH register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief LDMA_CH LDMA CH Register
|
||||
* @ingroup EFM32GG11B_LDMA
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t REQSEL; /**< Channel Peripheral Request Select Register */
|
||||
__IOM uint32_t CFG; /**< Channel Configuration Register */
|
||||
__IOM uint32_t LOOP; /**< Channel Loop Counter Register */
|
||||
__IOM uint32_t CTRL; /**< Channel Descriptor Control Word Register */
|
||||
__IOM uint32_t SRC; /**< Channel Descriptor Source Data Address Register */
|
||||
__IOM uint32_t DST; /**< Channel Descriptor Destination Data Address Register */
|
||||
__IOM uint32_t LINK; /**< Channel Descriptor Link Structure Address Register */
|
||||
uint32_t RESERVED0[5U]; /**< Reserved future */
|
||||
} LDMA_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
2003
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h
vendored
Normal file
2003
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
58
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h
vendored
Normal file
58
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_buf.h
vendored
Normal file
@ -0,0 +1,58 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LESENSE_BUF register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief LESENSE_BUF LESENSE BUF Register
|
||||
* @ingroup EFM32GG11B_LESENSE
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t DATA; /**< Scan Results */
|
||||
} LESENSE_BUF_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
61
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h
vendored
Normal file
61
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_ch.h
vendored
Normal file
@ -0,0 +1,61 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LESENSE_CH register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief LESENSE_CH LESENSE CH Register
|
||||
* @ingroup EFM32GG11B_LESENSE
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t TIMING; /**< Scan Configuration */
|
||||
__IOM uint32_t INTERACT; /**< Scan Configuration */
|
||||
__IOM uint32_t EVAL; /**< Scan Configuration */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved future */
|
||||
} LESENSE_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
59
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h
vendored
Normal file
59
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_lesense_st.h
vendored
Normal file
@ -0,0 +1,59 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LESENSE_ST register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief LESENSE_ST LESENSE ST Register
|
||||
* @ingroup EFM32GG11B_LESENSE
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t TCONFA; /**< State Transition Configuration a */
|
||||
__IOM uint32_t TCONFB; /**< State Transition Configuration B */
|
||||
} LESENSE_ST_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
612
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h
vendored
Normal file
612
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_letimer.h
vendored
Normal file
@ -0,0 +1,612 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LETIMER register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LETIMER LETIMER
|
||||
* @{
|
||||
* @brief EFM32GG11B_LETIMER Register Declaration
|
||||
******************************************************************************/
|
||||
/** LETIMER Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CNT; /**< Counter Value Register */
|
||||
__IOM uint32_t COMP0; /**< Compare Value Register 0 */
|
||||
__IOM uint32_t COMP1; /**< Compare Value Register 1 */
|
||||
__IOM uint32_t REP0; /**< Repeat Counter Register 0 */
|
||||
__IOM uint32_t REP1; /**< Repeat Counter Register 1 */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED2[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t PRSSEL; /**< PRS Input Select Register */
|
||||
} LETIMER_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LETIMER
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LETIMER_BitFields LETIMER Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LETIMER CTRL */
|
||||
#define _LETIMER_CTRL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_MASK 0x000013FFUL /**< Mask for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_SHIFT 0 /**< Shift value for LETIMER_REPMODE */
|
||||
#define _LETIMER_CTRL_REPMODE_MASK 0x3UL /**< Bit mask for LETIMER_REPMODE */
|
||||
#define _LETIMER_CTRL_REPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_FREE 0x00000000UL /**< Mode FREE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_ONESHOT 0x00000001UL /**< Mode ONESHOT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_BUFFERED 0x00000002UL /**< Mode BUFFERED for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_REPMODE_DOUBLE 0x00000003UL /**< Mode DOUBLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_DEFAULT (_LETIMER_CTRL_REPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_FREE (_LETIMER_CTRL_REPMODE_FREE << 0) /**< Shifted mode FREE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_ONESHOT (_LETIMER_CTRL_REPMODE_ONESHOT << 0) /**< Shifted mode ONESHOT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_BUFFERED (_LETIMER_CTRL_REPMODE_BUFFERED << 0) /**< Shifted mode BUFFERED for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_REPMODE_DOUBLE (_LETIMER_CTRL_REPMODE_DOUBLE << 0) /**< Shifted mode DOUBLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_SHIFT 2 /**< Shift value for LETIMER_UFOA0 */
|
||||
#define _LETIMER_CTRL_UFOA0_MASK 0xCUL /**< Bit mask for LETIMER_UFOA0 */
|
||||
#define _LETIMER_CTRL_UFOA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA0_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_DEFAULT (_LETIMER_CTRL_UFOA0_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_NONE (_LETIMER_CTRL_UFOA0_NONE << 2) /**< Shifted mode NONE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_TOGGLE (_LETIMER_CTRL_UFOA0_TOGGLE << 2) /**< Shifted mode TOGGLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_PULSE (_LETIMER_CTRL_UFOA0_PULSE << 2) /**< Shifted mode PULSE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA0_PWM (_LETIMER_CTRL_UFOA0_PWM << 2) /**< Shifted mode PWM for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_SHIFT 4 /**< Shift value for LETIMER_UFOA1 */
|
||||
#define _LETIMER_CTRL_UFOA1_MASK 0x30UL /**< Bit mask for LETIMER_UFOA1 */
|
||||
#define _LETIMER_CTRL_UFOA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_NONE 0x00000000UL /**< Mode NONE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_TOGGLE 0x00000001UL /**< Mode TOGGLE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_PULSE 0x00000002UL /**< Mode PULSE for LETIMER_CTRL */
|
||||
#define _LETIMER_CTRL_UFOA1_PWM 0x00000003UL /**< Mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_DEFAULT (_LETIMER_CTRL_UFOA1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_NONE (_LETIMER_CTRL_UFOA1_NONE << 4) /**< Shifted mode NONE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_TOGGLE (_LETIMER_CTRL_UFOA1_TOGGLE << 4) /**< Shifted mode TOGGLE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_PULSE (_LETIMER_CTRL_UFOA1_PULSE << 4) /**< Shifted mode PULSE for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_UFOA1_PWM (_LETIMER_CTRL_UFOA1_PWM << 4) /**< Shifted mode PWM for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL0 (0x1UL << 6) /**< Output 0 Polarity */
|
||||
#define _LETIMER_CTRL_OPOL0_SHIFT 6 /**< Shift value for LETIMER_OPOL0 */
|
||||
#define _LETIMER_CTRL_OPOL0_MASK 0x40UL /**< Bit mask for LETIMER_OPOL0 */
|
||||
#define _LETIMER_CTRL_OPOL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL0_DEFAULT (_LETIMER_CTRL_OPOL0_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL1 (0x1UL << 7) /**< Output 1 Polarity */
|
||||
#define _LETIMER_CTRL_OPOL1_SHIFT 7 /**< Shift value for LETIMER_OPOL1 */
|
||||
#define _LETIMER_CTRL_OPOL1_MASK 0x80UL /**< Bit mask for LETIMER_OPOL1 */
|
||||
#define _LETIMER_CTRL_OPOL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_OPOL1_DEFAULT (_LETIMER_CTRL_OPOL1_DEFAULT << 7) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_BUFTOP (0x1UL << 8) /**< Buffered Top */
|
||||
#define _LETIMER_CTRL_BUFTOP_SHIFT 8 /**< Shift value for LETIMER_BUFTOP */
|
||||
#define _LETIMER_CTRL_BUFTOP_MASK 0x100UL /**< Bit mask for LETIMER_BUFTOP */
|
||||
#define _LETIMER_CTRL_BUFTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_BUFTOP_DEFAULT (_LETIMER_CTRL_BUFTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_COMP0TOP (0x1UL << 9) /**< Compare Value 0 is Top Value */
|
||||
#define _LETIMER_CTRL_COMP0TOP_SHIFT 9 /**< Shift value for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_MASK 0x200UL /**< Bit mask for LETIMER_COMP0TOP */
|
||||
#define _LETIMER_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_COMP0TOP_DEFAULT (_LETIMER_CTRL_COMP0TOP_DEFAULT << 9) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_DEBUGRUN (0x1UL << 12) /**< Debug Mode Run Enable */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_SHIFT 12 /**< Shift value for LETIMER_DEBUGRUN */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_MASK 0x1000UL /**< Bit mask for LETIMER_DEBUGRUN */
|
||||
#define _LETIMER_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CTRL */
|
||||
#define LETIMER_CTRL_DEBUGRUN_DEFAULT (_LETIMER_CTRL_DEBUGRUN_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_CTRL */
|
||||
|
||||
/* Bit fields for LETIMER CMD */
|
||||
#define _LETIMER_CMD_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CMD */
|
||||
#define _LETIMER_CMD_MASK 0x0000001FUL /**< Mask for LETIMER_CMD */
|
||||
#define LETIMER_CMD_START (0x1UL << 0) /**< Start LETIMER */
|
||||
#define _LETIMER_CMD_START_SHIFT 0 /**< Shift value for LETIMER_START */
|
||||
#define _LETIMER_CMD_START_MASK 0x1UL /**< Bit mask for LETIMER_START */
|
||||
#define _LETIMER_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_START_DEFAULT (_LETIMER_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_STOP (0x1UL << 1) /**< Stop LETIMER */
|
||||
#define _LETIMER_CMD_STOP_SHIFT 1 /**< Shift value for LETIMER_STOP */
|
||||
#define _LETIMER_CMD_STOP_MASK 0x2UL /**< Bit mask for LETIMER_STOP */
|
||||
#define _LETIMER_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_STOP_DEFAULT (_LETIMER_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CLEAR (0x1UL << 2) /**< Clear LETIMER */
|
||||
#define _LETIMER_CMD_CLEAR_SHIFT 2 /**< Shift value for LETIMER_CLEAR */
|
||||
#define _LETIMER_CMD_CLEAR_MASK 0x4UL /**< Bit mask for LETIMER_CLEAR */
|
||||
#define _LETIMER_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CLEAR_DEFAULT (_LETIMER_CMD_CLEAR_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO0 (0x1UL << 3) /**< Clear Toggle Output 0 */
|
||||
#define _LETIMER_CMD_CTO0_SHIFT 3 /**< Shift value for LETIMER_CTO0 */
|
||||
#define _LETIMER_CMD_CTO0_MASK 0x8UL /**< Bit mask for LETIMER_CTO0 */
|
||||
#define _LETIMER_CMD_CTO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO0_DEFAULT (_LETIMER_CMD_CTO0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO1 (0x1UL << 4) /**< Clear Toggle Output 1 */
|
||||
#define _LETIMER_CMD_CTO1_SHIFT 4 /**< Shift value for LETIMER_CTO1 */
|
||||
#define _LETIMER_CMD_CTO1_MASK 0x10UL /**< Bit mask for LETIMER_CTO1 */
|
||||
#define _LETIMER_CMD_CTO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CMD */
|
||||
#define LETIMER_CMD_CTO1_DEFAULT (_LETIMER_CMD_CTO1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_CMD */
|
||||
|
||||
/* Bit fields for LETIMER STATUS */
|
||||
#define _LETIMER_STATUS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_STATUS */
|
||||
#define _LETIMER_STATUS_MASK 0x00000001UL /**< Mask for LETIMER_STATUS */
|
||||
#define LETIMER_STATUS_RUNNING (0x1UL << 0) /**< LETIMER Running */
|
||||
#define _LETIMER_STATUS_RUNNING_SHIFT 0 /**< Shift value for LETIMER_RUNNING */
|
||||
#define _LETIMER_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for LETIMER_RUNNING */
|
||||
#define _LETIMER_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_STATUS */
|
||||
#define LETIMER_STATUS_RUNNING_DEFAULT (_LETIMER_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_STATUS */
|
||||
|
||||
/* Bit fields for LETIMER CNT */
|
||||
#define _LETIMER_CNT_RESETVALUE 0x00000000UL /**< Default value for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_MASK 0x0000FFFFUL /**< Mask for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_SHIFT 0 /**< Shift value for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for LETIMER_CNT */
|
||||
#define _LETIMER_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_CNT */
|
||||
#define LETIMER_CNT_CNT_DEFAULT (_LETIMER_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_CNT */
|
||||
|
||||
/* Bit fields for LETIMER COMP0 */
|
||||
#define _LETIMER_COMP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP0 */
|
||||
#define LETIMER_COMP0_COMP0_DEFAULT (_LETIMER_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP0 */
|
||||
|
||||
/* Bit fields for LETIMER COMP1 */
|
||||
#define _LETIMER_COMP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_MASK 0x0000FFFFUL /**< Mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_SHIFT 0 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_MASK 0xFFFFUL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_COMP1 */
|
||||
#define LETIMER_COMP1_COMP1_DEFAULT (_LETIMER_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_COMP1 */
|
||||
|
||||
/* Bit fields for LETIMER REP0 */
|
||||
#define _LETIMER_REP0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_MASK 0x000000FFUL /**< Mask for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_SHIFT 0 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_MASK 0xFFUL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_REP0_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP0 */
|
||||
#define LETIMER_REP0_REP0_DEFAULT (_LETIMER_REP0_REP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP0 */
|
||||
|
||||
/* Bit fields for LETIMER REP1 */
|
||||
#define _LETIMER_REP1_RESETVALUE 0x00000000UL /**< Default value for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_MASK 0x000000FFUL /**< Mask for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_SHIFT 0 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_MASK 0xFFUL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_REP1_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_REP1 */
|
||||
#define LETIMER_REP1_REP1_DEFAULT (_LETIMER_REP1_REP1_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_REP1 */
|
||||
|
||||
/* Bit fields for LETIMER IF */
|
||||
#define _LETIMER_IF_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IF */
|
||||
#define _LETIMER_IF_MASK 0x0000001FUL /**< Mask for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP0 (0x1UL << 0) /**< Compare Match 0 Interrupt Flag */
|
||||
#define _LETIMER_IF_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IF_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP0_DEFAULT (_LETIMER_IF_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP1 (0x1UL << 1) /**< Compare Match 1 Interrupt Flag */
|
||||
#define _LETIMER_IF_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IF_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_COMP1_DEFAULT (_LETIMER_IF_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_UF (0x1UL << 2) /**< Underflow Interrupt Flag */
|
||||
#define _LETIMER_IF_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IF_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_UF_DEFAULT (_LETIMER_IF_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP0 (0x1UL << 3) /**< Repeat Counter 0 Interrupt Flag */
|
||||
#define _LETIMER_IF_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IF_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IF_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP0_DEFAULT (_LETIMER_IF_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP1 (0x1UL << 4) /**< Repeat Counter 1 Interrupt Flag */
|
||||
#define _LETIMER_IF_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IF_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IF_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IF */
|
||||
#define LETIMER_IF_REP1_DEFAULT (_LETIMER_IF_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IF */
|
||||
|
||||
/* Bit fields for LETIMER IFS */
|
||||
#define _LETIMER_IFS_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFS */
|
||||
#define _LETIMER_IFS_MASK 0x0000001FUL /**< Mask for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP0 (0x1UL << 0) /**< Set COMP0 Interrupt Flag */
|
||||
#define _LETIMER_IFS_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFS_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP0_DEFAULT (_LETIMER_IFS_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP1 (0x1UL << 1) /**< Set COMP1 Interrupt Flag */
|
||||
#define _LETIMER_IFS_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFS_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_COMP1_DEFAULT (_LETIMER_IFS_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_UF (0x1UL << 2) /**< Set UF Interrupt Flag */
|
||||
#define _LETIMER_IFS_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IFS_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_UF_DEFAULT (_LETIMER_IFS_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP0 (0x1UL << 3) /**< Set REP0 Interrupt Flag */
|
||||
#define _LETIMER_IFS_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IFS_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IFS_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP0_DEFAULT (_LETIMER_IFS_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP1 (0x1UL << 4) /**< Set REP1 Interrupt Flag */
|
||||
#define _LETIMER_IFS_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IFS_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IFS_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFS */
|
||||
#define LETIMER_IFS_REP1_DEFAULT (_LETIMER_IFS_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFS */
|
||||
|
||||
/* Bit fields for LETIMER IFC */
|
||||
#define _LETIMER_IFC_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IFC */
|
||||
#define _LETIMER_IFC_MASK 0x0000001FUL /**< Mask for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP0 (0x1UL << 0) /**< Clear COMP0 Interrupt Flag */
|
||||
#define _LETIMER_IFC_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFC_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP0_DEFAULT (_LETIMER_IFC_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP1 (0x1UL << 1) /**< Clear COMP1 Interrupt Flag */
|
||||
#define _LETIMER_IFC_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFC_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_COMP1_DEFAULT (_LETIMER_IFC_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_UF (0x1UL << 2) /**< Clear UF Interrupt Flag */
|
||||
#define _LETIMER_IFC_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IFC_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_UF_DEFAULT (_LETIMER_IFC_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP0 (0x1UL << 3) /**< Clear REP0 Interrupt Flag */
|
||||
#define _LETIMER_IFC_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IFC_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IFC_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP0_DEFAULT (_LETIMER_IFC_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP1 (0x1UL << 4) /**< Clear REP1 Interrupt Flag */
|
||||
#define _LETIMER_IFC_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IFC_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IFC_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IFC */
|
||||
#define LETIMER_IFC_REP1_DEFAULT (_LETIMER_IFC_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IFC */
|
||||
|
||||
/* Bit fields for LETIMER IEN */
|
||||
#define _LETIMER_IEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_IEN */
|
||||
#define _LETIMER_IEN_MASK 0x0000001FUL /**< Mask for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP0 (0x1UL << 0) /**< COMP0 Interrupt Enable */
|
||||
#define _LETIMER_IEN_COMP0_SHIFT 0 /**< Shift value for LETIMER_COMP0 */
|
||||
#define _LETIMER_IEN_COMP0_MASK 0x1UL /**< Bit mask for LETIMER_COMP0 */
|
||||
#define _LETIMER_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP0_DEFAULT (_LETIMER_IEN_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP1 (0x1UL << 1) /**< COMP1 Interrupt Enable */
|
||||
#define _LETIMER_IEN_COMP1_SHIFT 1 /**< Shift value for LETIMER_COMP1 */
|
||||
#define _LETIMER_IEN_COMP1_MASK 0x2UL /**< Bit mask for LETIMER_COMP1 */
|
||||
#define _LETIMER_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_COMP1_DEFAULT (_LETIMER_IEN_COMP1_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_UF (0x1UL << 2) /**< UF Interrupt Enable */
|
||||
#define _LETIMER_IEN_UF_SHIFT 2 /**< Shift value for LETIMER_UF */
|
||||
#define _LETIMER_IEN_UF_MASK 0x4UL /**< Bit mask for LETIMER_UF */
|
||||
#define _LETIMER_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_UF_DEFAULT (_LETIMER_IEN_UF_DEFAULT << 2) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP0 (0x1UL << 3) /**< REP0 Interrupt Enable */
|
||||
#define _LETIMER_IEN_REP0_SHIFT 3 /**< Shift value for LETIMER_REP0 */
|
||||
#define _LETIMER_IEN_REP0_MASK 0x8UL /**< Bit mask for LETIMER_REP0 */
|
||||
#define _LETIMER_IEN_REP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP0_DEFAULT (_LETIMER_IEN_REP0_DEFAULT << 3) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP1 (0x1UL << 4) /**< REP1 Interrupt Enable */
|
||||
#define _LETIMER_IEN_REP1_SHIFT 4 /**< Shift value for LETIMER_REP1 */
|
||||
#define _LETIMER_IEN_REP1_MASK 0x10UL /**< Bit mask for LETIMER_REP1 */
|
||||
#define _LETIMER_IEN_REP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_IEN */
|
||||
#define LETIMER_IEN_REP1_DEFAULT (_LETIMER_IEN_REP1_DEFAULT << 4) /**< Shifted mode DEFAULT for LETIMER_IEN */
|
||||
|
||||
/* Bit fields for LETIMER SYNCBUSY */
|
||||
#define _LETIMER_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LETIMER_SYNCBUSY */
|
||||
#define _LETIMER_SYNCBUSY_MASK 0x00000002UL /**< Mask for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
|
||||
#define _LETIMER_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LETIMER_CMD */
|
||||
#define _LETIMER_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LETIMER_CMD */
|
||||
#define _LETIMER_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
#define LETIMER_SYNCBUSY_CMD_DEFAULT (_LETIMER_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LETIMER ROUTEPEN */
|
||||
#define _LETIMER_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTEPEN */
|
||||
#define _LETIMER_ROUTEPEN_MASK 0x00000003UL /**< Mask for LETIMER_ROUTEPEN */
|
||||
#define LETIMER_ROUTEPEN_OUT0PEN (0x1UL << 0) /**< Output 0 Pin Enable */
|
||||
#define _LETIMER_ROUTEPEN_OUT0PEN_SHIFT 0 /**< Shift value for LETIMER_OUT0PEN */
|
||||
#define _LETIMER_ROUTEPEN_OUT0PEN_MASK 0x1UL /**< Bit mask for LETIMER_OUT0PEN */
|
||||
#define _LETIMER_ROUTEPEN_OUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
|
||||
#define LETIMER_ROUTEPEN_OUT0PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
|
||||
#define LETIMER_ROUTEPEN_OUT1PEN (0x1UL << 1) /**< Output 1 Pin Enable */
|
||||
#define _LETIMER_ROUTEPEN_OUT1PEN_SHIFT 1 /**< Shift value for LETIMER_OUT1PEN */
|
||||
#define _LETIMER_ROUTEPEN_OUT1PEN_MASK 0x2UL /**< Bit mask for LETIMER_OUT1PEN */
|
||||
#define _LETIMER_ROUTEPEN_OUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTEPEN */
|
||||
#define LETIMER_ROUTEPEN_OUT1PEN_DEFAULT (_LETIMER_ROUTEPEN_OUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LETIMER_ROUTEPEN */
|
||||
|
||||
/* Bit fields for LETIMER ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_MASK 0x00000707UL /**< Mask for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_SHIFT 0 /**< Shift value for LETIMER_OUT0LOC */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_MASK 0x7UL /**< Bit mask for LETIMER_OUT0LOC */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT0LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC0 (_LETIMER_ROUTELOC0_OUT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC1 (_LETIMER_ROUTELOC0_OUT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC2 (_LETIMER_ROUTELOC0_OUT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC3 (_LETIMER_ROUTELOC0_OUT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC4 (_LETIMER_ROUTELOC0_OUT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC5 (_LETIMER_ROUTELOC0_OUT0LOC_LOC5 << 0) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC6 (_LETIMER_ROUTELOC0_OUT0LOC_LOC6 << 0) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT0LOC_LOC7 (_LETIMER_ROUTELOC0_OUT0LOC_LOC7 << 0) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_SHIFT 8 /**< Shift value for LETIMER_OUT1LOC */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_MASK 0x700UL /**< Bit mask for LETIMER_OUT1LOC */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC5 0x00000005UL /**< Mode LOC5 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC6 0x00000006UL /**< Mode LOC6 for LETIMER_ROUTELOC0 */
|
||||
#define _LETIMER_ROUTELOC0_OUT1LOC_LOC7 0x00000007UL /**< Mode LOC7 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC0 (_LETIMER_ROUTELOC0_OUT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_DEFAULT (_LETIMER_ROUTELOC0_OUT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC1 (_LETIMER_ROUTELOC0_OUT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC2 (_LETIMER_ROUTELOC0_OUT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC3 (_LETIMER_ROUTELOC0_OUT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC4 (_LETIMER_ROUTELOC0_OUT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC5 (_LETIMER_ROUTELOC0_OUT1LOC_LOC5 << 8) /**< Shifted mode LOC5 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC6 (_LETIMER_ROUTELOC0_OUT1LOC_LOC6 << 8) /**< Shifted mode LOC6 for LETIMER_ROUTELOC0 */
|
||||
#define LETIMER_ROUTELOC0_OUT1LOC_LOC7 (_LETIMER_ROUTELOC0_OUT1LOC_LOC7 << 8) /**< Shifted mode LOC7 for LETIMER_ROUTELOC0 */
|
||||
|
||||
/* Bit fields for LETIMER PRSSEL */
|
||||
#define _LETIMER_PRSSEL_RESETVALUE 0x00000000UL /**< Default value for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_MASK 0x0CCDF7DFUL /**< Mask for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_SHIFT 0 /**< Shift value for LETIMER_PRSSTARTSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_MASK 0x1FUL /**< Bit mask for LETIMER_PRSSTARTSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTARTSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 (_LETIMER_PRSSEL_PRSSTARTSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_SHIFT 6 /**< Shift value for LETIMER_PRSSTOPSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_MASK 0x7C0UL /**< Bit mask for LETIMER_PRSSTOPSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT (_LETIMER_PRSSEL_PRSSTOPSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 (_LETIMER_PRSSEL_PRSSTOPSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_SHIFT 12 /**< Shift value for LETIMER_PRSCLEARSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_MASK 0x1F000UL /**< Bit mask for LETIMER_PRSCLEARSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT (_LETIMER_PRSSEL_PRSCLEARSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH0 << 12) /**< Shifted mode PRSCH0 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH1 << 12) /**< Shifted mode PRSCH1 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH2 << 12) /**< Shifted mode PRSCH2 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH3 << 12) /**< Shifted mode PRSCH3 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH4 << 12) /**< Shifted mode PRSCH4 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH5 << 12) /**< Shifted mode PRSCH5 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH6 << 12) /**< Shifted mode PRSCH6 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH7 << 12) /**< Shifted mode PRSCH7 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH8 << 12) /**< Shifted mode PRSCH8 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH9 << 12) /**< Shifted mode PRSCH9 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH10 << 12) /**< Shifted mode PRSCH10 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH11 << 12) /**< Shifted mode PRSCH11 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH12 << 12) /**< Shifted mode PRSCH12 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH13 << 12) /**< Shifted mode PRSCH13 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH14 << 12) /**< Shifted mode PRSCH14 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH15 << 12) /**< Shifted mode PRSCH15 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH16 << 12) /**< Shifted mode PRSCH16 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH17 << 12) /**< Shifted mode PRSCH17 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH18 << 12) /**< Shifted mode PRSCH18 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH19 << 12) /**< Shifted mode PRSCH19 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH20 << 12) /**< Shifted mode PRSCH20 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH21 << 12) /**< Shifted mode PRSCH21 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH22 << 12) /**< Shifted mode PRSCH22 for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 (_LETIMER_PRSSEL_PRSCLEARSEL_PRSCH23 << 12) /**< Shifted mode PRSCH23 for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_SHIFT 18 /**< Shift value for LETIMER_PRSSTARTMODE */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_MASK 0xC0000UL /**< Bit mask for LETIMER_PRSSTARTMODE */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTARTMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTARTMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTMODE_NONE (_LETIMER_PRSSEL_PRSSTARTMODE_NONE << 18) /**< Shifted mode NONE for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTMODE_RISING (_LETIMER_PRSSEL_PRSSTARTMODE_RISING << 18) /**< Shifted mode RISING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTMODE_FALLING (_LETIMER_PRSSEL_PRSSTARTMODE_FALLING << 18) /**< Shifted mode FALLING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTARTMODE_BOTH (_LETIMER_PRSSEL_PRSSTARTMODE_BOTH << 18) /**< Shifted mode BOTH for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_SHIFT 22 /**< Shift value for LETIMER_PRSSTOPMODE */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_MASK 0xC00000UL /**< Bit mask for LETIMER_PRSSTOPMODE */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSSTOPMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT (_LETIMER_PRSSEL_PRSSTOPMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPMODE_NONE (_LETIMER_PRSSEL_PRSSTOPMODE_NONE << 22) /**< Shifted mode NONE for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPMODE_RISING (_LETIMER_PRSSEL_PRSSTOPMODE_RISING << 22) /**< Shifted mode RISING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPMODE_FALLING (_LETIMER_PRSSEL_PRSSTOPMODE_FALLING << 22) /**< Shifted mode FALLING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSSTOPMODE_BOTH (_LETIMER_PRSSEL_PRSSTOPMODE_BOTH << 22) /**< Shifted mode BOTH for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_SHIFT 26 /**< Shift value for LETIMER_PRSCLEARMODE */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_MASK 0xC000000UL /**< Bit mask for LETIMER_PRSCLEARMODE */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_NONE 0x00000000UL /**< Mode NONE for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_RISING 0x00000001UL /**< Mode RISING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_FALLING 0x00000002UL /**< Mode FALLING for LETIMER_PRSSEL */
|
||||
#define _LETIMER_PRSSEL_PRSCLEARMODE_BOTH 0x00000003UL /**< Mode BOTH for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT (_LETIMER_PRSSEL_PRSCLEARMODE_DEFAULT << 26) /**< Shifted mode DEFAULT for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_NONE (_LETIMER_PRSSEL_PRSCLEARMODE_NONE << 26) /**< Shifted mode NONE for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_RISING (_LETIMER_PRSSEL_PRSCLEARMODE_RISING << 26) /**< Shifted mode RISING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_FALLING (_LETIMER_PRSSEL_PRSCLEARMODE_FALLING << 26) /**< Shifted mode FALLING for LETIMER_PRSSEL */
|
||||
#define LETIMER_PRSSEL_PRSCLEARMODE_BOTH (_LETIMER_PRSSEL_PRSCLEARMODE_BOTH << 26) /**< Shifted mode BOTH for LETIMER_PRSSEL */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LETIMER */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
771
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h
vendored
Normal file
771
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_leuart.h
vendored
Normal file
@ -0,0 +1,771 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_LEUART register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_LEUART LEUART
|
||||
* @{
|
||||
* @brief EFM32GG11B_LEUART Register Declaration
|
||||
******************************************************************************/
|
||||
/** LEUART Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IOM uint32_t CLKDIV; /**< Clock Control Register */
|
||||
__IOM uint32_t STARTFRAME; /**< Start Frame Register */
|
||||
__IOM uint32_t SIGFRAME; /**< Signal Frame Register */
|
||||
__IM uint32_t RXDATAX; /**< Receive Buffer Data Extended Register */
|
||||
__IM uint32_t RXDATA; /**< Receive Buffer Data Register */
|
||||
__IM uint32_t RXDATAXP; /**< Receive Buffer Data Extended Peek Register */
|
||||
__IOM uint32_t TXDATAX; /**< Transmit Buffer Data Extended Register */
|
||||
__IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t PULSECTRL; /**< Pulse Control Register */
|
||||
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED0[3U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
uint32_t RESERVED1[2U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t INPUT; /**< LEUART Input Register */
|
||||
} LEUART_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_LEUART
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_LEUART_BitFields LEUART Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for LEUART CTRL */
|
||||
#define _LEUART_CTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_MASK 0x0000FFFFUL /**< Mask for LEUART_CTRL */
|
||||
#define LEUART_CTRL_AUTOTRI (0x1UL << 0) /**< Automatic Transmitter Tristate */
|
||||
#define _LEUART_CTRL_AUTOTRI_SHIFT 0 /**< Shift value for LEUART_AUTOTRI */
|
||||
#define _LEUART_CTRL_AUTOTRI_MASK 0x1UL /**< Bit mask for LEUART_AUTOTRI */
|
||||
#define _LEUART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_AUTOTRI_DEFAULT (_LEUART_CTRL_AUTOTRI_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS (0x1UL << 1) /**< Data-Bit Mode */
|
||||
#define _LEUART_CTRL_DATABITS_SHIFT 1 /**< Shift value for LEUART_DATABITS */
|
||||
#define _LEUART_CTRL_DATABITS_MASK 0x2UL /**< Bit mask for LEUART_DATABITS */
|
||||
#define _LEUART_CTRL_DATABITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_DATABITS_EIGHT 0x00000000UL /**< Mode EIGHT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_DATABITS_NINE 0x00000001UL /**< Mode NINE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_DEFAULT (_LEUART_CTRL_DATABITS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_EIGHT (_LEUART_CTRL_DATABITS_EIGHT << 1) /**< Shifted mode EIGHT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_DATABITS_NINE (_LEUART_CTRL_DATABITS_NINE << 1) /**< Shifted mode NINE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_SHIFT 2 /**< Shift value for LEUART_PARITY */
|
||||
#define _LEUART_CTRL_PARITY_MASK 0xCUL /**< Bit mask for LEUART_PARITY */
|
||||
#define _LEUART_CTRL_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_EVEN 0x00000002UL /**< Mode EVEN for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_PARITY_ODD 0x00000003UL /**< Mode ODD for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_DEFAULT (_LEUART_CTRL_PARITY_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_NONE (_LEUART_CTRL_PARITY_NONE << 2) /**< Shifted mode NONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_EVEN (_LEUART_CTRL_PARITY_EVEN << 2) /**< Shifted mode EVEN for LEUART_CTRL */
|
||||
#define LEUART_CTRL_PARITY_ODD (_LEUART_CTRL_PARITY_ODD << 2) /**< Shifted mode ODD for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS (0x1UL << 4) /**< Stop-Bit Mode */
|
||||
#define _LEUART_CTRL_STOPBITS_SHIFT 4 /**< Shift value for LEUART_STOPBITS */
|
||||
#define _LEUART_CTRL_STOPBITS_MASK 0x10UL /**< Bit mask for LEUART_STOPBITS */
|
||||
#define _LEUART_CTRL_STOPBITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_STOPBITS_ONE 0x00000000UL /**< Mode ONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_STOPBITS_TWO 0x00000001UL /**< Mode TWO for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_DEFAULT (_LEUART_CTRL_STOPBITS_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_ONE (_LEUART_CTRL_STOPBITS_ONE << 4) /**< Shifted mode ONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_STOPBITS_TWO (_LEUART_CTRL_STOPBITS_TWO << 4) /**< Shifted mode TWO for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV (0x1UL << 5) /**< Invert Input and Output */
|
||||
#define _LEUART_CTRL_INV_SHIFT 5 /**< Shift value for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_MASK 0x20UL /**< Bit mask for LEUART_INV */
|
||||
#define _LEUART_CTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_INV_DEFAULT (_LEUART_CTRL_INV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_ERRSDMA (0x1UL << 6) /**< Clear RX DMA on Error */
|
||||
#define _LEUART_CTRL_ERRSDMA_SHIFT 6 /**< Shift value for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_MASK 0x40UL /**< Bit mask for LEUART_ERRSDMA */
|
||||
#define _LEUART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_ERRSDMA_DEFAULT (_LEUART_CTRL_ERRSDMA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_LOOPBK (0x1UL << 7) /**< Loopback Enable */
|
||||
#define _LEUART_CTRL_LOOPBK_SHIFT 7 /**< Shift value for LEUART_LOOPBK */
|
||||
#define _LEUART_CTRL_LOOPBK_MASK 0x80UL /**< Bit mask for LEUART_LOOPBK */
|
||||
#define _LEUART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_LOOPBK_DEFAULT (_LEUART_CTRL_LOOPBK_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_SFUBRX (0x1UL << 8) /**< Start-Frame UnBlock RX */
|
||||
#define _LEUART_CTRL_SFUBRX_SHIFT 8 /**< Shift value for LEUART_SFUBRX */
|
||||
#define _LEUART_CTRL_SFUBRX_MASK 0x100UL /**< Bit mask for LEUART_SFUBRX */
|
||||
#define _LEUART_CTRL_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_SFUBRX_DEFAULT (_LEUART_CTRL_SFUBRX_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPM (0x1UL << 9) /**< Multi-Processor Mode */
|
||||
#define _LEUART_CTRL_MPM_SHIFT 9 /**< Shift value for LEUART_MPM */
|
||||
#define _LEUART_CTRL_MPM_MASK 0x200UL /**< Bit mask for LEUART_MPM */
|
||||
#define _LEUART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPM_DEFAULT (_LEUART_CTRL_MPM_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPAB (0x1UL << 10) /**< Multi-Processor Address-Bit */
|
||||
#define _LEUART_CTRL_MPAB_SHIFT 10 /**< Shift value for LEUART_MPAB */
|
||||
#define _LEUART_CTRL_MPAB_MASK 0x400UL /**< Bit mask for LEUART_MPAB */
|
||||
#define _LEUART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_MPAB_DEFAULT (_LEUART_CTRL_MPAB_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_BIT8DV (0x1UL << 11) /**< Bit 8 Default Value */
|
||||
#define _LEUART_CTRL_BIT8DV_SHIFT 11 /**< Shift value for LEUART_BIT8DV */
|
||||
#define _LEUART_CTRL_BIT8DV_MASK 0x800UL /**< Bit mask for LEUART_BIT8DV */
|
||||
#define _LEUART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_BIT8DV_DEFAULT (_LEUART_CTRL_BIT8DV_DEFAULT << 11) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_RXDMAWU (0x1UL << 12) /**< RX DMA Wakeup */
|
||||
#define _LEUART_CTRL_RXDMAWU_SHIFT 12 /**< Shift value for LEUART_RXDMAWU */
|
||||
#define _LEUART_CTRL_RXDMAWU_MASK 0x1000UL /**< Bit mask for LEUART_RXDMAWU */
|
||||
#define _LEUART_CTRL_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_RXDMAWU_DEFAULT (_LEUART_CTRL_RXDMAWU_DEFAULT << 12) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDMAWU (0x1UL << 13) /**< TX DMA Wakeup */
|
||||
#define _LEUART_CTRL_TXDMAWU_SHIFT 13 /**< Shift value for LEUART_TXDMAWU */
|
||||
#define _LEUART_CTRL_TXDMAWU_MASK 0x2000UL /**< Bit mask for LEUART_TXDMAWU */
|
||||
#define _LEUART_CTRL_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDMAWU_DEFAULT (_LEUART_CTRL_TXDMAWU_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_SHIFT 14 /**< Shift value for LEUART_TXDELAY */
|
||||
#define _LEUART_CTRL_TXDELAY_MASK 0xC000UL /**< Bit mask for LEUART_TXDELAY */
|
||||
#define _LEUART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for LEUART_CTRL */
|
||||
#define _LEUART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_DEFAULT (_LEUART_CTRL_TXDELAY_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_NONE (_LEUART_CTRL_TXDELAY_NONE << 14) /**< Shifted mode NONE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_SINGLE (_LEUART_CTRL_TXDELAY_SINGLE << 14) /**< Shifted mode SINGLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_DOUBLE (_LEUART_CTRL_TXDELAY_DOUBLE << 14) /**< Shifted mode DOUBLE for LEUART_CTRL */
|
||||
#define LEUART_CTRL_TXDELAY_TRIPLE (_LEUART_CTRL_TXDELAY_TRIPLE << 14) /**< Shifted mode TRIPLE for LEUART_CTRL */
|
||||
|
||||
/* Bit fields for LEUART CMD */
|
||||
#define _LEUART_CMD_RESETVALUE 0x00000000UL /**< Default value for LEUART_CMD */
|
||||
#define _LEUART_CMD_MASK 0x000000FFUL /**< Mask for LEUART_CMD */
|
||||
#define LEUART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
|
||||
#define _LEUART_CMD_RXEN_SHIFT 0 /**< Shift value for LEUART_RXEN */
|
||||
#define _LEUART_CMD_RXEN_MASK 0x1UL /**< Bit mask for LEUART_RXEN */
|
||||
#define _LEUART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXEN_DEFAULT (_LEUART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
|
||||
#define _LEUART_CMD_RXDIS_SHIFT 1 /**< Shift value for LEUART_RXDIS */
|
||||
#define _LEUART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for LEUART_RXDIS */
|
||||
#define _LEUART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXDIS_DEFAULT (_LEUART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
|
||||
#define _LEUART_CMD_TXEN_SHIFT 2 /**< Shift value for LEUART_TXEN */
|
||||
#define _LEUART_CMD_TXEN_MASK 0x4UL /**< Bit mask for LEUART_TXEN */
|
||||
#define _LEUART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXEN_DEFAULT (_LEUART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
|
||||
#define _LEUART_CMD_TXDIS_SHIFT 3 /**< Shift value for LEUART_TXDIS */
|
||||
#define _LEUART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for LEUART_TXDIS */
|
||||
#define _LEUART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_TXDIS_DEFAULT (_LEUART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */
|
||||
#define _LEUART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for LEUART_RXBLOCKEN */
|
||||
#define _LEUART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for LEUART_RXBLOCKEN */
|
||||
#define _LEUART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKEN_DEFAULT (_LEUART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for LEUART_RXBLOCKDIS */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for LEUART_RXBLOCKDIS */
|
||||
#define _LEUART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_RXBLOCKDIS_DEFAULT (_LEUART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
|
||||
#define _LEUART_CMD_CLEARTX_SHIFT 6 /**< Shift value for LEUART_CLEARTX */
|
||||
#define _LEUART_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for LEUART_CLEARTX */
|
||||
#define _LEUART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARTX_DEFAULT (_LEUART_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARRX (0x1UL << 7) /**< Clear RX */
|
||||
#define _LEUART_CMD_CLEARRX_SHIFT 7 /**< Shift value for LEUART_CLEARRX */
|
||||
#define _LEUART_CMD_CLEARRX_MASK 0x80UL /**< Bit mask for LEUART_CLEARRX */
|
||||
#define _LEUART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CMD */
|
||||
#define LEUART_CMD_CLEARRX_DEFAULT (_LEUART_CMD_CLEARRX_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_CMD */
|
||||
|
||||
/* Bit fields for LEUART STATUS */
|
||||
#define _LEUART_STATUS_RESETVALUE 0x00000050UL /**< Default value for LEUART_STATUS */
|
||||
#define _LEUART_STATUS_MASK 0x0000007FUL /**< Mask for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
|
||||
#define _LEUART_STATUS_RXENS_SHIFT 0 /**< Shift value for LEUART_RXENS */
|
||||
#define _LEUART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for LEUART_RXENS */
|
||||
#define _LEUART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXENS_DEFAULT (_LEUART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
|
||||
#define _LEUART_STATUS_TXENS_SHIFT 1 /**< Shift value for LEUART_TXENS */
|
||||
#define _LEUART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for LEUART_TXENS */
|
||||
#define _LEUART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXENS_DEFAULT (_LEUART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXBLOCK (0x1UL << 2) /**< Block Incoming Data */
|
||||
#define _LEUART_STATUS_RXBLOCK_SHIFT 2 /**< Shift value for LEUART_RXBLOCK */
|
||||
#define _LEUART_STATUS_RXBLOCK_MASK 0x4UL /**< Bit mask for LEUART_RXBLOCK */
|
||||
#define _LEUART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXBLOCK_DEFAULT (_LEUART_STATUS_RXBLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXC (0x1UL << 3) /**< TX Complete */
|
||||
#define _LEUART_STATUS_TXC_SHIFT 3 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_STATUS_TXC_MASK 0x8UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXC_DEFAULT (_LEUART_STATUS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXBL (0x1UL << 4) /**< TX Buffer Level */
|
||||
#define _LEUART_STATUS_TXBL_SHIFT 4 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_STATUS_TXBL_MASK 0x10UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXBL_DEFAULT (_LEUART_STATUS_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXDATAV (0x1UL << 5) /**< RX Data Valid */
|
||||
#define _LEUART_STATUS_RXDATAV_SHIFT 5 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_STATUS_RXDATAV_MASK 0x20UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_RXDATAV_DEFAULT (_LEUART_STATUS_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXIDLE (0x1UL << 6) /**< TX Idle */
|
||||
#define _LEUART_STATUS_TXIDLE_SHIFT 6 /**< Shift value for LEUART_TXIDLE */
|
||||
#define _LEUART_STATUS_TXIDLE_MASK 0x40UL /**< Bit mask for LEUART_TXIDLE */
|
||||
#define _LEUART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_STATUS */
|
||||
#define LEUART_STATUS_TXIDLE_DEFAULT (_LEUART_STATUS_TXIDLE_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_STATUS */
|
||||
|
||||
/* Bit fields for LEUART CLKDIV */
|
||||
#define _LEUART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for LEUART_CLKDIV */
|
||||
#define _LEUART_CLKDIV_MASK 0x0001FFF8UL /**< Mask for LEUART_CLKDIV */
|
||||
#define _LEUART_CLKDIV_DIV_SHIFT 3 /**< Shift value for LEUART_DIV */
|
||||
#define _LEUART_CLKDIV_DIV_MASK 0x1FFF8UL /**< Bit mask for LEUART_DIV */
|
||||
#define _LEUART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_CLKDIV */
|
||||
#define LEUART_CLKDIV_DIV_DEFAULT (_LEUART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_CLKDIV */
|
||||
|
||||
/* Bit fields for LEUART STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_MASK 0x000001FFUL /**< Mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_SHIFT 0 /**< Shift value for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_STARTFRAME_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_STARTFRAME */
|
||||
#define LEUART_STARTFRAME_STARTFRAME_DEFAULT (_LEUART_STARTFRAME_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_STARTFRAME */
|
||||
|
||||
/* Bit fields for LEUART SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_RESETVALUE 0x00000000UL /**< Default value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_MASK 0x000001FFUL /**< Mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_SHIFT 0 /**< Shift value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_MASK 0x1FFUL /**< Bit mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SIGFRAME_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SIGFRAME */
|
||||
#define LEUART_SIGFRAME_SIGFRAME_DEFAULT (_LEUART_SIGFRAME_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SIGFRAME */
|
||||
|
||||
/* Bit fields for LEUART RXDATAX */
|
||||
#define _LEUART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAX */
|
||||
#define _LEUART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAX */
|
||||
#define _LEUART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_RXDATA_DEFAULT (_LEUART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_PERR (0x1UL << 14) /**< Receive Data Parity Error */
|
||||
#define _LEUART_RXDATAX_PERR_SHIFT 14 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_PERR_DEFAULT (_LEUART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_FERR (0x1UL << 15) /**< Receive Data Framing Error */
|
||||
#define _LEUART_RXDATAX_FERR_SHIFT 15 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAX */
|
||||
#define LEUART_RXDATAX_FERR_DEFAULT (_LEUART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAX */
|
||||
|
||||
/* Bit fields for LEUART RXDATA */
|
||||
#define _LEUART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_MASK 0x000000FFUL /**< Mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for LEUART_RXDATA */
|
||||
#define _LEUART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATA */
|
||||
#define LEUART_RXDATA_RXDATA_DEFAULT (_LEUART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATA */
|
||||
|
||||
/* Bit fields for LEUART RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for LEUART_RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for LEUART_RXDATAXP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for LEUART_RXDATAP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for LEUART_RXDATAP */
|
||||
#define _LEUART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_RXDATAP_DEFAULT (_LEUART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_PERRP (0x1UL << 14) /**< Receive Data Parity Error Peek */
|
||||
#define _LEUART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for LEUART_PERRP */
|
||||
#define _LEUART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for LEUART_PERRP */
|
||||
#define _LEUART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_PERRP_DEFAULT (_LEUART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_FERRP (0x1UL << 15) /**< Receive Data Framing Error Peek */
|
||||
#define _LEUART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for LEUART_FERRP */
|
||||
#define _LEUART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for LEUART_FERRP */
|
||||
#define _LEUART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_RXDATAXP */
|
||||
#define LEUART_RXDATAXP_FERRP_DEFAULT (_LEUART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_RXDATAXP */
|
||||
|
||||
/* Bit fields for LEUART TXDATAX */
|
||||
#define _LEUART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATAX */
|
||||
#define _LEUART_TXDATAX_MASK 0x0000E1FFUL /**< Mask for LEUART_TXDATAX */
|
||||
#define _LEUART_TXDATAX_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATAX_TXDATA_MASK 0x1FFUL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATAX_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDATA_DEFAULT (_LEUART_TXDATAX_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data as Break */
|
||||
#define _LEUART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for LEUART_TXBREAK */
|
||||
#define _LEUART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXBREAK_DEFAULT (_LEUART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDISAT (0x1UL << 14) /**< Disable TX After Transmission */
|
||||
#define _LEUART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for LEUART_TXDISAT */
|
||||
#define _LEUART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for LEUART_TXDISAT */
|
||||
#define _LEUART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_TXDISAT_DEFAULT (_LEUART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
|
||||
#define _LEUART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for LEUART_RXENAT */
|
||||
#define _LEUART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for LEUART_RXENAT */
|
||||
#define _LEUART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATAX */
|
||||
#define LEUART_TXDATAX_RXENAT_DEFAULT (_LEUART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for LEUART_TXDATAX */
|
||||
|
||||
/* Bit fields for LEUART TXDATA */
|
||||
#define _LEUART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_MASK 0x000000FFUL /**< Mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_TXDATA */
|
||||
#define LEUART_TXDATA_TXDATA_DEFAULT (_LEUART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_TXDATA */
|
||||
|
||||
/* Bit fields for LEUART IF */
|
||||
#define _LEUART_IF_RESETVALUE 0x00000002UL /**< Default value for LEUART_IF */
|
||||
#define _LEUART_IF_MASK 0x000007FFUL /**< Mask for LEUART_IF */
|
||||
#define LEUART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
|
||||
#define _LEUART_IF_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IF_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXC_DEFAULT (_LEUART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
|
||||
#define _LEUART_IF_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_IF_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXBL_DEFAULT (_LEUART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
|
||||
#define _LEUART_IF_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXDATAV_DEFAULT (_LEUART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXOF (0x1UL << 3) /**< RX Overflow Interrupt Flag */
|
||||
#define _LEUART_IF_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IF_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXOF_DEFAULT (_LEUART_IF_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXUF (0x1UL << 4) /**< RX Underflow Interrupt Flag */
|
||||
#define _LEUART_IF_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IF_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_RXUF_DEFAULT (_LEUART_IF_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXOF (0x1UL << 5) /**< TX Overflow Interrupt Flag */
|
||||
#define _LEUART_IF_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IF_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_TXOF_DEFAULT (_LEUART_IF_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_PERR (0x1UL << 6) /**< Parity Error Interrupt Flag */
|
||||
#define _LEUART_IF_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IF_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_PERR_DEFAULT (_LEUART_IF_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_FERR (0x1UL << 7) /**< Framing Error Interrupt Flag */
|
||||
#define _LEUART_IF_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IF_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_FERR_DEFAULT (_LEUART_IF_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_MPAF (0x1UL << 8) /**< Multi-Processor Address Frame Interrupt Flag */
|
||||
#define _LEUART_IF_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IF_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_MPAF_DEFAULT (_LEUART_IF_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_STARTF (0x1UL << 9) /**< Start Frame Interrupt Flag */
|
||||
#define _LEUART_IF_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IF_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_STARTF_DEFAULT (_LEUART_IF_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_SIGF (0x1UL << 10) /**< Signal Frame Interrupt Flag */
|
||||
#define _LEUART_IF_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IF_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IF */
|
||||
#define LEUART_IF_SIGF_DEFAULT (_LEUART_IF_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IF */
|
||||
|
||||
/* Bit fields for LEUART IFS */
|
||||
#define _LEUART_IFS_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFS */
|
||||
#define _LEUART_IFS_MASK 0x000007F9UL /**< Mask for LEUART_IFS */
|
||||
#define LEUART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
|
||||
#define _LEUART_IFS_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IFS_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXC_DEFAULT (_LEUART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXOF (0x1UL << 3) /**< Set RXOF Interrupt Flag */
|
||||
#define _LEUART_IFS_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IFS_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXOF_DEFAULT (_LEUART_IFS_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXUF (0x1UL << 4) /**< Set RXUF Interrupt Flag */
|
||||
#define _LEUART_IFS_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IFS_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_RXUF_DEFAULT (_LEUART_IFS_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXOF (0x1UL << 5) /**< Set TXOF Interrupt Flag */
|
||||
#define _LEUART_IFS_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IFS_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_TXOF_DEFAULT (_LEUART_IFS_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_PERR (0x1UL << 6) /**< Set PERR Interrupt Flag */
|
||||
#define _LEUART_IFS_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IFS_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_PERR_DEFAULT (_LEUART_IFS_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_FERR (0x1UL << 7) /**< Set FERR Interrupt Flag */
|
||||
#define _LEUART_IFS_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IFS_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_FERR_DEFAULT (_LEUART_IFS_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_MPAF (0x1UL << 8) /**< Set MPAF Interrupt Flag */
|
||||
#define _LEUART_IFS_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IFS_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_MPAF_DEFAULT (_LEUART_IFS_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_STARTF (0x1UL << 9) /**< Set STARTF Interrupt Flag */
|
||||
#define _LEUART_IFS_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IFS_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IFS_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_STARTF_DEFAULT (_LEUART_IFS_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_SIGF (0x1UL << 10) /**< Set SIGF Interrupt Flag */
|
||||
#define _LEUART_IFS_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IFS_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IFS_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFS */
|
||||
#define LEUART_IFS_SIGF_DEFAULT (_LEUART_IFS_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFS */
|
||||
|
||||
/* Bit fields for LEUART IFC */
|
||||
#define _LEUART_IFC_RESETVALUE 0x00000000UL /**< Default value for LEUART_IFC */
|
||||
#define _LEUART_IFC_MASK 0x000007F9UL /**< Mask for LEUART_IFC */
|
||||
#define LEUART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
|
||||
#define _LEUART_IFC_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IFC_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXC_DEFAULT (_LEUART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXOF (0x1UL << 3) /**< Clear RXOF Interrupt Flag */
|
||||
#define _LEUART_IFC_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IFC_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXOF_DEFAULT (_LEUART_IFC_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXUF (0x1UL << 4) /**< Clear RXUF Interrupt Flag */
|
||||
#define _LEUART_IFC_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IFC_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_RXUF_DEFAULT (_LEUART_IFC_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXOF (0x1UL << 5) /**< Clear TXOF Interrupt Flag */
|
||||
#define _LEUART_IFC_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IFC_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_TXOF_DEFAULT (_LEUART_IFC_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_PERR (0x1UL << 6) /**< Clear PERR Interrupt Flag */
|
||||
#define _LEUART_IFC_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IFC_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_PERR_DEFAULT (_LEUART_IFC_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_FERR (0x1UL << 7) /**< Clear FERR Interrupt Flag */
|
||||
#define _LEUART_IFC_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IFC_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_FERR_DEFAULT (_LEUART_IFC_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_MPAF (0x1UL << 8) /**< Clear MPAF Interrupt Flag */
|
||||
#define _LEUART_IFC_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IFC_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_MPAF_DEFAULT (_LEUART_IFC_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_STARTF (0x1UL << 9) /**< Clear STARTF Interrupt Flag */
|
||||
#define _LEUART_IFC_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IFC_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IFC_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_STARTF_DEFAULT (_LEUART_IFC_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_SIGF (0x1UL << 10) /**< Clear SIGF Interrupt Flag */
|
||||
#define _LEUART_IFC_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IFC_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IFC_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IFC */
|
||||
#define LEUART_IFC_SIGF_DEFAULT (_LEUART_IFC_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IFC */
|
||||
|
||||
/* Bit fields for LEUART IEN */
|
||||
#define _LEUART_IEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_IEN */
|
||||
#define _LEUART_IEN_MASK 0x000007FFUL /**< Mask for LEUART_IEN */
|
||||
#define LEUART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
|
||||
#define _LEUART_IEN_TXC_SHIFT 0 /**< Shift value for LEUART_TXC */
|
||||
#define _LEUART_IEN_TXC_MASK 0x1UL /**< Bit mask for LEUART_TXC */
|
||||
#define _LEUART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXC_DEFAULT (_LEUART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
|
||||
#define _LEUART_IEN_TXBL_SHIFT 1 /**< Shift value for LEUART_TXBL */
|
||||
#define _LEUART_IEN_TXBL_MASK 0x2UL /**< Bit mask for LEUART_TXBL */
|
||||
#define _LEUART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXBL_DEFAULT (_LEUART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
|
||||
#define _LEUART_IEN_RXDATAV_SHIFT 2 /**< Shift value for LEUART_RXDATAV */
|
||||
#define _LEUART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for LEUART_RXDATAV */
|
||||
#define _LEUART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXDATAV_DEFAULT (_LEUART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXOF (0x1UL << 3) /**< RXOF Interrupt Enable */
|
||||
#define _LEUART_IEN_RXOF_SHIFT 3 /**< Shift value for LEUART_RXOF */
|
||||
#define _LEUART_IEN_RXOF_MASK 0x8UL /**< Bit mask for LEUART_RXOF */
|
||||
#define _LEUART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXOF_DEFAULT (_LEUART_IEN_RXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXUF (0x1UL << 4) /**< RXUF Interrupt Enable */
|
||||
#define _LEUART_IEN_RXUF_SHIFT 4 /**< Shift value for LEUART_RXUF */
|
||||
#define _LEUART_IEN_RXUF_MASK 0x10UL /**< Bit mask for LEUART_RXUF */
|
||||
#define _LEUART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_RXUF_DEFAULT (_LEUART_IEN_RXUF_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXOF (0x1UL << 5) /**< TXOF Interrupt Enable */
|
||||
#define _LEUART_IEN_TXOF_SHIFT 5 /**< Shift value for LEUART_TXOF */
|
||||
#define _LEUART_IEN_TXOF_MASK 0x20UL /**< Bit mask for LEUART_TXOF */
|
||||
#define _LEUART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_TXOF_DEFAULT (_LEUART_IEN_TXOF_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_PERR (0x1UL << 6) /**< PERR Interrupt Enable */
|
||||
#define _LEUART_IEN_PERR_SHIFT 6 /**< Shift value for LEUART_PERR */
|
||||
#define _LEUART_IEN_PERR_MASK 0x40UL /**< Bit mask for LEUART_PERR */
|
||||
#define _LEUART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_PERR_DEFAULT (_LEUART_IEN_PERR_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_FERR (0x1UL << 7) /**< FERR Interrupt Enable */
|
||||
#define _LEUART_IEN_FERR_SHIFT 7 /**< Shift value for LEUART_FERR */
|
||||
#define _LEUART_IEN_FERR_MASK 0x80UL /**< Bit mask for LEUART_FERR */
|
||||
#define _LEUART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_FERR_DEFAULT (_LEUART_IEN_FERR_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_MPAF (0x1UL << 8) /**< MPAF Interrupt Enable */
|
||||
#define _LEUART_IEN_MPAF_SHIFT 8 /**< Shift value for LEUART_MPAF */
|
||||
#define _LEUART_IEN_MPAF_MASK 0x100UL /**< Bit mask for LEUART_MPAF */
|
||||
#define _LEUART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_MPAF_DEFAULT (_LEUART_IEN_MPAF_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_STARTF (0x1UL << 9) /**< STARTF Interrupt Enable */
|
||||
#define _LEUART_IEN_STARTF_SHIFT 9 /**< Shift value for LEUART_STARTF */
|
||||
#define _LEUART_IEN_STARTF_MASK 0x200UL /**< Bit mask for LEUART_STARTF */
|
||||
#define _LEUART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_STARTF_DEFAULT (_LEUART_IEN_STARTF_DEFAULT << 9) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_SIGF (0x1UL << 10) /**< SIGF Interrupt Enable */
|
||||
#define _LEUART_IEN_SIGF_SHIFT 10 /**< Shift value for LEUART_SIGF */
|
||||
#define _LEUART_IEN_SIGF_MASK 0x400UL /**< Bit mask for LEUART_SIGF */
|
||||
#define _LEUART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_IEN */
|
||||
#define LEUART_IEN_SIGF_DEFAULT (_LEUART_IEN_SIGF_DEFAULT << 10) /**< Shifted mode DEFAULT for LEUART_IEN */
|
||||
|
||||
/* Bit fields for LEUART PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_RESETVALUE 0x00000000UL /**< Default value for LEUART_PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_MASK 0x0000003FUL /**< Mask for LEUART_PULSECTRL */
|
||||
#define _LEUART_PULSECTRL_PULSEW_SHIFT 0 /**< Shift value for LEUART_PULSEW */
|
||||
#define _LEUART_PULSECTRL_PULSEW_MASK 0xFUL /**< Bit mask for LEUART_PULSEW */
|
||||
#define _LEUART_PULSECTRL_PULSEW_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEW_DEFAULT (_LEUART_PULSECTRL_PULSEW_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEEN (0x1UL << 4) /**< Pulse Generator/Extender Enable */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_SHIFT 4 /**< Shift value for LEUART_PULSEEN */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_MASK 0x10UL /**< Bit mask for LEUART_PULSEEN */
|
||||
#define _LEUART_PULSECTRL_PULSEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEEN_DEFAULT (_LEUART_PULSECTRL_PULSEEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEFILT (0x1UL << 5) /**< Pulse Filter */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_SHIFT 5 /**< Shift value for LEUART_PULSEFILT */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_MASK 0x20UL /**< Bit mask for LEUART_PULSEFILT */
|
||||
#define _LEUART_PULSECTRL_PULSEFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_PULSECTRL */
|
||||
#define LEUART_PULSECTRL_PULSEFILT_DEFAULT (_LEUART_PULSECTRL_PULSEFILT_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_PULSECTRL */
|
||||
|
||||
/* Bit fields for LEUART FREEZE */
|
||||
#define _LEUART_FREEZE_RESETVALUE 0x00000000UL /**< Default value for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_MASK 0x00000001UL /**< Mask for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _LEUART_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for LEUART_REGFREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for LEUART_REGFREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for LEUART_FREEZE */
|
||||
#define _LEUART_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_DEFAULT (_LEUART_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_UPDATE (_LEUART_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for LEUART_FREEZE */
|
||||
#define LEUART_FREEZE_REGFREEZE_FREEZE (_LEUART_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for LEUART_FREEZE */
|
||||
|
||||
/* Bit fields for LEUART SYNCBUSY */
|
||||
#define _LEUART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LEUART_SYNCBUSY */
|
||||
#define _LEUART_SYNCBUSY_MASK 0x000000FFUL /**< Mask for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for LEUART_CTRL */
|
||||
#define _LEUART_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for LEUART_CTRL */
|
||||
#define _LEUART_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CTRL_DEFAULT (_LEUART_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for LEUART_CMD */
|
||||
#define _LEUART_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for LEUART_CMD */
|
||||
#define _LEUART_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CMD_DEFAULT (_LEUART_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CLKDIV (0x1UL << 2) /**< CLKDIV Register Busy */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_SHIFT 2 /**< Shift value for LEUART_CLKDIV */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_MASK 0x4UL /**< Bit mask for LEUART_CLKDIV */
|
||||
#define _LEUART_SYNCBUSY_CLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_CLKDIV_DEFAULT (_LEUART_SYNCBUSY_CLKDIV_DEFAULT << 2) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_STARTFRAME (0x1UL << 3) /**< STARTFRAME Register Busy */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_SHIFT 3 /**< Shift value for LEUART_STARTFRAME */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_MASK 0x8UL /**< Bit mask for LEUART_STARTFRAME */
|
||||
#define _LEUART_SYNCBUSY_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_STARTFRAME_DEFAULT (_LEUART_SYNCBUSY_STARTFRAME_DEFAULT << 3) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_SIGFRAME (0x1UL << 4) /**< SIGFRAME Register Busy */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_SHIFT 4 /**< Shift value for LEUART_SIGFRAME */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_MASK 0x10UL /**< Bit mask for LEUART_SIGFRAME */
|
||||
#define _LEUART_SYNCBUSY_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_SIGFRAME_DEFAULT (_LEUART_SYNCBUSY_SIGFRAME_DEFAULT << 4) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATAX (0x1UL << 5) /**< TXDATAX Register Busy */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_SHIFT 5 /**< Shift value for LEUART_TXDATAX */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_MASK 0x20UL /**< Bit mask for LEUART_TXDATAX */
|
||||
#define _LEUART_SYNCBUSY_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATAX_DEFAULT (_LEUART_SYNCBUSY_TXDATAX_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATA (0x1UL << 6) /**< TXDATA Register Busy */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_SHIFT 6 /**< Shift value for LEUART_TXDATA */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_MASK 0x40UL /**< Bit mask for LEUART_TXDATA */
|
||||
#define _LEUART_SYNCBUSY_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_TXDATA_DEFAULT (_LEUART_SYNCBUSY_TXDATA_DEFAULT << 6) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_PULSECTRL (0x1UL << 7) /**< PULSECTRL Register Busy */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_SHIFT 7 /**< Shift value for LEUART_PULSECTRL */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_MASK 0x80UL /**< Bit mask for LEUART_PULSECTRL */
|
||||
#define _LEUART_SYNCBUSY_PULSECTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_SYNCBUSY */
|
||||
#define LEUART_SYNCBUSY_PULSECTRL_DEFAULT (_LEUART_SYNCBUSY_PULSECTRL_DEFAULT << 7) /**< Shifted mode DEFAULT for LEUART_SYNCBUSY */
|
||||
|
||||
/* Bit fields for LEUART ROUTEPEN */
|
||||
#define _LEUART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTEPEN */
|
||||
#define _LEUART_ROUTEPEN_MASK 0x00000003UL /**< Mask for LEUART_ROUTEPEN */
|
||||
#define LEUART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
|
||||
#define _LEUART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for LEUART_RXPEN */
|
||||
#define _LEUART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for LEUART_RXPEN */
|
||||
#define _LEUART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
|
||||
#define LEUART_ROUTEPEN_RXPEN_DEFAULT (_LEUART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
|
||||
#define LEUART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
|
||||
#define _LEUART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for LEUART_TXPEN */
|
||||
#define _LEUART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for LEUART_TXPEN */
|
||||
#define _LEUART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTEPEN */
|
||||
#define LEUART_ROUTEPEN_TXPEN_DEFAULT (_LEUART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for LEUART_ROUTEPEN */
|
||||
|
||||
/* Bit fields for LEUART ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_MASK 0x00000707UL /**< Mask for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for LEUART_RXLOC */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_MASK 0x7UL /**< Bit mask for LEUART_RXLOC */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC0 (_LEUART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_DEFAULT (_LEUART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC1 (_LEUART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC2 (_LEUART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC3 (_LEUART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC4 (_LEUART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_RXLOC_LOC5 (_LEUART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for LEUART_TXLOC */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_MASK 0x700UL /**< Bit mask for LEUART_TXLOC */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for LEUART_ROUTELOC0 */
|
||||
#define _LEUART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC0 (_LEUART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_DEFAULT (_LEUART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC1 (_LEUART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC2 (_LEUART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC3 (_LEUART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC4 (_LEUART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for LEUART_ROUTELOC0 */
|
||||
#define LEUART_ROUTELOC0_TXLOC_LOC5 (_LEUART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for LEUART_ROUTELOC0 */
|
||||
|
||||
/* Bit fields for LEUART INPUT */
|
||||
#define _LEUART_INPUT_RESETVALUE 0x00000000UL /**< Default value for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_MASK 0x0000003FUL /**< Mask for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for LEUART_RXPRSSEL */
|
||||
#define _LEUART_INPUT_RXPRSSEL_MASK 0x1FUL /**< Bit mask for LEUART_RXPRSSEL */
|
||||
#define _LEUART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for LEUART_INPUT */
|
||||
#define _LEUART_INPUT_RXPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_DEFAULT (_LEUART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH0 (_LEUART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH1 (_LEUART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH2 (_LEUART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH3 (_LEUART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH4 (_LEUART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH5 (_LEUART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH6 (_LEUART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH7 (_LEUART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH8 (_LEUART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH9 (_LEUART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH10 (_LEUART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH11 (_LEUART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH12 (_LEUART_INPUT_RXPRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH13 (_LEUART_INPUT_RXPRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH14 (_LEUART_INPUT_RXPRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH15 (_LEUART_INPUT_RXPRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH16 (_LEUART_INPUT_RXPRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH17 (_LEUART_INPUT_RXPRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH18 (_LEUART_INPUT_RXPRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH19 (_LEUART_INPUT_RXPRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH20 (_LEUART_INPUT_RXPRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH21 (_LEUART_INPUT_RXPRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH22 (_LEUART_INPUT_RXPRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRSSEL_PRSCH23 (_LEUART_INPUT_RXPRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRS (0x1UL << 5) /**< PRS RX Enable */
|
||||
#define _LEUART_INPUT_RXPRS_SHIFT 5 /**< Shift value for LEUART_RXPRS */
|
||||
#define _LEUART_INPUT_RXPRS_MASK 0x20UL /**< Bit mask for LEUART_RXPRS */
|
||||
#define _LEUART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LEUART_INPUT */
|
||||
#define LEUART_INPUT_RXPRS_DEFAULT (_LEUART_INPUT_RXPRS_DEFAULT << 5) /**< Shifted mode DEFAULT for LEUART_INPUT */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_LEUART */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
847
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h
vendored
Normal file
847
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_msc.h
vendored
Normal file
@ -0,0 +1,847 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_MSC register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_MSC MSC
|
||||
* @{
|
||||
* @brief EFM32GG11B_MSC Register Declaration
|
||||
******************************************************************************/
|
||||
/** MSC Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Memory System Control Register */
|
||||
__IOM uint32_t READCTRL; /**< Read Control Register */
|
||||
__IOM uint32_t WRITECTRL; /**< Write Control Register */
|
||||
__IOM uint32_t WRITECMD; /**< Write Command Register */
|
||||
__IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t WDATA; /**< Write Data Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
__IOM uint32_t LOCK; /**< Configuration Lock Register */
|
||||
__IOM uint32_t CACHECMD; /**< Flash Cache Command Register */
|
||||
__IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
|
||||
__IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
|
||||
|
||||
uint32_t RESERVED2[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
|
||||
|
||||
uint32_t RESERVED3[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t STARTUP; /**< Startup Control */
|
||||
|
||||
uint32_t RESERVED4[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BANKSWITCHLOCK; /**< Bank Switching Lock Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
|
||||
uint32_t RESERVED5[6U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t BOOTLOADERCTRL; /**< Bootloader Read and Write Enable, Write Once Register */
|
||||
__IOM uint32_t AAPUNLOCKCMD; /**< Software Unlock AAP Command Register */
|
||||
__IOM uint32_t CACHECONFIG0; /**< Cache Configuration Register 0 */
|
||||
|
||||
uint32_t RESERVED6[25U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t RAMCTRL; /**< RAM Control Enable Register */
|
||||
__IOM uint32_t ECCCTRL; /**< RAM ECC Control Register */
|
||||
__IM uint32_t RAMECCADDR; /**< RAM ECC Error Address Register */
|
||||
__IM uint32_t RAM1ECCADDR; /**< RAM1 ECC Error Address Register */
|
||||
} MSC_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_MSC
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_MSC_BitFields MSC Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for MSC CTRL */
|
||||
#define _MSC_CTRL_RESETVALUE 0x00000021UL /**< Default value for MSC_CTRL */
|
||||
#define _MSC_CTRL_MASK 0x0000107FUL /**< Mask for MSC_CTRL */
|
||||
#define MSC_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for MSC_ADDRFAULTEN */
|
||||
#define _MSC_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for MSC_ADDRFAULTEN */
|
||||
#define _MSC_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_ADDRFAULTEN_DEFAULT (_MSC_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_CLKDISFAULTEN (0x1UL << 1) /**< Clock-disabled Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_CLKDISFAULTEN_SHIFT 1 /**< Shift value for MSC_CLKDISFAULTEN */
|
||||
#define _MSC_CTRL_CLKDISFAULTEN_MASK 0x2UL /**< Bit mask for MSC_CLKDISFAULTEN */
|
||||
#define _MSC_CTRL_CLKDISFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_CLKDISFAULTEN_DEFAULT (_MSC_CTRL_CLKDISFAULTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_PWRUPONDEMAND (0x1UL << 2) /**< Power Up on Demand During Wake Up */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_SHIFT 2 /**< Shift value for MSC_PWRUPONDEMAND */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_MASK 0x4UL /**< Bit mask for MSC_PWRUPONDEMAND */
|
||||
#define _MSC_CTRL_PWRUPONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_PWRUPONDEMAND_DEFAULT (_MSC_CTRL_PWRUPONDEMAND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_IFCREADCLEAR (0x1UL << 3) /**< IFC Read Clears IF */
|
||||
#define _MSC_CTRL_IFCREADCLEAR_SHIFT 3 /**< Shift value for MSC_IFCREADCLEAR */
|
||||
#define _MSC_CTRL_IFCREADCLEAR_MASK 0x8UL /**< Bit mask for MSC_IFCREADCLEAR */
|
||||
#define _MSC_CTRL_IFCREADCLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_IFCREADCLEAR_DEFAULT (_MSC_CTRL_IFCREADCLEAR_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_TIMEOUTFAULTEN (0x1UL << 4) /**< Timeout Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_TIMEOUTFAULTEN_SHIFT 4 /**< Shift value for MSC_TIMEOUTFAULTEN */
|
||||
#define _MSC_CTRL_TIMEOUTFAULTEN_MASK 0x10UL /**< Bit mask for MSC_TIMEOUTFAULTEN */
|
||||
#define _MSC_CTRL_TIMEOUTFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_TIMEOUTFAULTEN_DEFAULT (_MSC_CTRL_TIMEOUTFAULTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two Bit ECC Error Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for MSC_RAMECCERRFAULTEN */
|
||||
#define _MSC_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for MSC_RAMECCERRFAULTEN */
|
||||
#define _MSC_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_RAMECCERRFAULTEN_DEFAULT (_MSC_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_EBIFAULTEN (0x1UL << 6) /**< EBI Bus Fault Response Enable */
|
||||
#define _MSC_CTRL_EBIFAULTEN_SHIFT 6 /**< Shift value for MSC_EBIFAULTEN */
|
||||
#define _MSC_CTRL_EBIFAULTEN_MASK 0x40UL /**< Bit mask for MSC_EBIFAULTEN */
|
||||
#define _MSC_CTRL_EBIFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_EBIFAULTEN_DEFAULT (_MSC_CTRL_EBIFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_WAITMODE (0x1UL << 12) /**< Peripheral Access Wait Mode */
|
||||
#define _MSC_CTRL_WAITMODE_SHIFT 12 /**< Shift value for MSC_WAITMODE */
|
||||
#define _MSC_CTRL_WAITMODE_MASK 0x1000UL /**< Bit mask for MSC_WAITMODE */
|
||||
#define _MSC_CTRL_WAITMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CTRL */
|
||||
#define _MSC_CTRL_WAITMODE_WS0 0x00000000UL /**< Mode WS0 for MSC_CTRL */
|
||||
#define _MSC_CTRL_WAITMODE_WS1 0x00000001UL /**< Mode WS1 for MSC_CTRL */
|
||||
#define MSC_CTRL_WAITMODE_DEFAULT (_MSC_CTRL_WAITMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_CTRL */
|
||||
#define MSC_CTRL_WAITMODE_WS0 (_MSC_CTRL_WAITMODE_WS0 << 12) /**< Shifted mode WS0 for MSC_CTRL */
|
||||
#define MSC_CTRL_WAITMODE_WS1 (_MSC_CTRL_WAITMODE_WS1 << 12) /**< Shifted mode WS1 for MSC_CTRL */
|
||||
|
||||
/* Bit fields for MSC READCTRL */
|
||||
#define _MSC_READCTRL_RESETVALUE 0x01000100UL /**< Default value for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MASK 0x13000778UL /**< Mask for MSC_READCTRL */
|
||||
#define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
|
||||
#define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
|
||||
#define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
|
||||
#define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
|
||||
#define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
|
||||
#define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
|
||||
#define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
|
||||
#define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
|
||||
#define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
|
||||
#define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
|
||||
#define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
|
||||
#define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
|
||||
#define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_PREFETCH (0x1UL << 8) /**< Prefetch Mode */
|
||||
#define _MSC_READCTRL_PREFETCH_SHIFT 8 /**< Shift value for MSC_PREFETCH */
|
||||
#define _MSC_READCTRL_PREFETCH_MASK 0x100UL /**< Bit mask for MSC_PREFETCH */
|
||||
#define _MSC_READCTRL_PREFETCH_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_PREFETCH_DEFAULT (_MSC_READCTRL_PREFETCH_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_USEHPROT (0x1UL << 9) /**< AHB_HPROT Mode */
|
||||
#define _MSC_READCTRL_USEHPROT_SHIFT 9 /**< Shift value for MSC_USEHPROT */
|
||||
#define _MSC_READCTRL_USEHPROT_MASK 0x200UL /**< Bit mask for MSC_USEHPROT */
|
||||
#define _MSC_READCTRL_USEHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_USEHPROT_DEFAULT (_MSC_READCTRL_USEHPROT_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_QSPICDIS (0x1UL << 10) /**< QSPI Cache Disable */
|
||||
#define _MSC_READCTRL_QSPICDIS_SHIFT 10 /**< Shift value for MSC_QSPICDIS */
|
||||
#define _MSC_READCTRL_QSPICDIS_MASK 0x400UL /**< Bit mask for MSC_QSPICDIS */
|
||||
#define _MSC_READCTRL_QSPICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_QSPICDIS_DEFAULT (_MSC_READCTRL_QSPICDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_SHIFT 24 /**< Shift value for MSC_MODE */
|
||||
#define _MSC_READCTRL_MODE_MASK 0x3000000UL /**< Bit mask for MSC_MODE */
|
||||
#define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS2 0x00000002UL /**< Mode WS2 for MSC_READCTRL */
|
||||
#define _MSC_READCTRL_MODE_WS3 0x00000003UL /**< Mode WS3 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 24) /**< Shifted mode WS0 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 24) /**< Shifted mode WS1 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 24) /**< Shifted mode WS2 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_MODE_WS3 (_MSC_READCTRL_MODE_WS3 << 24) /**< Shifted mode WS3 for MSC_READCTRL */
|
||||
#define MSC_READCTRL_SCBTP (0x1UL << 28) /**< Suppress Conditional Branch Target Perfetch */
|
||||
#define _MSC_READCTRL_SCBTP_SHIFT 28 /**< Shift value for MSC_SCBTP */
|
||||
#define _MSC_READCTRL_SCBTP_MASK 0x10000000UL /**< Bit mask for MSC_SCBTP */
|
||||
#define _MSC_READCTRL_SCBTP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
|
||||
#define MSC_READCTRL_SCBTP_DEFAULT (_MSC_READCTRL_SCBTP_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_READCTRL */
|
||||
|
||||
/* Bit fields for MSC WRITECTRL */
|
||||
#define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
|
||||
#define _MSC_WRITECTRL_MASK 0x00000023UL /**< Mask for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
|
||||
#define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
|
||||
#define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
|
||||
#define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
|
||||
#define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_RWWEN (0x1UL << 5) /**< Read-While-Write Enable */
|
||||
#define _MSC_WRITECTRL_RWWEN_SHIFT 5 /**< Shift value for MSC_RWWEN */
|
||||
#define _MSC_WRITECTRL_RWWEN_MASK 0x20UL /**< Bit mask for MSC_RWWEN */
|
||||
#define _MSC_WRITECTRL_RWWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
|
||||
#define MSC_WRITECTRL_RWWEN_DEFAULT (_MSC_WRITECTRL_RWWEN_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
|
||||
|
||||
/* Bit fields for MSC WRITECMD */
|
||||
#define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
|
||||
#define _MSC_WRITECMD_MASK 0x0000133FUL /**< Mask for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB Into ADDR */
|
||||
#define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
|
||||
#define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
|
||||
#define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
|
||||
#define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
|
||||
#define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
|
||||
#define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
|
||||
#define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
|
||||
#define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
|
||||
#define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
|
||||
#define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
|
||||
#define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
|
||||
#define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort Erase Sequence */
|
||||
#define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
|
||||
#define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
|
||||
#define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass Erase Region 0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN1 (0x1UL << 9) /**< Mass Erase Region 1 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN1_SHIFT 9 /**< Shift value for MSC_ERASEMAIN1 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN1_MASK 0x200UL /**< Bit mask for MSC_ERASEMAIN1 */
|
||||
#define _MSC_WRITECMD_ERASEMAIN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_ERASEMAIN1_DEFAULT (_MSC_WRITECMD_ERASEMAIN1_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA State */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
|
||||
#define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
|
||||
#define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
|
||||
|
||||
/* Bit fields for MSC ADDRB */
|
||||
#define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
|
||||
#define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
|
||||
#define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
|
||||
|
||||
/* Bit fields for MSC WDATA */
|
||||
#define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
|
||||
#define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
|
||||
#define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
|
||||
#define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
|
||||
|
||||
/* Bit fields for MSC STATUS */
|
||||
#define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
|
||||
#define _MSC_STATUS_MASK 0xFF0000FFUL /**< Mask for MSC_STATUS */
|
||||
#define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
|
||||
#define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
|
||||
#define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
|
||||
#define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
|
||||
#define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
|
||||
#define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
|
||||
#define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
|
||||
#define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
|
||||
#define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
|
||||
#define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
|
||||
#define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
|
||||
#define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
|
||||
#define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
|
||||
#define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
|
||||
#define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
|
||||
#define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
|
||||
#define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
|
||||
#define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
|
||||
#define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
|
||||
#define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_BANKSWITCHED (0x1UL << 7) /**< BANK SWITCHING STATUS */
|
||||
#define _MSC_STATUS_BANKSWITCHED_SHIFT 7 /**< Shift value for MSC_BANKSWITCHED */
|
||||
#define _MSC_STATUS_BANKSWITCHED_MASK 0x80UL /**< Bit mask for MSC_BANKSWITCHED */
|
||||
#define _MSC_STATUS_BANKSWITCHED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_BANKSWITCHED_DEFAULT (_MSC_STATUS_BANKSWITCHED_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define _MSC_STATUS_WDATAVALID_SHIFT 24 /**< Shift value for MSC_WDATAVALID */
|
||||
#define _MSC_STATUS_WDATAVALID_MASK 0xF000000UL /**< Bit mask for MSC_WDATAVALID */
|
||||
#define _MSC_STATUS_WDATAVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_WDATAVALID_DEFAULT (_MSC_STATUS_WDATAVALID_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_SHIFT 28 /**< Shift value for MSC_PWRUPCKBDFAILCOUNT */
|
||||
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_MASK 0xF0000000UL /**< Bit mask for MSC_PWRUPCKBDFAILCOUNT */
|
||||
#define _MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
|
||||
#define MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT (_MSC_STATUS_PWRUPCKBDFAILCOUNT_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STATUS */
|
||||
|
||||
/* Bit fields for MSC IF */
|
||||
#define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
|
||||
#define _MSC_IF_MASK 0x000F017FUL /**< Mask for MSC_IF */
|
||||
#define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
|
||||
#define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
|
||||
#define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
|
||||
#define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
|
||||
#define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
|
||||
#define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
|
||||
#define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
|
||||
#define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
|
||||
#define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_PWRUPF (0x1UL << 4) /**< Flash Power Up Sequence Complete Flag */
|
||||
#define _MSC_IF_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
|
||||
#define _MSC_IF_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
|
||||
#define _MSC_IF_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_PWRUPF_DEFAULT (_MSC_IF_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_ICACHERR (0x1UL << 5) /**< ICache RAM Parity Error Flag */
|
||||
#define _MSC_IF_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
|
||||
#define _MSC_IF_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
|
||||
#define _MSC_IF_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_ICACHERR_DEFAULT (_MSC_IF_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WDATAOV (0x1UL << 6) /**< Flash Controller Write Buffer Overflow */
|
||||
#define _MSC_IF_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
|
||||
#define _MSC_IF_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
|
||||
#define _MSC_IF_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_WDATAOV_DEFAULT (_MSC_IF_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_LVEWRITE (0x1UL << 8) /**< Flash LVE Write Error Flag */
|
||||
#define _MSC_IF_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
|
||||
#define _MSC_IF_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
|
||||
#define _MSC_IF_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_LVEWRITE_DEFAULT (_MSC_IF_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt Flag */
|
||||
#define _MSC_IF_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */
|
||||
#define _MSC_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */
|
||||
#define _MSC_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAMERR1B_DEFAULT (_MSC_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt Flag */
|
||||
#define _MSC_IF_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */
|
||||
#define _MSC_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */
|
||||
#define _MSC_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAMERR2B_DEFAULT (_MSC_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAM1ERR1B (0x1UL << 18) /**< RAM1 1-bit ECC Error Interrupt Flag */
|
||||
#define _MSC_IF_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */
|
||||
#define _MSC_IF_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */
|
||||
#define _MSC_IF_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAM1ERR1B_DEFAULT (_MSC_IF_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAM1ERR2B (0x1UL << 19) /**< RAM1 2-bit ECC Error Interrupt Flag */
|
||||
#define _MSC_IF_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */
|
||||
#define _MSC_IF_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */
|
||||
#define _MSC_IF_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
|
||||
#define MSC_IF_RAM1ERR2B_DEFAULT (_MSC_IF_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IF */
|
||||
|
||||
/* Bit fields for MSC IFS */
|
||||
#define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
|
||||
#define _MSC_IFS_MASK 0x000F017FUL /**< Mask for MSC_IFS */
|
||||
#define MSC_IFS_ERASE (0x1UL << 0) /**< Set ERASE Interrupt Flag */
|
||||
#define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WRITE (0x1UL << 1) /**< Set WRITE Interrupt Flag */
|
||||
#define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_CHOF (0x1UL << 2) /**< Set CHOF Interrupt Flag */
|
||||
#define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
|
||||
#define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
|
||||
#define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_CMOF (0x1UL << 3) /**< Set CMOF Interrupt Flag */
|
||||
#define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
|
||||
#define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
|
||||
#define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_PWRUPF (0x1UL << 4) /**< Set PWRUPF Interrupt Flag */
|
||||
#define _MSC_IFS_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
|
||||
#define _MSC_IFS_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
|
||||
#define _MSC_IFS_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_PWRUPF_DEFAULT (_MSC_IFS_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_ICACHERR (0x1UL << 5) /**< Set ICACHERR Interrupt Flag */
|
||||
#define _MSC_IFS_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
|
||||
#define _MSC_IFS_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
|
||||
#define _MSC_IFS_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_ICACHERR_DEFAULT (_MSC_IFS_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WDATAOV (0x1UL << 6) /**< Set WDATAOV Interrupt Flag */
|
||||
#define _MSC_IFS_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
|
||||
#define _MSC_IFS_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
|
||||
#define _MSC_IFS_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_WDATAOV_DEFAULT (_MSC_IFS_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_LVEWRITE (0x1UL << 8) /**< Set LVEWRITE Interrupt Flag */
|
||||
#define _MSC_IFS_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
|
||||
#define _MSC_IFS_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
|
||||
#define _MSC_IFS_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_LVEWRITE_DEFAULT (_MSC_IFS_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAMERR1B (0x1UL << 16) /**< Set RAMERR1B Interrupt Flag */
|
||||
#define _MSC_IFS_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */
|
||||
#define _MSC_IFS_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */
|
||||
#define _MSC_IFS_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAMERR1B_DEFAULT (_MSC_IFS_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAMERR2B (0x1UL << 17) /**< Set RAMERR2B Interrupt Flag */
|
||||
#define _MSC_IFS_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */
|
||||
#define _MSC_IFS_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */
|
||||
#define _MSC_IFS_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAMERR2B_DEFAULT (_MSC_IFS_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAM1ERR1B (0x1UL << 18) /**< Set RAM1ERR1B Interrupt Flag */
|
||||
#define _MSC_IFS_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */
|
||||
#define _MSC_IFS_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */
|
||||
#define _MSC_IFS_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAM1ERR1B_DEFAULT (_MSC_IFS_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAM1ERR2B (0x1UL << 19) /**< Set RAM1ERR2B Interrupt Flag */
|
||||
#define _MSC_IFS_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */
|
||||
#define _MSC_IFS_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */
|
||||
#define _MSC_IFS_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
|
||||
#define MSC_IFS_RAM1ERR2B_DEFAULT (_MSC_IFS_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFS */
|
||||
|
||||
/* Bit fields for MSC IFC */
|
||||
#define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
|
||||
#define _MSC_IFC_MASK 0x000F017FUL /**< Mask for MSC_IFC */
|
||||
#define MSC_IFC_ERASE (0x1UL << 0) /**< Clear ERASE Interrupt Flag */
|
||||
#define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WRITE (0x1UL << 1) /**< Clear WRITE Interrupt Flag */
|
||||
#define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_CHOF (0x1UL << 2) /**< Clear CHOF Interrupt Flag */
|
||||
#define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
|
||||
#define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
|
||||
#define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_CMOF (0x1UL << 3) /**< Clear CMOF Interrupt Flag */
|
||||
#define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
|
||||
#define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
|
||||
#define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_PWRUPF (0x1UL << 4) /**< Clear PWRUPF Interrupt Flag */
|
||||
#define _MSC_IFC_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
|
||||
#define _MSC_IFC_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
|
||||
#define _MSC_IFC_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_PWRUPF_DEFAULT (_MSC_IFC_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_ICACHERR (0x1UL << 5) /**< Clear ICACHERR Interrupt Flag */
|
||||
#define _MSC_IFC_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
|
||||
#define _MSC_IFC_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
|
||||
#define _MSC_IFC_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_ICACHERR_DEFAULT (_MSC_IFC_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WDATAOV (0x1UL << 6) /**< Clear WDATAOV Interrupt Flag */
|
||||
#define _MSC_IFC_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
|
||||
#define _MSC_IFC_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
|
||||
#define _MSC_IFC_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_WDATAOV_DEFAULT (_MSC_IFC_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_LVEWRITE (0x1UL << 8) /**< Clear LVEWRITE Interrupt Flag */
|
||||
#define _MSC_IFC_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
|
||||
#define _MSC_IFC_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
|
||||
#define _MSC_IFC_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_LVEWRITE_DEFAULT (_MSC_IFC_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAMERR1B (0x1UL << 16) /**< Clear RAMERR1B Interrupt Flag */
|
||||
#define _MSC_IFC_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */
|
||||
#define _MSC_IFC_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */
|
||||
#define _MSC_IFC_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAMERR1B_DEFAULT (_MSC_IFC_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAMERR2B (0x1UL << 17) /**< Clear RAMERR2B Interrupt Flag */
|
||||
#define _MSC_IFC_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */
|
||||
#define _MSC_IFC_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */
|
||||
#define _MSC_IFC_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAMERR2B_DEFAULT (_MSC_IFC_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAM1ERR1B (0x1UL << 18) /**< Clear RAM1ERR1B Interrupt Flag */
|
||||
#define _MSC_IFC_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */
|
||||
#define _MSC_IFC_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */
|
||||
#define _MSC_IFC_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAM1ERR1B_DEFAULT (_MSC_IFC_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAM1ERR2B (0x1UL << 19) /**< Clear RAM1ERR2B Interrupt Flag */
|
||||
#define _MSC_IFC_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */
|
||||
#define _MSC_IFC_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */
|
||||
#define _MSC_IFC_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
|
||||
#define MSC_IFC_RAM1ERR2B_DEFAULT (_MSC_IFC_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IFC */
|
||||
|
||||
/* Bit fields for MSC IEN */
|
||||
#define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
|
||||
#define _MSC_IEN_MASK 0x000F017FUL /**< Mask for MSC_IEN */
|
||||
#define MSC_IEN_ERASE (0x1UL << 0) /**< ERASE Interrupt Enable */
|
||||
#define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
|
||||
#define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
|
||||
#define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WRITE (0x1UL << 1) /**< WRITE Interrupt Enable */
|
||||
#define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
|
||||
#define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
|
||||
#define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_CHOF (0x1UL << 2) /**< CHOF Interrupt Enable */
|
||||
#define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
|
||||
#define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
|
||||
#define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_CMOF (0x1UL << 3) /**< CMOF Interrupt Enable */
|
||||
#define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
|
||||
#define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
|
||||
#define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_PWRUPF (0x1UL << 4) /**< PWRUPF Interrupt Enable */
|
||||
#define _MSC_IEN_PWRUPF_SHIFT 4 /**< Shift value for MSC_PWRUPF */
|
||||
#define _MSC_IEN_PWRUPF_MASK 0x10UL /**< Bit mask for MSC_PWRUPF */
|
||||
#define _MSC_IEN_PWRUPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_PWRUPF_DEFAULT (_MSC_IEN_PWRUPF_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_ICACHERR (0x1UL << 5) /**< ICACHERR Interrupt Enable */
|
||||
#define _MSC_IEN_ICACHERR_SHIFT 5 /**< Shift value for MSC_ICACHERR */
|
||||
#define _MSC_IEN_ICACHERR_MASK 0x20UL /**< Bit mask for MSC_ICACHERR */
|
||||
#define _MSC_IEN_ICACHERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_ICACHERR_DEFAULT (_MSC_IEN_ICACHERR_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WDATAOV (0x1UL << 6) /**< WDATAOV Interrupt Enable */
|
||||
#define _MSC_IEN_WDATAOV_SHIFT 6 /**< Shift value for MSC_WDATAOV */
|
||||
#define _MSC_IEN_WDATAOV_MASK 0x40UL /**< Bit mask for MSC_WDATAOV */
|
||||
#define _MSC_IEN_WDATAOV_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_WDATAOV_DEFAULT (_MSC_IEN_WDATAOV_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_LVEWRITE (0x1UL << 8) /**< LVEWRITE Interrupt Enable */
|
||||
#define _MSC_IEN_LVEWRITE_SHIFT 8 /**< Shift value for MSC_LVEWRITE */
|
||||
#define _MSC_IEN_LVEWRITE_MASK 0x100UL /**< Bit mask for MSC_LVEWRITE */
|
||||
#define _MSC_IEN_LVEWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_LVEWRITE_DEFAULT (_MSC_IEN_LVEWRITE_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAMERR1B (0x1UL << 16) /**< RAMERR1B Interrupt Enable */
|
||||
#define _MSC_IEN_RAMERR1B_SHIFT 16 /**< Shift value for MSC_RAMERR1B */
|
||||
#define _MSC_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for MSC_RAMERR1B */
|
||||
#define _MSC_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAMERR1B_DEFAULT (_MSC_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAMERR2B (0x1UL << 17) /**< RAMERR2B Interrupt Enable */
|
||||
#define _MSC_IEN_RAMERR2B_SHIFT 17 /**< Shift value for MSC_RAMERR2B */
|
||||
#define _MSC_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for MSC_RAMERR2B */
|
||||
#define _MSC_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAMERR2B_DEFAULT (_MSC_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAM1ERR1B (0x1UL << 18) /**< RAM1ERR1B Interrupt Enable */
|
||||
#define _MSC_IEN_RAM1ERR1B_SHIFT 18 /**< Shift value for MSC_RAM1ERR1B */
|
||||
#define _MSC_IEN_RAM1ERR1B_MASK 0x40000UL /**< Bit mask for MSC_RAM1ERR1B */
|
||||
#define _MSC_IEN_RAM1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAM1ERR1B_DEFAULT (_MSC_IEN_RAM1ERR1B_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAM1ERR2B (0x1UL << 19) /**< RAM1ERR2B Interrupt Enable */
|
||||
#define _MSC_IEN_RAM1ERR2B_SHIFT 19 /**< Shift value for MSC_RAM1ERR2B */
|
||||
#define _MSC_IEN_RAM1ERR2B_MASK 0x80000UL /**< Bit mask for MSC_RAM1ERR2B */
|
||||
#define _MSC_IEN_RAM1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
|
||||
#define MSC_IEN_RAM1ERR2B_DEFAULT (_MSC_IEN_RAM1ERR2B_DEFAULT << 19) /**< Shifted mode DEFAULT for MSC_IEN */
|
||||
|
||||
/* Bit fields for MSC LOCK */
|
||||
#define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
|
||||
#define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
|
||||
#define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
|
||||
#define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
|
||||
#define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
|
||||
#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
|
||||
|
||||
/* Bit fields for MSC CACHECMD */
|
||||
#define _MSC_CACHECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHECMD */
|
||||
#define _MSC_CACHECMD_MASK 0x00000007UL /**< Mask for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
|
||||
#define _MSC_CACHECMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
|
||||
#define _MSC_CACHECMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
|
||||
#define _MSC_CACHECMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_INVCACHE_DEFAULT (_MSC_CACHECMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
|
||||
#define _MSC_CACHECMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
|
||||
#define _MSC_CACHECMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
|
||||
#define _MSC_CACHECMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_STARTPC_DEFAULT (_MSC_CACHECMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
|
||||
#define _MSC_CACHECMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
|
||||
#define _MSC_CACHECMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
|
||||
#define _MSC_CACHECMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHECMD */
|
||||
#define MSC_CACHECMD_STOPPC_DEFAULT (_MSC_CACHECMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CACHECMD */
|
||||
|
||||
/* Bit fields for MSC CACHEHITS */
|
||||
#define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
|
||||
#define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
|
||||
#define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
|
||||
#define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
|
||||
#define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
|
||||
#define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
|
||||
|
||||
/* Bit fields for MSC CACHEMISSES */
|
||||
#define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
|
||||
#define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
|
||||
#define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
|
||||
#define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
|
||||
#define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
|
||||
#define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
|
||||
|
||||
/* Bit fields for MSC MASSLOCK */
|
||||
#define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
|
||||
#define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
|
||||
#define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
|
||||
#define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
|
||||
#define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
|
||||
#define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
|
||||
#define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
|
||||
|
||||
/* Bit fields for MSC STARTUP */
|
||||
#define _MSC_STARTUP_RESETVALUE 0x13001054UL /**< Default value for MSC_STARTUP */
|
||||
#define _MSC_STARTUP_MASK 0x773FF3FFUL /**< Mask for MSC_STARTUP */
|
||||
#define _MSC_STARTUP_STDLY0_SHIFT 0 /**< Shift value for MSC_STDLY0 */
|
||||
#define _MSC_STARTUP_STDLY0_MASK 0x3FFUL /**< Bit mask for MSC_STDLY0 */
|
||||
#define _MSC_STARTUP_STDLY0_DEFAULT 0x00000054UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STDLY0_DEFAULT (_MSC_STARTUP_STDLY0_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
#define _MSC_STARTUP_STDLY1_SHIFT 12 /**< Shift value for MSC_STDLY1 */
|
||||
#define _MSC_STARTUP_STDLY1_MASK 0x3FF000UL /**< Bit mask for MSC_STDLY1 */
|
||||
#define _MSC_STARTUP_STDLY1_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STDLY1_DEFAULT (_MSC_STARTUP_STDLY1_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_ASTWAIT (0x1UL << 24) /**< Active Startup Wait */
|
||||
#define _MSC_STARTUP_ASTWAIT_SHIFT 24 /**< Shift value for MSC_ASTWAIT */
|
||||
#define _MSC_STARTUP_ASTWAIT_MASK 0x1000000UL /**< Bit mask for MSC_ASTWAIT */
|
||||
#define _MSC_STARTUP_ASTWAIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_ASTWAIT_DEFAULT (_MSC_STARTUP_ASTWAIT_DEFAULT << 24) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STWSEN (0x1UL << 25) /**< Startup Waitstates Enable */
|
||||
#define _MSC_STARTUP_STWSEN_SHIFT 25 /**< Shift value for MSC_STWSEN */
|
||||
#define _MSC_STARTUP_STWSEN_MASK 0x2000000UL /**< Bit mask for MSC_STWSEN */
|
||||
#define _MSC_STARTUP_STWSEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STWSEN_DEFAULT (_MSC_STARTUP_STWSEN_DEFAULT << 25) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STWSAEN (0x1UL << 26) /**< Startup Waitstates Always Enable */
|
||||
#define _MSC_STARTUP_STWSAEN_SHIFT 26 /**< Shift value for MSC_STWSAEN */
|
||||
#define _MSC_STARTUP_STWSAEN_MASK 0x4000000UL /**< Bit mask for MSC_STWSAEN */
|
||||
#define _MSC_STARTUP_STWSAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STWSAEN_DEFAULT (_MSC_STARTUP_STWSAEN_DEFAULT << 26) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
#define _MSC_STARTUP_STWS_SHIFT 28 /**< Shift value for MSC_STWS */
|
||||
#define _MSC_STARTUP_STWS_MASK 0x70000000UL /**< Bit mask for MSC_STWS */
|
||||
#define _MSC_STARTUP_STWS_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STARTUP */
|
||||
#define MSC_STARTUP_STWS_DEFAULT (_MSC_STARTUP_STWS_DEFAULT << 28) /**< Shifted mode DEFAULT for MSC_STARTUP */
|
||||
|
||||
/* Bit fields for MSC BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_SHIFT 0 /**< Shift value for MSC_BANKSWITCHLOCKKEY */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_BANKSWITCHLOCKKEY */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_BANKSWITCHLOCK */
|
||||
#define _MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK 0x00007C2BUL /**< Mode UNLOCK for MSC_BANKSWITCHLOCK */
|
||||
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_BANKSWITCHLOCK */
|
||||
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_BANKSWITCHLOCK */
|
||||
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BANKSWITCHLOCK */
|
||||
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_BANKSWITCHLOCK */
|
||||
#define MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK (_MSC_BANKSWITCHLOCK_BANKSWITCHLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_BANKSWITCHLOCK */
|
||||
|
||||
/* Bit fields for MSC CMD */
|
||||
#define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
|
||||
#define _MSC_CMD_MASK 0x00000003UL /**< Mask for MSC_CMD */
|
||||
#define MSC_CMD_PWRUP (0x1UL << 0) /**< Flash Power Up Command */
|
||||
#define _MSC_CMD_PWRUP_SHIFT 0 /**< Shift value for MSC_PWRUP */
|
||||
#define _MSC_CMD_PWRUP_MASK 0x1UL /**< Bit mask for MSC_PWRUP */
|
||||
#define _MSC_CMD_PWRUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
|
||||
#define MSC_CMD_PWRUP_DEFAULT (_MSC_CMD_PWRUP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
|
||||
#define MSC_CMD_SWITCHINGBANK (0x1UL << 1) /**< BANK SWITCHING COMMAND */
|
||||
#define _MSC_CMD_SWITCHINGBANK_SHIFT 1 /**< Shift value for MSC_SWITCHINGBANK */
|
||||
#define _MSC_CMD_SWITCHINGBANK_MASK 0x2UL /**< Bit mask for MSC_SWITCHINGBANK */
|
||||
#define _MSC_CMD_SWITCHINGBANK_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
|
||||
#define MSC_CMD_SWITCHINGBANK_DEFAULT (_MSC_CMD_SWITCHINGBANK_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
|
||||
|
||||
/* Bit fields for MSC BOOTLOADERCTRL */
|
||||
#define _MSC_BOOTLOADERCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_BOOTLOADERCTRL */
|
||||
#define _MSC_BOOTLOADERCTRL_MASK 0x00000003UL /**< Mask for MSC_BOOTLOADERCTRL */
|
||||
#define MSC_BOOTLOADERCTRL_BLRDIS (0x1UL << 0) /**< Flash Bootloader Read Disable */
|
||||
#define _MSC_BOOTLOADERCTRL_BLRDIS_SHIFT 0 /**< Shift value for MSC_BLRDIS */
|
||||
#define _MSC_BOOTLOADERCTRL_BLRDIS_MASK 0x1UL /**< Bit mask for MSC_BLRDIS */
|
||||
#define _MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
|
||||
#define MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLRDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
|
||||
#define MSC_BOOTLOADERCTRL_BLWDIS (0x1UL << 1) /**< Flash Bootloader Write/Erase Disable */
|
||||
#define _MSC_BOOTLOADERCTRL_BLWDIS_SHIFT 1 /**< Shift value for MSC_BLWDIS */
|
||||
#define _MSC_BOOTLOADERCTRL_BLWDIS_MASK 0x2UL /**< Bit mask for MSC_BLWDIS */
|
||||
#define _MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_BOOTLOADERCTRL */
|
||||
#define MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT (_MSC_BOOTLOADERCTRL_BLWDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_BOOTLOADERCTRL */
|
||||
|
||||
/* Bit fields for MSC AAPUNLOCKCMD */
|
||||
#define _MSC_AAPUNLOCKCMD_RESETVALUE 0x00000000UL /**< Default value for MSC_AAPUNLOCKCMD */
|
||||
#define _MSC_AAPUNLOCKCMD_MASK 0x00000001UL /**< Mask for MSC_AAPUNLOCKCMD */
|
||||
#define MSC_AAPUNLOCKCMD_UNLOCKAAP (0x1UL << 0) /**< Software Unlock AAP Command */
|
||||
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_SHIFT 0 /**< Shift value for MSC_UNLOCKAAP */
|
||||
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_MASK 0x1UL /**< Bit mask for MSC_UNLOCKAAP */
|
||||
#define _MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_AAPUNLOCKCMD */
|
||||
#define MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT (_MSC_AAPUNLOCKCMD_UNLOCKAAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_AAPUNLOCKCMD */
|
||||
|
||||
/* Bit fields for MSC CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_RESETVALUE 0x00000003UL /**< Default value for MSC_CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_MASK 0x00000003UL /**< Mask for MSC_CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_SHIFT 0 /**< Shift value for MSC_CACHELPLEVEL */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MASK 0x3UL /**< Bit mask for MSC_CACHELPLEVEL */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_BASE 0x00000000UL /**< Mode BASE for MSC_CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED 0x00000001UL /**< Mode ADVANCED for MSC_CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for MSC_CACHECONFIG0 */
|
||||
#define _MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY 0x00000003UL /**< Mode MINACTIVITY for MSC_CACHECONFIG0 */
|
||||
#define MSC_CACHECONFIG0_CACHELPLEVEL_BASE (_MSC_CACHECONFIG0_CACHELPLEVEL_BASE << 0) /**< Shifted mode BASE for MSC_CACHECONFIG0 */
|
||||
#define MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED (_MSC_CACHECONFIG0_CACHELPLEVEL_ADVANCED << 0) /**< Shifted mode ADVANCED for MSC_CACHECONFIG0 */
|
||||
#define MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT (_MSC_CACHECONFIG0_CACHELPLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHECONFIG0 */
|
||||
#define MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY (_MSC_CACHECONFIG0_CACHELPLEVEL_MINACTIVITY << 0) /**< Shifted mode MINACTIVITY for MSC_CACHECONFIG0 */
|
||||
|
||||
/* Bit fields for MSC RAMCTRL */
|
||||
#define _MSC_RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_RAMCTRL */
|
||||
#define _MSC_RAMCTRL_MASK 0x00070606UL /**< Mask for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */
|
||||
#define _MSC_RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for MSC_RAMWSEN */
|
||||
#define _MSC_RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for MSC_RAMWSEN */
|
||||
#define _MSC_RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAMWSEN_DEFAULT (_MSC_RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prefetch Enable */
|
||||
#define _MSC_RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for MSC_RAMPREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for MSC_RAMPREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM1WSEN (0x1UL << 9) /**< RAM1 WAIT STATE Enable */
|
||||
#define _MSC_RAMCTRL_RAM1WSEN_SHIFT 9 /**< Shift value for MSC_RAM1WSEN */
|
||||
#define _MSC_RAMCTRL_RAM1WSEN_MASK 0x200UL /**< Bit mask for MSC_RAM1WSEN */
|
||||
#define _MSC_RAMCTRL_RAM1WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM1WSEN_DEFAULT (_MSC_RAMCTRL_RAM1WSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM1PREFETCHEN (0x1UL << 10) /**< RAM1 Prefetch Enable */
|
||||
#define _MSC_RAMCTRL_RAM1PREFETCHEN_SHIFT 10 /**< Shift value for MSC_RAM1PREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAM1PREFETCHEN_MASK 0x400UL /**< Bit mask for MSC_RAM1PREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM1PREFETCHEN_DEFAULT << 10) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2CACHEEN (0x1UL << 16) /**< RAM2 CACHE Enable */
|
||||
#define _MSC_RAMCTRL_RAM2CACHEEN_SHIFT 16 /**< Shift value for MSC_RAM2CACHEEN */
|
||||
#define _MSC_RAMCTRL_RAM2CACHEEN_MASK 0x10000UL /**< Bit mask for MSC_RAM2CACHEEN */
|
||||
#define _MSC_RAMCTRL_RAM2CACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2CACHEEN_DEFAULT (_MSC_RAMCTRL_RAM2CACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2WSEN (0x1UL << 17) /**< RAM2 WAIT STATE Enable */
|
||||
#define _MSC_RAMCTRL_RAM2WSEN_SHIFT 17 /**< Shift value for MSC_RAM2WSEN */
|
||||
#define _MSC_RAMCTRL_RAM2WSEN_MASK 0x20000UL /**< Bit mask for MSC_RAM2WSEN */
|
||||
#define _MSC_RAMCTRL_RAM2WSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2WSEN_DEFAULT (_MSC_RAMCTRL_RAM2WSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2PREFETCHEN (0x1UL << 18) /**< RAM2 Prefetch Enable */
|
||||
#define _MSC_RAMCTRL_RAM2PREFETCHEN_SHIFT 18 /**< Shift value for MSC_RAM2PREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAM2PREFETCHEN_MASK 0x40000UL /**< Bit mask for MSC_RAM2PREFETCHEN */
|
||||
#define _MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAMCTRL */
|
||||
#define MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT (_MSC_RAMCTRL_RAM2PREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for MSC_RAMCTRL */
|
||||
|
||||
/* Bit fields for MSC ECCCTRL */
|
||||
#define _MSC_ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_ECCCTRL */
|
||||
#define _MSC_ECCCTRL_MASK 0x0000000FUL /**< Mask for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */
|
||||
#define _MSC_ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for MSC_RAMECCEWEN */
|
||||
#define _MSC_ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for MSC_RAMECCEWEN */
|
||||
#define _MSC_ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAMECCEWEN_DEFAULT (_MSC_ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */
|
||||
#define _MSC_ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for MSC_RAMECCCHKEN */
|
||||
#define _MSC_ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for MSC_RAMECCCHKEN */
|
||||
#define _MSC_ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAMECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAM1ECCEWEN (0x1UL << 2) /**< RAM1 ECC Write Enable */
|
||||
#define _MSC_ECCCTRL_RAM1ECCEWEN_SHIFT 2 /**< Shift value for MSC_RAM1ECCEWEN */
|
||||
#define _MSC_ECCCTRL_RAM1ECCEWEN_MASK 0x4UL /**< Bit mask for MSC_RAM1ECCEWEN */
|
||||
#define _MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCEWEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAM1ECCCHKEN (0x1UL << 3) /**< RAM1 ECC Check Enable */
|
||||
#define _MSC_ECCCTRL_RAM1ECCCHKEN_SHIFT 3 /**< Shift value for MSC_RAM1ECCCHKEN */
|
||||
#define _MSC_ECCCTRL_RAM1ECCCHKEN_MASK 0x8UL /**< Bit mask for MSC_RAM1ECCCHKEN */
|
||||
#define _MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ECCCTRL */
|
||||
#define MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT (_MSC_ECCCTRL_RAM1ECCCHKEN_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_ECCCTRL */
|
||||
|
||||
/* Bit fields for MSC RAMECCADDR */
|
||||
#define _MSC_RAMECCADDR_RESETVALUE 0x20000000UL /**< Default value for MSC_RAMECCADDR */
|
||||
#define _MSC_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAMECCADDR */
|
||||
#define _MSC_RAMECCADDR_RAMECCADDR_SHIFT 0 /**< Shift value for MSC_RAMECCADDR */
|
||||
#define _MSC_RAMECCADDR_RAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAMECCADDR */
|
||||
#define _MSC_RAMECCADDR_RAMECCADDR_DEFAULT 0x20000000UL /**< Mode DEFAULT for MSC_RAMECCADDR */
|
||||
#define MSC_RAMECCADDR_RAMECCADDR_DEFAULT (_MSC_RAMECCADDR_RAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAMECCADDR */
|
||||
|
||||
/* Bit fields for MSC RAM1ECCADDR */
|
||||
#define _MSC_RAM1ECCADDR_RESETVALUE 0x00000000UL /**< Default value for MSC_RAM1ECCADDR */
|
||||
#define _MSC_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for MSC_RAM1ECCADDR */
|
||||
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_SHIFT 0 /**< Shift value for MSC_RAM1ECCADDR */
|
||||
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_RAM1ECCADDR */
|
||||
#define _MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_RAM1ECCADDR */
|
||||
#define MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT (_MSC_RAM1ECCADDR_RAM1ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_RAM1ECCADDR */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_MSC */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h
vendored
Normal file
698
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_pcnt.h
vendored
Normal file
@ -0,0 +1,698 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_PCNT register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @defgroup EFM32GG11B_PCNT PCNT
|
||||
* @{
|
||||
* @brief EFM32GG11B_PCNT Register Declaration
|
||||
******************************************************************************/
|
||||
/** PCNT Register Declaration */
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Control Register */
|
||||
__IOM uint32_t CMD; /**< Command Register */
|
||||
__IM uint32_t STATUS; /**< Status Register */
|
||||
__IM uint32_t CNT; /**< Counter Value Register */
|
||||
__IM uint32_t TOP; /**< Top Value Register */
|
||||
__IOM uint32_t TOPB; /**< Top Value Buffer Register */
|
||||
__IM uint32_t IF; /**< Interrupt Flag Register */
|
||||
__IOM uint32_t IFS; /**< Interrupt Flag Set Register */
|
||||
__IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
|
||||
__IOM uint32_t IEN; /**< Interrupt Enable Register */
|
||||
uint32_t RESERVED0[1U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
|
||||
|
||||
uint32_t RESERVED1[4U]; /**< Reserved for future use **/
|
||||
__IOM uint32_t FREEZE; /**< Freeze Register */
|
||||
__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
|
||||
|
||||
uint32_t RESERVED2[7U]; /**< Reserved for future use **/
|
||||
__IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */
|
||||
__IOM uint32_t INPUT; /**< PCNT Input Register */
|
||||
__IOM uint32_t OVSCFG; /**< Oversampling Config Register */
|
||||
} PCNT_TypeDef; /** @} */
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup EFM32GG11B_PCNT
|
||||
* @{
|
||||
* @defgroup EFM32GG11B_PCNT_BitFields PCNT Bit Fields
|
||||
* @{
|
||||
******************************************************************************/
|
||||
|
||||
/* Bit fields for PCNT CTRL */
|
||||
#define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MASK 0xFFDBFFFFUL /**< Mask for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */
|
||||
#define _PCNT_CTRL_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */
|
||||
#define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_OVSQUAD1X 0x00000004UL /**< Mode OVSQUAD1X for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_OVSQUAD2X 0x00000005UL /**< Mode OVSQUAD2X for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_MODE_OVSQUAD4X 0x00000006UL /**< Mode OVSQUAD4X for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_OVSQUAD1X (_PCNT_CTRL_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_OVSQUAD2X (_PCNT_CTRL_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CTRL */
|
||||
#define PCNT_CTRL_MODE_OVSQUAD4X (_PCNT_CTRL_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CTRL */
|
||||
#define PCNT_CTRL_FILT (0x1UL << 3) /**< Enable Digital Pulse Width Filter */
|
||||
#define _PCNT_CTRL_FILT_SHIFT 3 /**< Shift value for PCNT_FILT */
|
||||
#define _PCNT_CTRL_FILT_MASK 0x8UL /**< Bit mask for PCNT_FILT */
|
||||
#define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_RSTEN (0x1UL << 4) /**< Enable PCNT Clock Domain Reset */
|
||||
#define _PCNT_CTRL_RSTEN_SHIFT 4 /**< Shift value for PCNT_RSTEN */
|
||||
#define _PCNT_CTRL_RSTEN_MASK 0x10UL /**< Bit mask for PCNT_RSTEN */
|
||||
#define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTRSTEN (0x1UL << 5) /**< Enable CNT Reset */
|
||||
#define _PCNT_CTRL_CNTRSTEN_SHIFT 5 /**< Shift value for PCNT_CNTRSTEN */
|
||||
#define _PCNT_CTRL_CNTRSTEN_MASK 0x20UL /**< Bit mask for PCNT_CNTRSTEN */
|
||||
#define _PCNT_CTRL_CNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTRSTEN_DEFAULT (_PCNT_CTRL_CNTRSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTRSTEN (0x1UL << 6) /**< Enable AUXCNT Reset */
|
||||
#define _PCNT_CTRL_AUXCNTRSTEN_SHIFT 6 /**< Shift value for PCNT_AUXCNTRSTEN */
|
||||
#define _PCNT_CTRL_AUXCNTRSTEN_MASK 0x40UL /**< Bit mask for PCNT_AUXCNTRSTEN */
|
||||
#define _PCNT_CTRL_AUXCNTRSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTRSTEN_DEFAULT (_PCNT_CTRL_AUXCNTRSTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_DEBUGHALT (0x1UL << 7) /**< Debug Mode Halt Enable */
|
||||
#define _PCNT_CTRL_DEBUGHALT_SHIFT 7 /**< Shift value for PCNT_DEBUGHALT */
|
||||
#define _PCNT_CTRL_DEBUGHALT_MASK 0x80UL /**< Bit mask for PCNT_DEBUGHALT */
|
||||
#define _PCNT_CTRL_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_DEBUGHALT_DEFAULT (_PCNT_CTRL_DEBUGHALT_DEFAULT << 7) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */
|
||||
#define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */
|
||||
#define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */
|
||||
#define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count Direction Determined By S1 */
|
||||
#define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */
|
||||
#define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */
|
||||
#define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */
|
||||
#define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */
|
||||
#define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_AUXCNTEV_SHIFT 12 /**< Shift value for PCNT_AUXCNTEV */
|
||||
#define _PCNT_CTRL_AUXCNTEV_MASK 0x3000UL /**< Bit mask for PCNT_AUXCNTEV */
|
||||
#define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 12) /**< Shifted mode NONE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 12) /**< Shifted mode UP for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 12) /**< Shifted mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 12) /**< Shifted mode BOTH for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR (0x1UL << 14) /**< Non-Quadrature Mode Counter Direction Control */
|
||||
#define _PCNT_CTRL_CNTDIR_SHIFT 14 /**< Shift value for PCNT_CNTDIR */
|
||||
#define _PCNT_CTRL_CNTDIR_MASK 0x4000UL /**< Bit mask for PCNT_CNTDIR */
|
||||
#define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 14) /**< Shifted mode UP for PCNT_CTRL */
|
||||
#define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE (0x1UL << 15) /**< Edge Select */
|
||||
#define _PCNT_CTRL_EDGE_SHIFT 15 /**< Shift value for PCNT_EDGE */
|
||||
#define _PCNT_CTRL_EDGE_MASK 0x8000UL /**< Bit mask for PCNT_EDGE */
|
||||
#define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 15) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 15) /**< Shifted mode POS for PCNT_CTRL */
|
||||
#define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 15) /**< Shifted mode NEG for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCMODE_SHIFT 16 /**< Shift value for PCNT_TCCMODE */
|
||||
#define _PCNT_CTRL_TCCMODE_MASK 0x30000UL /**< Bit mask for PCNT_TCCMODE */
|
||||
#define _PCNT_CTRL_TCCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCMODE_DISABLED 0x00000000UL /**< Mode DISABLED for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCMODE_LFA 0x00000001UL /**< Mode LFA for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCMODE_PRS 0x00000002UL /**< Mode PRS for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCMODE_DEFAULT (_PCNT_CTRL_TCCMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCMODE_DISABLED (_PCNT_CTRL_TCCMODE_DISABLED << 16) /**< Shifted mode DISABLED for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCMODE_LFA (_PCNT_CTRL_TCCMODE_LFA << 16) /**< Shifted mode LFA for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCMODE_PRS (_PCNT_CTRL_TCCMODE_PRS << 16) /**< Shifted mode PRS for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRESC_SHIFT 19 /**< Shift value for PCNT_TCCPRESC */
|
||||
#define _PCNT_CTRL_TCCPRESC_MASK 0x180000UL /**< Bit mask for PCNT_TCCPRESC */
|
||||
#define _PCNT_CTRL_TCCPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRESC_DIV1 0x00000000UL /**< Mode DIV1 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRESC_DIV2 0x00000001UL /**< Mode DIV2 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRESC_DIV4 0x00000002UL /**< Mode DIV4 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRESC_DIV8 0x00000003UL /**< Mode DIV8 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRESC_DEFAULT (_PCNT_CTRL_TCCPRESC_DEFAULT << 19) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRESC_DIV1 (_PCNT_CTRL_TCCPRESC_DIV1 << 19) /**< Shifted mode DIV1 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRESC_DIV2 (_PCNT_CTRL_TCCPRESC_DIV2 << 19) /**< Shifted mode DIV2 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRESC_DIV4 (_PCNT_CTRL_TCCPRESC_DIV4 << 19) /**< Shifted mode DIV4 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRESC_DIV8 (_PCNT_CTRL_TCCPRESC_DIV8 << 19) /**< Shifted mode DIV8 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCCOMP_SHIFT 22 /**< Shift value for PCNT_TCCCOMP */
|
||||
#define _PCNT_CTRL_TCCCOMP_MASK 0xC00000UL /**< Bit mask for PCNT_TCCCOMP */
|
||||
#define _PCNT_CTRL_TCCCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCCOMP_LTOE 0x00000000UL /**< Mode LTOE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCCOMP_GTOE 0x00000001UL /**< Mode GTOE for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCCOMP_RANGE 0x00000002UL /**< Mode RANGE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_DEFAULT (_PCNT_CTRL_TCCCOMP_DEFAULT << 22) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_LTOE (_PCNT_CTRL_TCCCOMP_LTOE << 22) /**< Shifted mode LTOE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_GTOE (_PCNT_CTRL_TCCCOMP_GTOE << 22) /**< Shifted mode GTOE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCCOMP_RANGE (_PCNT_CTRL_TCCCOMP_RANGE << 22) /**< Shifted mode RANGE for PCNT_CTRL */
|
||||
#define PCNT_CTRL_PRSGATEEN (0x1UL << 24) /**< PRS Gate Enable */
|
||||
#define _PCNT_CTRL_PRSGATEEN_SHIFT 24 /**< Shift value for PCNT_PRSGATEEN */
|
||||
#define _PCNT_CTRL_PRSGATEEN_MASK 0x1000000UL /**< Bit mask for PCNT_PRSGATEEN */
|
||||
#define _PCNT_CTRL_PRSGATEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_PRSGATEEN_DEFAULT (_PCNT_CTRL_PRSGATEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSPOL (0x1UL << 25) /**< TCC PRS Polarity Select */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_SHIFT 25 /**< Shift value for PCNT_TCCPRSPOL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_MASK 0x2000000UL /**< Bit mask for PCNT_TCCPRSPOL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_RISING 0x00000000UL /**< Mode RISING for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSPOL_FALLING 0x00000001UL /**< Mode FALLING for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSPOL_DEFAULT (_PCNT_CTRL_TCCPRSPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSPOL_RISING (_PCNT_CTRL_TCCPRSPOL_RISING << 25) /**< Shifted mode RISING for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSPOL_FALLING (_PCNT_CTRL_TCCPRSPOL_FALLING << 25) /**< Shifted mode FALLING for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_SHIFT 26 /**< Shift value for PCNT_TCCPRSSEL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_MASK 0x7C000000UL /**< Bit mask for PCNT_TCCPRSSEL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_CTRL */
|
||||
#define _PCNT_CTRL_TCCPRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_DEFAULT (_PCNT_CTRL_TCCPRSSEL_DEFAULT << 26) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH0 (_PCNT_CTRL_TCCPRSSEL_PRSCH0 << 26) /**< Shifted mode PRSCH0 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH1 (_PCNT_CTRL_TCCPRSSEL_PRSCH1 << 26) /**< Shifted mode PRSCH1 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH2 (_PCNT_CTRL_TCCPRSSEL_PRSCH2 << 26) /**< Shifted mode PRSCH2 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH3 (_PCNT_CTRL_TCCPRSSEL_PRSCH3 << 26) /**< Shifted mode PRSCH3 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH4 (_PCNT_CTRL_TCCPRSSEL_PRSCH4 << 26) /**< Shifted mode PRSCH4 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH5 (_PCNT_CTRL_TCCPRSSEL_PRSCH5 << 26) /**< Shifted mode PRSCH5 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH6 (_PCNT_CTRL_TCCPRSSEL_PRSCH6 << 26) /**< Shifted mode PRSCH6 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH7 (_PCNT_CTRL_TCCPRSSEL_PRSCH7 << 26) /**< Shifted mode PRSCH7 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH8 (_PCNT_CTRL_TCCPRSSEL_PRSCH8 << 26) /**< Shifted mode PRSCH8 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH9 (_PCNT_CTRL_TCCPRSSEL_PRSCH9 << 26) /**< Shifted mode PRSCH9 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH10 (_PCNT_CTRL_TCCPRSSEL_PRSCH10 << 26) /**< Shifted mode PRSCH10 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH11 (_PCNT_CTRL_TCCPRSSEL_PRSCH11 << 26) /**< Shifted mode PRSCH11 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH12 (_PCNT_CTRL_TCCPRSSEL_PRSCH12 << 26) /**< Shifted mode PRSCH12 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH13 (_PCNT_CTRL_TCCPRSSEL_PRSCH13 << 26) /**< Shifted mode PRSCH13 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH14 (_PCNT_CTRL_TCCPRSSEL_PRSCH14 << 26) /**< Shifted mode PRSCH14 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH15 (_PCNT_CTRL_TCCPRSSEL_PRSCH15 << 26) /**< Shifted mode PRSCH15 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH16 (_PCNT_CTRL_TCCPRSSEL_PRSCH16 << 26) /**< Shifted mode PRSCH16 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH17 (_PCNT_CTRL_TCCPRSSEL_PRSCH17 << 26) /**< Shifted mode PRSCH17 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH18 (_PCNT_CTRL_TCCPRSSEL_PRSCH18 << 26) /**< Shifted mode PRSCH18 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH19 (_PCNT_CTRL_TCCPRSSEL_PRSCH19 << 26) /**< Shifted mode PRSCH19 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH20 (_PCNT_CTRL_TCCPRSSEL_PRSCH20 << 26) /**< Shifted mode PRSCH20 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH21 (_PCNT_CTRL_TCCPRSSEL_PRSCH21 << 26) /**< Shifted mode PRSCH21 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH22 (_PCNT_CTRL_TCCPRSSEL_PRSCH22 << 26) /**< Shifted mode PRSCH22 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TCCPRSSEL_PRSCH23 (_PCNT_CTRL_TCCPRSSEL_PRSCH23 << 26) /**< Shifted mode PRSCH23 for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TOPBHFSEL (0x1UL << 31) /**< TOPB High Frequency Value Select */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_SHIFT 31 /**< Shift value for PCNT_TOPBHFSEL */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_MASK 0x80000000UL /**< Bit mask for PCNT_TOPBHFSEL */
|
||||
#define _PCNT_CTRL_TOPBHFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */
|
||||
#define PCNT_CTRL_TOPBHFSEL_DEFAULT (_PCNT_CTRL_TOPBHFSEL_DEFAULT << 31) /**< Shifted mode DEFAULT for PCNT_CTRL */
|
||||
|
||||
/* Bit fields for PCNT CMD */
|
||||
#define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */
|
||||
#define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */
|
||||
#define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */
|
||||
#define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */
|
||||
#define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */
|
||||
#define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */
|
||||
#define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */
|
||||
#define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */
|
||||
#define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */
|
||||
#define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */
|
||||
|
||||
/* Bit fields for PCNT STATUS */
|
||||
#define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */
|
||||
#define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */
|
||||
#define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */
|
||||
#define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */
|
||||
#define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */
|
||||
#define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */
|
||||
|
||||
/* Bit fields for PCNT CNT */
|
||||
#define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */
|
||||
#define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */
|
||||
#define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */
|
||||
#define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */
|
||||
|
||||
/* Bit fields for PCNT TOP */
|
||||
#define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */
|
||||
#define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */
|
||||
#define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */
|
||||
#define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */
|
||||
|
||||
/* Bit fields for PCNT TOPB */
|
||||
#define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */
|
||||
#define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */
|
||||
#define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */
|
||||
|
||||
/* Bit fields for PCNT IF */
|
||||
#define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */
|
||||
#define _PCNT_IF_MASK 0x0000003FUL /**< Mask for PCNT_IF */
|
||||
#define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */
|
||||
#define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */
|
||||
#define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */
|
||||
#define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */
|
||||
#define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
|
||||
#define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
|
||||
#define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_TCC (0x1UL << 4) /**< Triggered Compare Interrupt Read Flag */
|
||||
#define _PCNT_IF_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
|
||||
#define _PCNT_IF_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
|
||||
#define _PCNT_IF_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_TCC_DEFAULT (_PCNT_IF_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OQSTERR (0x1UL << 5) /**< Oversampling Quadrature State Error Interrupt */
|
||||
#define _PCNT_IF_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
|
||||
#define _PCNT_IF_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
|
||||
#define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */
|
||||
#define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IF */
|
||||
|
||||
/* Bit fields for PCNT IFS */
|
||||
#define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */
|
||||
#define _PCNT_IFS_MASK 0x0000003FUL /**< Mask for PCNT_IFS */
|
||||
#define PCNT_IFS_UF (0x1UL << 0) /**< Set UF Interrupt Flag */
|
||||
#define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OF (0x1UL << 1) /**< Set OF Interrupt Flag */
|
||||
#define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Set DIRCNG Interrupt Flag */
|
||||
#define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_AUXOF (0x1UL << 3) /**< Set AUXOF Interrupt Flag */
|
||||
#define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
|
||||
#define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
|
||||
#define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_TCC (0x1UL << 4) /**< Set TCC Interrupt Flag */
|
||||
#define _PCNT_IFS_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
|
||||
#define _PCNT_IFS_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
|
||||
#define _PCNT_IFS_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_TCC_DEFAULT (_PCNT_IFS_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OQSTERR (0x1UL << 5) /**< Set OQSTERR Interrupt Flag */
|
||||
#define _PCNT_IFS_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
|
||||
#define _PCNT_IFS_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
|
||||
#define _PCNT_IFS_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */
|
||||
#define PCNT_IFS_OQSTERR_DEFAULT (_PCNT_IFS_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFS */
|
||||
|
||||
/* Bit fields for PCNT IFC */
|
||||
#define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */
|
||||
#define _PCNT_IFC_MASK 0x0000003FUL /**< Mask for PCNT_IFC */
|
||||
#define PCNT_IFC_UF (0x1UL << 0) /**< Clear UF Interrupt Flag */
|
||||
#define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OF (0x1UL << 1) /**< Clear OF Interrupt Flag */
|
||||
#define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Clear DIRCNG Interrupt Flag */
|
||||
#define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_AUXOF (0x1UL << 3) /**< Clear AUXOF Interrupt Flag */
|
||||
#define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
|
||||
#define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
|
||||
#define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_TCC (0x1UL << 4) /**< Clear TCC Interrupt Flag */
|
||||
#define _PCNT_IFC_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
|
||||
#define _PCNT_IFC_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
|
||||
#define _PCNT_IFC_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_TCC_DEFAULT (_PCNT_IFC_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OQSTERR (0x1UL << 5) /**< Clear OQSTERR Interrupt Flag */
|
||||
#define _PCNT_IFC_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
|
||||
#define _PCNT_IFC_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
|
||||
#define _PCNT_IFC_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */
|
||||
#define PCNT_IFC_OQSTERR_DEFAULT (_PCNT_IFC_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IFC */
|
||||
|
||||
/* Bit fields for PCNT IEN */
|
||||
#define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */
|
||||
#define _PCNT_IEN_MASK 0x0000003FUL /**< Mask for PCNT_IEN */
|
||||
#define PCNT_IEN_UF (0x1UL << 0) /**< UF Interrupt Enable */
|
||||
#define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */
|
||||
#define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */
|
||||
#define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OF (0x1UL << 1) /**< OF Interrupt Enable */
|
||||
#define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */
|
||||
#define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */
|
||||
#define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_DIRCNG (0x1UL << 2) /**< DIRCNG Interrupt Enable */
|
||||
#define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */
|
||||
#define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */
|
||||
#define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_AUXOF (0x1UL << 3) /**< AUXOF Interrupt Enable */
|
||||
#define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */
|
||||
#define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */
|
||||
#define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_TCC (0x1UL << 4) /**< TCC Interrupt Enable */
|
||||
#define _PCNT_IEN_TCC_SHIFT 4 /**< Shift value for PCNT_TCC */
|
||||
#define _PCNT_IEN_TCC_MASK 0x10UL /**< Bit mask for PCNT_TCC */
|
||||
#define _PCNT_IEN_TCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_TCC_DEFAULT (_PCNT_IEN_TCC_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OQSTERR (0x1UL << 5) /**< OQSTERR Interrupt Enable */
|
||||
#define _PCNT_IEN_OQSTERR_SHIFT 5 /**< Shift value for PCNT_OQSTERR */
|
||||
#define _PCNT_IEN_OQSTERR_MASK 0x20UL /**< Bit mask for PCNT_OQSTERR */
|
||||
#define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */
|
||||
#define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_IEN */
|
||||
|
||||
/* Bit fields for PCNT ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_MASK 0x00000707UL /**< Mask for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_SHIFT 0 /**< Shift value for PCNT_S0INLOC */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_MASK 0x7UL /**< Bit mask for PCNT_S0INLOC */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S0INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC0 (_PCNT_ROUTELOC0_S0INLOC_LOC0 << 0) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_DEFAULT (_PCNT_ROUTELOC0_S0INLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC1 (_PCNT_ROUTELOC0_S0INLOC_LOC1 << 0) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC2 (_PCNT_ROUTELOC0_S0INLOC_LOC2 << 0) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC3 (_PCNT_ROUTELOC0_S0INLOC_LOC3 << 0) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC4 (_PCNT_ROUTELOC0_S0INLOC_LOC4 << 0) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC5 (_PCNT_ROUTELOC0_S0INLOC_LOC5 << 0) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC6 (_PCNT_ROUTELOC0_S0INLOC_LOC6 << 0) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S0INLOC_LOC7 (_PCNT_ROUTELOC0_S0INLOC_LOC7 << 0) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_SHIFT 8 /**< Shift value for PCNT_S1INLOC */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_MASK 0x700UL /**< Bit mask for PCNT_S1INLOC */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC4 0x00000004UL /**< Mode LOC4 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC5 0x00000005UL /**< Mode LOC5 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC6 0x00000006UL /**< Mode LOC6 for PCNT_ROUTELOC0 */
|
||||
#define _PCNT_ROUTELOC0_S1INLOC_LOC7 0x00000007UL /**< Mode LOC7 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC0 (_PCNT_ROUTELOC0_S1INLOC_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_DEFAULT (_PCNT_ROUTELOC0_S1INLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC1 (_PCNT_ROUTELOC0_S1INLOC_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC2 (_PCNT_ROUTELOC0_S1INLOC_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC3 (_PCNT_ROUTELOC0_S1INLOC_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC4 (_PCNT_ROUTELOC0_S1INLOC_LOC4 << 8) /**< Shifted mode LOC4 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC5 (_PCNT_ROUTELOC0_S1INLOC_LOC5 << 8) /**< Shifted mode LOC5 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC6 (_PCNT_ROUTELOC0_S1INLOC_LOC6 << 8) /**< Shifted mode LOC6 for PCNT_ROUTELOC0 */
|
||||
#define PCNT_ROUTELOC0_S1INLOC_LOC7 (_PCNT_ROUTELOC0_S1INLOC_LOC7 << 8) /**< Shifted mode LOC7 for PCNT_ROUTELOC0 */
|
||||
|
||||
/* Bit fields for PCNT FREEZE */
|
||||
#define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
|
||||
#define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */
|
||||
#define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */
|
||||
#define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */
|
||||
|
||||
/* Bit fields for PCNT SYNCBUSY */
|
||||
#define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */
|
||||
#define _PCNT_SYNCBUSY_MASK 0x0000000FUL /**< Mask for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
|
||||
#define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */
|
||||
#define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */
|
||||
#define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */
|
||||
#define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */
|
||||
#define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */
|
||||
#define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */
|
||||
#define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */
|
||||
#define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */
|
||||
#define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_OVSCFG (0x1UL << 3) /**< OVSCFG Register Busy */
|
||||
#define _PCNT_SYNCBUSY_OVSCFG_SHIFT 3 /**< Shift value for PCNT_OVSCFG */
|
||||
#define _PCNT_SYNCBUSY_OVSCFG_MASK 0x8UL /**< Bit mask for PCNT_OVSCFG */
|
||||
#define _PCNT_SYNCBUSY_OVSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */
|
||||
#define PCNT_SYNCBUSY_OVSCFG_DEFAULT (_PCNT_SYNCBUSY_OVSCFG_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */
|
||||
|
||||
/* Bit fields for PCNT AUXCNT */
|
||||
#define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */
|
||||
#define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */
|
||||
#define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */
|
||||
#define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */
|
||||
#define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */
|
||||
#define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */
|
||||
|
||||
/* Bit fields for PCNT INPUT */
|
||||
#define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_MASK 0x00000FFFUL /**< Mask for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */
|
||||
#define _PCNT_INPUT_S0PRSSEL_MASK 0x1FUL /**< Bit mask for PCNT_S0PRSSEL */
|
||||
#define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S0PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH12 (_PCNT_INPUT_S0PRSSEL_PRSCH12 << 0) /**< Shifted mode PRSCH12 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH13 (_PCNT_INPUT_S0PRSSEL_PRSCH13 << 0) /**< Shifted mode PRSCH13 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH14 (_PCNT_INPUT_S0PRSSEL_PRSCH14 << 0) /**< Shifted mode PRSCH14 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH15 (_PCNT_INPUT_S0PRSSEL_PRSCH15 << 0) /**< Shifted mode PRSCH15 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH16 (_PCNT_INPUT_S0PRSSEL_PRSCH16 << 0) /**< Shifted mode PRSCH16 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH17 (_PCNT_INPUT_S0PRSSEL_PRSCH17 << 0) /**< Shifted mode PRSCH17 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH18 (_PCNT_INPUT_S0PRSSEL_PRSCH18 << 0) /**< Shifted mode PRSCH18 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH19 (_PCNT_INPUT_S0PRSSEL_PRSCH19 << 0) /**< Shifted mode PRSCH19 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH20 (_PCNT_INPUT_S0PRSSEL_PRSCH20 << 0) /**< Shifted mode PRSCH20 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH21 (_PCNT_INPUT_S0PRSSEL_PRSCH21 << 0) /**< Shifted mode PRSCH21 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH22 (_PCNT_INPUT_S0PRSSEL_PRSCH22 << 0) /**< Shifted mode PRSCH22 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSSEL_PRSCH23 (_PCNT_INPUT_S0PRSSEL_PRSCH23 << 0) /**< Shifted mode PRSCH23 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSEN (0x1UL << 5) /**< S0IN PRS Enable */
|
||||
#define _PCNT_INPUT_S0PRSEN_SHIFT 5 /**< Shift value for PCNT_S0PRSEN */
|
||||
#define _PCNT_INPUT_S0PRSEN_MASK 0x20UL /**< Bit mask for PCNT_S0PRSEN */
|
||||
#define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */
|
||||
#define _PCNT_INPUT_S1PRSSEL_MASK 0x7C0UL /**< Bit mask for PCNT_S1PRSSEL */
|
||||
#define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH12 0x0000000CUL /**< Mode PRSCH12 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH13 0x0000000DUL /**< Mode PRSCH13 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH14 0x0000000EUL /**< Mode PRSCH14 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH15 0x0000000FUL /**< Mode PRSCH15 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH16 0x00000010UL /**< Mode PRSCH16 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH17 0x00000011UL /**< Mode PRSCH17 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH18 0x00000012UL /**< Mode PRSCH18 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH19 0x00000013UL /**< Mode PRSCH19 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH20 0x00000014UL /**< Mode PRSCH20 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH21 0x00000015UL /**< Mode PRSCH21 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH22 0x00000016UL /**< Mode PRSCH22 for PCNT_INPUT */
|
||||
#define _PCNT_INPUT_S1PRSSEL_PRSCH23 0x00000017UL /**< Mode PRSCH23 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH12 (_PCNT_INPUT_S1PRSSEL_PRSCH12 << 6) /**< Shifted mode PRSCH12 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH13 (_PCNT_INPUT_S1PRSSEL_PRSCH13 << 6) /**< Shifted mode PRSCH13 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH14 (_PCNT_INPUT_S1PRSSEL_PRSCH14 << 6) /**< Shifted mode PRSCH14 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH15 (_PCNT_INPUT_S1PRSSEL_PRSCH15 << 6) /**< Shifted mode PRSCH15 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH16 (_PCNT_INPUT_S1PRSSEL_PRSCH16 << 6) /**< Shifted mode PRSCH16 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH17 (_PCNT_INPUT_S1PRSSEL_PRSCH17 << 6) /**< Shifted mode PRSCH17 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH18 (_PCNT_INPUT_S1PRSSEL_PRSCH18 << 6) /**< Shifted mode PRSCH18 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH19 (_PCNT_INPUT_S1PRSSEL_PRSCH19 << 6) /**< Shifted mode PRSCH19 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH20 (_PCNT_INPUT_S1PRSSEL_PRSCH20 << 6) /**< Shifted mode PRSCH20 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH21 (_PCNT_INPUT_S1PRSSEL_PRSCH21 << 6) /**< Shifted mode PRSCH21 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH22 (_PCNT_INPUT_S1PRSSEL_PRSCH22 << 6) /**< Shifted mode PRSCH22 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSSEL_PRSCH23 (_PCNT_INPUT_S1PRSSEL_PRSCH23 << 6) /**< Shifted mode PRSCH23 for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSEN (0x1UL << 11) /**< S1IN PRS Enable */
|
||||
#define _PCNT_INPUT_S1PRSEN_SHIFT 11 /**< Shift value for PCNT_S1PRSEN */
|
||||
#define _PCNT_INPUT_S1PRSEN_MASK 0x800UL /**< Bit mask for PCNT_S1PRSEN */
|
||||
#define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */
|
||||
#define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_INPUT */
|
||||
|
||||
/* Bit fields for PCNT OVSCFG */
|
||||
#define _PCNT_OVSCFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCFG */
|
||||
#define _PCNT_OVSCFG_MASK 0x000010FFUL /**< Mask for PCNT_OVSCFG */
|
||||
#define _PCNT_OVSCFG_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */
|
||||
#define _PCNT_OVSCFG_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */
|
||||
#define _PCNT_OVSCFG_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
|
||||
#define PCNT_OVSCFG_FILTLEN_DEFAULT (_PCNT_OVSCFG_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
|
||||
#define PCNT_OVSCFG_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */
|
||||
#define _PCNT_OVSCFG_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */
|
||||
#define _PCNT_OVSCFG_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */
|
||||
#define _PCNT_OVSCFG_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCFG */
|
||||
#define PCNT_OVSCFG_FLUTTERRM_DEFAULT (_PCNT_OVSCFG_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCFG */
|
||||
|
||||
/** @} */
|
||||
/** @} End of group EFM32GG11B_PCNT */
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
1579
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h
vendored
Normal file
1579
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
58
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h
vendored
Normal file
58
cpu/efm32/families/efm32gg11b/include/vendor/efm32gg11b_prs_ch.h
vendored
Normal file
@ -0,0 +1,58 @@
|
||||
/***************************************************************************//**
|
||||
* @file
|
||||
* @brief EFM32GG11B_PRS_CH register and bit field definitions
|
||||
*******************************************************************************
|
||||
* # License
|
||||
* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
|
||||
*******************************************************************************
|
||||
*
|
||||
* SPDX-License-Identifier: Zlib
|
||||
*
|
||||
* The licensor of this software is Silicon Laboratories Inc.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied
|
||||
* warranty. In no event will the authors be held liable for any damages
|
||||
* arising from the use of this software.
|
||||
*
|
||||
* Permission is granted to anyone to use this software for any purpose,
|
||||
* including commercial applications, and to alter it and redistribute it
|
||||
* freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software
|
||||
* in a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma system_include /* Treat file as system include file. */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* Treat file as system include file. */
|
||||
#endif
|
||||
|
||||
/***************************************************************************//**
|
||||
* @addtogroup Parts
|
||||
* @{
|
||||
******************************************************************************/
|
||||
/***************************************************************************//**
|
||||
* @brief PRS_CH PRS CH Register
|
||||
* @ingroup EFM32GG11B_PRS
|
||||
******************************************************************************/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /**< Channel Control Register */
|
||||
} PRS_CH_TypeDef;
|
||||
|
||||
/** @} End of group Parts */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user