mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
drivers: support for ST L3Gxxxx 3-axis gyroscope family
This commit is contained in:
Gunar Schorcht
parent
936696fd16
commit
1569299c92
@ -76,6 +76,10 @@ ifneq (,$(filter itg320x_%,$(USEMODULE)))
|
||||
USEMODULE += itg320x
|
||||
endif
|
||||
|
||||
ifneq (,$(filter l3gxxxx_%,$(USEMODULE)))
|
||||
USEMODULE += l3gxxxx
|
||||
endif
|
||||
|
||||
ifneq (,$(filter lis2dh12%,$(USEMODULE)))
|
||||
USEMODULE += lis2dh12
|
||||
endif
|
||||
|
||||
1999
drivers/include/l3gxxxx.h
Normal file
1999
drivers/include/l3gxxxx.h
Normal file
File diff suppressed because it is too large
Load Diff
1
drivers/l3gxxxx/Makefile
Normal file
1
drivers/l3gxxxx/Makefile
Normal file
@ -0,0 +1 @@
|
||||
include $(RIOTMAKE)/driver_with_saul.mk
|
||||
25
drivers/l3gxxxx/Makefile.dep
Normal file
25
drivers/l3gxxxx/Makefile.dep
Normal file
@ -0,0 +1,25 @@
|
||||
ifeq (,$(filter l3gd20% l3g4200d_ng %3g4250d,$(USEMODULE)))
|
||||
# pull in L3GD20H variant by default if no interface is defined
|
||||
USEMODULE += l3gd20h
|
||||
endif
|
||||
|
||||
ifeq (,$(filter l3gxxxx_spi,$(USEMODULE)))
|
||||
# pull in I2C variant by default if no interface is defined
|
||||
USEMODULE += l3gxxxx_i2c
|
||||
endif
|
||||
|
||||
ifneq (,$(filter l3gxxxx_spi,$(USEMODULE)))
|
||||
FEATURES_REQUIRED += periph_spi
|
||||
endif
|
||||
|
||||
ifneq (,$(filter l3gxxxx_i2c,$(USEMODULE)))
|
||||
FEATURES_REQUIRED += periph_i2c
|
||||
endif
|
||||
|
||||
ifneq (,$(filter l3gxxxx_irq_%,$(USEMODULE)))
|
||||
USEMODULE += l3gxxxx_irq
|
||||
endif
|
||||
|
||||
ifneq (,$(filter l3gxxxx_irq,$(USEMODULE)))
|
||||
FEATURES_REQUIRED += periph_gpio_irq
|
||||
endif
|
||||
19
drivers/l3gxxxx/Makefile.include
Normal file
19
drivers/l3gxxxx/Makefile.include
Normal file
@ -0,0 +1,19 @@
|
||||
# include variants of L3Gxxxx driver as pseudo modules
|
||||
PSEUDOMODULES += a3g4250d
|
||||
PSEUDOMODULES += i3g4250d
|
||||
PSEUDOMODULES += l3g4200d_ng
|
||||
PSEUDOMODULES += l3gd20
|
||||
PSEUDOMODULES += l3gd20h
|
||||
|
||||
PSEUDOMODULES += l3gxxxx_i2c
|
||||
PSEUDOMODULES += l3gxxxx_spi
|
||||
PSEUDOMODULES += l3gxxxx_low_odr
|
||||
PSEUDOMODULES += l3gxxxx_fifo
|
||||
PSEUDOMODULES += l3gxxxx_irq
|
||||
PSEUDOMODULES += l3gxxxx_irq_data
|
||||
PSEUDOMODULES += l3gxxxx_irq_event
|
||||
PSEUDOMODULES += l3gxxxx_sleep
|
||||
PSEUDOMODULES += l3gxxxx_config
|
||||
|
||||
USEMODULE_INCLUDES_l3gxxxx := $(LAST_MAKEFILEDIR)/include
|
||||
USEMODULE_INCLUDES += $(USEMODULE_INCLUDES_l3gxxxx)
|
||||
385
drivers/l3gxxxx/include/l3gxxxx_params.h
Normal file
385
drivers/l3gxxxx/include/l3gxxxx_params.h
Normal file
@ -0,0 +1,385 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Gunar Schorcht
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup drivers_l3gxxxx
|
||||
* @brief Default configuration for ST L3Gxxxx 3-axis gyroscope sensor family
|
||||
* @author Gunar Schorcht <gunar@schorcht.net>
|
||||
* @file
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef L3GXXXX_PARAMS_H
|
||||
#define L3GXXXX_PARAMS_H
|
||||
|
||||
#include "board.h"
|
||||
#include "l3gxxxx.h"
|
||||
#include "saul_reg.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Default hardware configuration
|
||||
* @{
|
||||
*/
|
||||
#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
|
||||
|
||||
#ifndef L3GXXXX_I2C_DEV
|
||||
/** Default I2C device, if the I2C interface is used */
|
||||
#define L3GXXXX_I2C_DEV (I2C_DEV(0))
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_I2C_ADDR
|
||||
/** Default I2C address, if the I2C interface is used */
|
||||
#define L3GXXXX_I2C_ADDR (L3GXXXX_I2C_ADDR_2)
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_I2C_IF_PARAMS
|
||||
/** Default I2C interface parameter set */
|
||||
#define L3GXXXX_I2C_IF_PARAMS .if_params.type = L3GXXXX_I2C, \
|
||||
.if_params.i2c.dev = L3GXXXX_I2C_DEV, \
|
||||
.if_params.i2c.addr = L3GXXXX_I2C_ADDR,
|
||||
#endif
|
||||
|
||||
#endif /* MODULE_L3GXXXX_I2C || DOXYGEN */
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
|
||||
|
||||
#ifndef L3GXXXX_SPI_DEV
|
||||
/** Default SPI device, if the SPI interface is used */
|
||||
#define L3GXXXX_SPI_DEV SPI_DEV(0)
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_SPI_CLK
|
||||
/** Default SPI clock frequency, if the SPI interface is used */
|
||||
#define L3GXXXX_SPI_CLK (SPI_CLK_1MHZ)
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_SPI_CS
|
||||
/** Default SPI CS signal, if the SPI interface is used */
|
||||
#define L3GXXXX_SPI_CS (GPIO_PIN(0, 0))
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_SPI_IF_PARAMS
|
||||
/** Default SPI interface parameter set */
|
||||
#define L3GXXXX_SPI_IF_PARAMS .if_params.type = L3GXXXX_SPI, \
|
||||
.if_params.spi.dev = L3GXXXX_SPI_DEV, \
|
||||
.if_params.spi.clk = L3GXXXX_SPI_CLK, \
|
||||
.if_params.spi.cs = L3GXXXX_SPI_CS,
|
||||
#endif
|
||||
|
||||
#endif /* MODULE_L3GXXXX_SPI || DOXYGEN */
|
||||
|
||||
#ifndef L3GXXXX_INT1_PIN
|
||||
/** Default MCU pin for INT1 signal */
|
||||
#define L3GXXXX_INT1_PIN (GPIO_PIN(0, 1))
|
||||
#endif
|
||||
|
||||
#ifndef L3GXXXX_INT2_PIN
|
||||
/** Default MCU pin for INT2/DRDY signal */
|
||||
#define L3GXXXX_INT2_PIN (GPIO_PIN(0, 2))
|
||||
#endif
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Default sensor configuration
|
||||
* @{
|
||||
*/
|
||||
#if !DOXYGEN
|
||||
/* Mapping of Kconfig defines to the respective driver enumeration values */
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_ODR_100_12
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_12)
|
||||
#elif CONFIG_L3GXXXX_ODR_100_25
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_25)
|
||||
#elif CONFIG_L3GXXXX_ODR_200_12
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_12)
|
||||
#elif CONFIG_L3GXXXX_ODR_200_25
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_25)
|
||||
#elif CONFIG_L3GXXXX_ODR_200_50
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_50)
|
||||
#elif CONFIG_L3GXXXX_ODR_200_70
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_200_70)
|
||||
#elif CONFIG_L3GXXXX_ODR_400_20
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_20)
|
||||
#elif CONFIG_L3GXXXX_ODR_400_25
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_25)
|
||||
#elif CONFIG_L3GXXXX_ODR_400_50
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_50)
|
||||
#elif CONFIG_L3GXXXX_ODR_400_110
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_400_110)
|
||||
#elif CONFIG_L3GXXXX_ODR_800_30
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_30)
|
||||
#elif CONFIG_L3GXXXX_ODR_800_35
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_35)
|
||||
#elif CONFIG_L3GXXXX_ODR_800_50
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_50)
|
||||
#elif CONFIG_L3GXXXX_ODR_800_100
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_800_100)
|
||||
#elif CONFIG_L3GXXXX_ODR_12
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_12)
|
||||
#elif CONFIG_L3GXXXX_ODR_25
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_25)
|
||||
#elif CONFIG_L3GXXXX_ODR_50
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_50)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_SCALE_245_DPS
|
||||
#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_245_DPS)
|
||||
#elif CONFIG_L3GXXXX_SCALE_500_DPS
|
||||
#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_500_DPS)
|
||||
#elif CONFIG_L3GXXXX_SCALE_2000_DPS
|
||||
#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_2000_DPS)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_NO_FILTER
|
||||
#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_NO_FILTER)
|
||||
#elif CONFIG_L3GXXXX_HPF_ONLY
|
||||
#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_ONLY)
|
||||
#elif CONFIG_L3GXXXX_LPF2_ONLY
|
||||
#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_LPF2_ONLY)
|
||||
#elif CONFIG_L3GXXXX_HPF_AND_LPF2
|
||||
#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_AND_LPF2)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_HPF_NORMAL
|
||||
#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_NORMAL)
|
||||
#elif CONFIG_L3GXXXX_HPF_REFERENCE
|
||||
#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_REFERENCE)
|
||||
#elif CONFIG_L3GXXXX_HPF_AUTORESET
|
||||
#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_AUTORESET)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_FIFO_MODE_BYPASS
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS)
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_FIFO
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_FIFO)
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_STREAM
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_STREAM)
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_STREAM_TO_FIFO
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_STREAM_TO_FIFO)
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_BYPASS_TO_STREAM
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS_TO_STREAM)
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_DYNAMIC_STREAM
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_DYNAMIC_STREAM
|
||||
#elif CONFIG_L3GXXXX_FIFO_MODE_BYPASS_TO_FIFO
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_BYPASS_TO_FIFO)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_L3GXXXX_INT1_NO_FILTER
|
||||
#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_NO_FILTER)
|
||||
#elif CONFIG_L3GXXXX_INT1_HPF_ONLY
|
||||
#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_ONLY)
|
||||
#elif CONFIG_L3GXXXX_INT1_LPF2_ONLY
|
||||
#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_LPF2_ONLY)
|
||||
#elif CONFIG_L3GXXXX_INT1_HPF_AND_LPF2
|
||||
#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_AND_LPF2)
|
||||
#endif
|
||||
|
||||
#endif /* !DOXYGEN */
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_ODR
|
||||
/** Default ODR and cut-off frequency */
|
||||
#define CONFIG_L3GXXXX_ODR (L3GXXXX_ODR_100_25)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_SCALE
|
||||
/** Default full scale */
|
||||
#define CONFIG_L3GXXXX_SCALE (L3GXXXX_SCALE_245_DPS)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_FILTER_SEL
|
||||
/** Default filter selection used for output data */
|
||||
#define CONFIG_L3GXXXX_FILTER_SEL (L3GXXXX_HPF_AND_LPF2)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_HPF_MODE
|
||||
/** Default HPF mode used for output data */
|
||||
#define CONFIG_L3GXXXX_HPF_MODE (L3GXXXX_HPF_NORMAL)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_HPF_CUTOFF
|
||||
/** Default HPF cutoff frequency 8 Hz */
|
||||
#define CONFIG_L3GXXXX_HPF_CUTOFF (0)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_FIFO_MODE
|
||||
/** Default FIFO mode if FIO is used */
|
||||
#define CONFIG_L3GXXXX_FIFO_MODE (L3GXXXX_FIFO)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_FIFO_WATERMARK
|
||||
/** Default FIFO watermark level (threshold) value if FIO is used */
|
||||
#define CONFIG_L3GXXXX_FIFO_WATERMARK (23)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_X_THRESH
|
||||
/** Default INT1 threshold for X axis events (~30 dps at fulls scale of ±245 dps) */
|
||||
#define CONFIG_L3GXXXX_INT1_X_THRESH (4012)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_X_GT_THRESH
|
||||
/** Default INT1 interrupt enable for |X| > X threshold (X high event) */
|
||||
#define CONFIG_L3GXXXX_INT1_X_GT_THRESH (true)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_X_LT_THRESH
|
||||
/** Default INT1 interrupt enable for |X| < X threshold (X low event) */
|
||||
#define CONFIG_L3GXXXX_INT1_X_LT_THRESH (false)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Y_THRESH
|
||||
/** Default INT1 threshold for Y axis events (~30 dps at fulls scale of ±245 dps) */
|
||||
#define CONFIG_L3GXXXX_INT1_Y_THRESH (4012)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Y_GT_THRESH
|
||||
/** Default INT1 interrupt enable for |Y| < Y threshold (Y low event) */
|
||||
#define CONFIG_L3GXXXX_INT1_Y_GT_THRESH (true)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Y_LT_THRESH
|
||||
/** Default INT1 interrupt enable for |Y| > Y threshold (Y high event) */
|
||||
#define CONFIG_L3GXXXX_INT1_Y_LT_THRESH (false)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Z_THRESH
|
||||
/** Default INT1 threshold for Z axis events (~30 dps at fulls scale of ±245 dps) */
|
||||
#define CONFIG_L3GXXXX_INT1_Z_THRESH (4012)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Z_GT_THRESH
|
||||
/** Default INT1 interrupt enable for |Z| < Z threshold (Z low event) */
|
||||
#define CONFIG_L3GXXXX_INT1_Z_GT_THRESH (true)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_Z_LT_THRESH
|
||||
/** Default INT1 interrupt enable for |Z| > Z threshold (Z high event) */
|
||||
#define CONFIG_L3GXXXX_INT1_Z_LT_THRESH (false)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_FILTER
|
||||
/** Default filter selection used for INT1 interrupt */
|
||||
#define CONFIG_L3GXXXX_INT1_FILTER (L3GXXXX_HPF_AND_LPF2)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_AND
|
||||
/** Default event interrupt combination is OR */
|
||||
#define CONFIG_L3GXXXX_INT1_AND (false)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_L3GXXXX_INT1_LATCH
|
||||
/** Default INT1 event interrupt latch enabled */
|
||||
#define CONFIG_L3GXXXX_INT1_LATCH (true)
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_IRQ_EVENT) || DOXYGEN
|
||||
/** Default INT1 parameter set */
|
||||
#define L3GXXXX_INT1_PARAMS .int1_pin = L3GXXXX_INT1_PIN, \
|
||||
.int1_cfg.x_high_enabled = CONFIG_L3GXXXX_INT1_X_GT_THRESH, \
|
||||
.int1_cfg.y_high_enabled = CONFIG_L3GXXXX_INT1_Y_GT_THRESH, \
|
||||
.int1_cfg.z_high_enabled = CONFIG_L3GXXXX_INT1_Z_GT_THRESH, \
|
||||
.int1_cfg.x_low_enabled = CONFIG_L3GXXXX_INT1_X_LT_THRESH, \
|
||||
.int1_cfg.y_low_enabled = CONFIG_L3GXXXX_INT1_Y_LT_THRESH, \
|
||||
.int1_cfg.z_low_enabled = CONFIG_L3GXXXX_INT1_Z_LT_THRESH, \
|
||||
.int1_cfg.x_threshold = CONFIG_L3GXXXX_INT1_X_THRESH, \
|
||||
.int1_cfg.y_threshold = CONFIG_L3GXXXX_INT1_Y_THRESH, \
|
||||
.int1_cfg.z_threshold = CONFIG_L3GXXXX_INT1_Z_THRESH, \
|
||||
.int1_cfg.filter = CONFIG_L3GXXXX_INT1_FILTER, \
|
||||
.int1_cfg.and_or = CONFIG_L3GXXXX_INT1_AND, \
|
||||
.int1_cfg.latch = CONFIG_L3GXXXX_INT1_LATCH,
|
||||
#else
|
||||
#define L3GXXXX_INT1_PARAMS
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_IRQ_DATA) || DOXYGEN
|
||||
/** Default INT2 parameter set */
|
||||
#define L3GXXXX_INT2_PARAMS .int2_pin = L3GXXXX_INT2_PIN,
|
||||
#else
|
||||
#define L3GXXXX_INT2_PARAMS
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_FIFO) || DOXYGEN
|
||||
/** Default FIFO parameter set */
|
||||
#define L3GXXXX_FIFO_PARAMS .fifo_mode = CONFIG_L3GXXXX_FIFO_MODE, \
|
||||
.fifo_watermark = CONFIG_L3GXXXX_FIFO_WATERMARK,
|
||||
#else
|
||||
#define L3GXXXX_FIFO_PARAMS
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
|
||||
|
||||
#ifndef L3GXXXX_I2C_PARAMS
|
||||
/** Default I2C device parameter set */
|
||||
#define L3GXXXX_I2C_PARAMS { \
|
||||
L3GXXXX_I2C_IF_PARAMS \
|
||||
.odr = CONFIG_L3GXXXX_ODR, \
|
||||
.scale = CONFIG_L3GXXXX_SCALE, \
|
||||
.filter_sel = CONFIG_L3GXXXX_FILTER_SEL, \
|
||||
.hpf_mode = CONFIG_L3GXXXX_HPF_MODE, \
|
||||
.hpf_cutoff = CONFIG_L3GXXXX_HPF_CUTOFF, \
|
||||
L3GXXXX_FIFO_PARAMS \
|
||||
L3GXXXX_INT1_PARAMS \
|
||||
L3GXXXX_INT2_PARAMS \
|
||||
}
|
||||
#endif
|
||||
#endif /* MODULE_L3GXXXX_I2C || DOXYGEN */
|
||||
|
||||
#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
|
||||
#ifndef L3GXXXX_SPI_PARAMS
|
||||
/** Default SPI device parameter set */
|
||||
#define L3GXXXX_SPI_PARAMS { \
|
||||
L3GXXXX_SPI_IF_PARAMS \
|
||||
.odr = CONFIG_L3GXXXX_ODR, \
|
||||
.scale = CONFIG_L3GXXXX_SCALE, \
|
||||
.filter_sel = CONFIG_L3GXXXX_FILTER_SEL, \
|
||||
.hpf_mode = CONFIG_L3GXXXX_HPF_MODE, \
|
||||
.hpf_cutoff = CONFIG_L3GXXXX_HPF_CUTOFF, \
|
||||
L3GXXXX_FIFO_PARAMS \
|
||||
L3GXXXX_INT1_PARAMS \
|
||||
L3GXXXX_INT2_PARAMS \
|
||||
}
|
||||
#endif
|
||||
#endif /* MODULE_L3GXXXX_SPI || DOXYGEN */
|
||||
|
||||
#ifndef L3GXXXX_SAUL_INFO
|
||||
/** Default SAUL device info */
|
||||
#define L3GXXXX_SAUL_INFO { .name = "l3gxxxx" }
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
/**
|
||||
* @brief Allocate some memory to store the actual configuration
|
||||
*/
|
||||
static const l3gxxxx_params_t l3gxxxx_params[] =
|
||||
{
|
||||
#if IS_USED(MODULE_L3GXXXX_I2C) || DOXYGEN
|
||||
L3GXXXX_I2C_PARAMS,
|
||||
#endif
|
||||
#if IS_USED(MODULE_L3GXXXX_SPI) || DOXYGEN
|
||||
L3GXXXX_SPI_PARAMS,
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Additional meta information to keep in the SAUL registry
|
||||
*/
|
||||
static const saul_reg_info_t l3gxxxx_saul_info[] =
|
||||
{
|
||||
L3GXXXX_SAUL_INFO
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* L3GXXXX_PARAMS_H */
|
||||
/** @} */
|
||||
196
drivers/l3gxxxx/include/l3gxxxx_regs.h
Normal file
196
drivers/l3gxxxx/include/l3gxxxx_regs.h
Normal file
@ -0,0 +1,196 @@
|
||||
/*
|
||||
* Copyright (C) 2018 Gunar Schorcht
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup drivers_l3gxxxx
|
||||
* @brief Register definitions for ST L3Gxxxx 3-axis gyroscope sensor family
|
||||
* @author Gunar Schorcht <gunar@schorcht.net>
|
||||
* @file
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef L3GXXXX_REGS_H
|
||||
#define L3GXXXX_REGS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @name Register addresses
|
||||
* @{
|
||||
*/
|
||||
#define L3GXXXX_REG_WHO_AM_I (0x0f) /**< Register address WHO_AM_I */
|
||||
#define L3GXXXX_REG_CTRL1 (0x20) /**< Register address CTRL1 */
|
||||
#define L3GXXXX_REG_CTRL2 (0x21) /**< Register address CTRL2 */
|
||||
#define L3GXXXX_REG_CTRL3 (0x22) /**< Register address CTRL3 */
|
||||
#define L3GXXXX_REG_CTRL4 (0x23) /**< Register address CTRL4 */
|
||||
#define L3GXXXX_REG_CTRL5 (0x24) /**< Register address CTRL5 */
|
||||
#define L3GXXXX_REG_REFERENCE (0x25) /**< Register address REFERENCE */
|
||||
#define L3GXXXX_REG_OUT_TEMP (0x26) /**< Register address OUT_TEMP */
|
||||
#define L3GXXXX_REG_STATUS (0x27) /**< Register address STATUS */
|
||||
#define L3GXXXX_REG_OUT_X_L (0x28) /**< Register address OUT_X_L */
|
||||
#define L3GXXXX_REG_OUT_X_H (0x29) /**< Register address OUT_X_H */
|
||||
#define L3GXXXX_REG_OUT_Y_L (0x2a) /**< Register address OUT_Y_L */
|
||||
#define L3GXXXX_REG_OUT_Y_H (0x2b) /**< Register address OUT_Y_H */
|
||||
#define L3GXXXX_REG_OUT_Z_L (0x2c) /**< Register address OUT_Z_L */
|
||||
#define L3GXXXX_REG_OUT_Z_H (0x2d) /**< Register address OUT_Z_H */
|
||||
#define L3GXXXX_REG_FIFO_CTRL (0x2e) /**< Register address FIFO_CTRL */
|
||||
#define L3GXXXX_REG_FIFO_SRC (0x2f) /**< Register address FIFO_SRC */
|
||||
#define L3GXXXX_REG_IG_CFG (0x30) /**< Register address IG_CFG */
|
||||
#define L3GXXXX_REG_IG_SRC (0x31) /**< Register address IG_SRC */
|
||||
#define L3GXXXX_REG_IG_THS_XH (0x32) /**< Register address IG_THS_XH */
|
||||
#define L3GXXXX_REG_IG_THS_XL (0x33) /**< Register address IG_THS_XL */
|
||||
#define L3GXXXX_REG_IG_THS_YH (0x34) /**< Register address IG_THS_YH */
|
||||
#define L3GXXXX_REG_IG_THS_YL (0x35) /**< Register address IG_THS_YL */
|
||||
#define L3GXXXX_REG_IG_THS_ZH (0x36) /**< Register address IG_THS_ZH */
|
||||
#define L3GXXXX_REG_IG_THS_ZL (0x37) /**< Register address IG_THS_ZL */
|
||||
#define L3GXXXX_REG_IG_DURATION (0x38) /**< Register address IG_DURATION */
|
||||
#define L3GXXXX_REG_LOW_ODR (0x39) /**< Register address LOW_ODR */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Register structure definitions
|
||||
* @{
|
||||
*/
|
||||
#define L3GXXXX_ZYXOR (0x80) /**< L3GXXXX_REG_STATUS<7> */
|
||||
#define L3GXXXX_ZOR (0x40) /**< L3GXXXX_REG_STATUS<6> */
|
||||
#define L3GXXXX_YOR (0x20) /**< L3GXXXX_REG_STATUS<5> */
|
||||
#define L3GXXXX_XOR (0x10) /**< L3GXXXX_REG_STATUS<4> */
|
||||
#define L3GXXXX_ZYXDA (0x08) /**< L3GXXXX_REG_STATUS<3> */
|
||||
#define L3GXXXX_ZDA (0x04) /**< L3GXXXX_REG_STATUS<2> */
|
||||
#define L3GXXXX_YDA (0x02) /**< L3GXXXX_REG_STATUS<1> */
|
||||
#define L3GXXXX_XDA (0x01) /**< L3GXXXX_REG_STATUS<0> */
|
||||
|
||||
#define L3GXXXX_ANY_DATA_READY (0x07) /**< L3GXXXX_REG_STATUS<2:0> */
|
||||
#define L3GXXXX_ANY_DATA_READY_S (0) /**< L3GXXXX_REG_STATUS<2:0> */
|
||||
|
||||
#define L3GXXXX_ODR (0xc0) /**< L3GXXXX_REG_CTRL1<7:6> */
|
||||
#define L3GXXXX_BW (0x30) /**< L3GXXXX_REG_CTRL1<5:4> */
|
||||
#define L3GXXXX_ODR_BW (0xf0) /**< L3GXXXX_REG_CTRL1<7:4> */
|
||||
#define L3GXXXX_POWER_MODE (0x08) /**< L3GXXXX_REG_CTRL1<3> */
|
||||
#define L3GXXXX_Z_ENABLED (0x04) /**< L3GXXXX_REG_CTRL1<2> */
|
||||
#define L3GXXXX_Y_ENABLED (0x02) /**< L3GXXXX_REG_CTRL1<1> */
|
||||
#define L3GXXXX_X_ENABLED (0x01) /**< L3GXXXX_REG_CTRL1<0> */
|
||||
#define L3GXXXX_XYZ_ENABLED (0x07) /**< L3GXXXX_REG_CTRL1<2:0> */
|
||||
|
||||
#define L3GXXXX_ODR_S (6) /**< L3GXXXX_REG_CTRL1<7:6> */
|
||||
#define L3GXXXX_BW_S (4) /**< L3GXXXX_REG_CTRL1<5:4> */
|
||||
#define L3GXXXX_ODR_BW_S (4) /**< L3GXXXX_REG_CTRL1<7:4> */
|
||||
#define L3GXXXX_POWER_MODE_S (3) /**< L3GXXXX_REG_CTRL1<3> */
|
||||
#define L3GXXXX_Z_ENABLED_S (2) /**< L3GXXXX_REG_CTRL1<2> */
|
||||
#define L3GXXXX_Y_ENABLED_S (1) /**< L3GXXXX_REG_CTRL1<1> */
|
||||
#define L3GXXXX_X_ENABLED_S (1) /**< L3GXXXX_REG_CTRL1<0> */
|
||||
#define L3GXXXX_XYZ_ENABLED_S (0) /**< L3GXXXX_REG_CTRL1<2:0> */
|
||||
|
||||
#define L3GXXXX_EXTR_EN (0x80) /**< L3GXXXX_REG_CTRL2<7> */
|
||||
#define L3GXXXX_LVL_EN (0x40) /**< L3GXXXX_REG_CTRL2<6> */
|
||||
#define L3GXXXX_HPF_MODE (0x30) /**< L3GXXXX_REG_CTRL2<5:4> */
|
||||
#define L3GXXXX_HPF_CUTOFF (0x0f) /**< L3GXXXX_REG_CTRL2<3:0> */
|
||||
|
||||
#define L3GXXXX_EXTR_EN_S (7) /**< L3GXXXX_REG_CTRL2<7> */
|
||||
#define L3GXXXX_LVL_EN_S (6) /**< L3GXXXX_REG_CTRL2<6> */
|
||||
#define L3GXXXX_HPF_MODE_S (4) /**< L3GXXXX_REG_CTRL2<5:4> */
|
||||
|
||||
#define L3GXXXX_INT1_IG (0x80) /**< L3GXXXX_REG_CTRL3<7> */
|
||||
#define L3GXXXX_INT1_BOOT (0x40) /**< L3GXXXX_REG_CTRL3<6> */
|
||||
#define L3GXXXX_HL_ACTIVE (0x20) /**< L3GXXXX_REG_CTRL3<5> */
|
||||
#define L3GXXXX_PP_OD (0x10) /**< L3GXXXX_REG_CTRL3<4> */
|
||||
#define L3GXXXX_INT2_DRDY (0x08) /**< L3GXXXX_REG_CTRL3<3> */
|
||||
#define L3GXXXX_INT2_WTM (0x04) /**< L3GXXXX_REG_CTRL3<2> */
|
||||
#define L3GXXXX_INT2_ORUN (0x02) /**< L3GXXXX_REG_CTRL3<1> */
|
||||
#define L3GXXXX_INT2_EMPTY (0x01) /**< L3GXXXX_REG_CTRL3<0> */
|
||||
|
||||
#define L3GXXXX_INT1_IG_S (7) /**< L3GXXXX_REG_CTRL3<7> */
|
||||
#define L3GXXXX_INT1_BOOT_S (6) /**< L3GXXXX_REG_CTRL3<6> */
|
||||
#define L3GXXXX_HL_ACTIVE_S (5) /**< L3GXXXX_REG_CTRL3<5> */
|
||||
#define L3GXXXX_PP_OD_S (4) /**< L3GXXXX_REG_CTRL3<4> */
|
||||
#define L3GXXXX_INT2_DRDY_S (3) /**< L3GXXXX_REG_CTRL3<3> */
|
||||
#define L3GXXXX_INT2_WTM_S (2) /**< L3GXXXX_REG_CTRL3<2> */
|
||||
#define L3GXXXX_INT2_ORUN_S (1) /**< L3GXXXX_REG_CTRL3<1> */
|
||||
#define L3GXXXX_INT2_EMPTY_S (0) /**< L3GXXXX_REG_CTRL3<0> */
|
||||
|
||||
#define L3GXXXX_BLOCK_DATA_UPDATE (0x80) /**< L3GXXXX_REG_CTRL4<7> */
|
||||
#define L3GXXXX_BIG_LITTLE_ENDIAN (0x40) /**< L3GXXXX_REG_CTRL4<6> */
|
||||
#define L3GXXXX_FULL_SCALE (0x30) /**< L3GXXXX_REG_CTRL4<5:4> */
|
||||
|
||||
#define L3GXXXX_FULL_SCALE_S (4) /**< L3GXXXX_REG_CTRL4<5:4> */
|
||||
|
||||
#define L3GXXXX_BOOT (0x80) /**< L3GXXXX_REG_CTRL5<7> */
|
||||
#define L3GXXXX_FIFO_EN (0x40) /**< L3GXXXX_REG_CTRL5<6> */
|
||||
#define L3GXXXX_STOP_ON_WTM (0x20) /**< L3GXXXX_REG_CTRL5<5> */
|
||||
#define L3GXXXX_HP_ENABLED (0x10) /**< L3GXXXX_REG_CTRL5<4> */
|
||||
#define L3GXXXX_IG_SEL (0x0c) /**< L3GXXXX_REG_CTRL5<3:2> */
|
||||
#define L3GXXXX_OUT_SEL (0x03) /**< L3GXXXX_REG_CTRL5<1:0> */
|
||||
|
||||
#define L3GXXXX_BOOT_S (7) /**< L3GXXXX_REG_CTRL5<7> */
|
||||
#define L3GXXXX_FIFO_EN_S (6) /**< L3GXXXX_REG_CTRL5<6> */
|
||||
#define L3GXXXX_STOP_ON_WTM_S (5) /**< L3GXXXX_REG_CTRL5<5> */
|
||||
#define L3GXXXX_HP_ENABLED_S (4) /**< L3GXXXX_REG_CTRL5<4> */
|
||||
#define L3GXXXX_IG_SEL_S (2) /**< L3GXXXX_REG_CTRL5<3:2> */
|
||||
#define L3GXXXX_OUT_SEL_S (0) /**< L3GXXXX_REG_CTRL5<1:0> */
|
||||
|
||||
#define L3GXXXX_FIFO_MODE (0xe0) /**< L3GXXXX_REG_FIFO_CTRL<7:5> */
|
||||
#define L3GXXXX_FIFO_WATERMARK (0x1f) /**< L3GXXXX_REG_FIFO_CTRL<4:0> */
|
||||
|
||||
#define L3GXXXX_FIFO_MODE_S (5) /**< L3GXXXX_REG_FIFO_CTRL<7:5> */
|
||||
#define L3GXXXX_FIFO_WATERMARK_S (0) /**< L3GXXXX_REG_FIFO_CTRL<4:0> */
|
||||
|
||||
#define L3GXXXX_FIFO_WTM (0x80) /**< L3GXXXX_REG_FIFO_SRC<7> */
|
||||
#define L3GXXXX_FIFO_OVR (0x40) /**< L3GXXXX_REG_FIFO_SRC<6> */
|
||||
#define L3GXXXX_FIFO_EMPTY (0x20) /**< L3GXXXX_REG_FIFO_SRC<5> */
|
||||
#define L3GXXXX_FIFO_FFS (0x1f) /**< L3GXXXX_REG_FIFO_SRC<4:0> */
|
||||
|
||||
#define L3GXXXX_FIFO_WTM_S (7) /**< L3GXXXX_REG_FIFO_SRC<7> */
|
||||
#define L3GXXXX_FIFO_OVR_S (6) /**< L3GXXXX_REG_FIFO_SRC<6> */
|
||||
#define L3GXXXX_FIFO_EMPTY_S (5) /**< L3GXXXX_REG_FIFO_SRC<5> */
|
||||
#define L3GXXXX_FIFO_FFS_S (0) /**< L3GXXXX_REG_FIFO_SRC<4:0> */
|
||||
|
||||
#define L3GXXXX_INT1_AND_OR (0x80) /**< L3GXXXX_REG_IG_CFG<7> */
|
||||
#define L3GXXXX_INT1_LATCH (0x40) /**< L3GXXXX_REG_IG_CFG<6> */
|
||||
#define L3GXXXX_INT1_Z_HIGH (0x20) /**< L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5> */
|
||||
#define L3GXXXX_INT1_Z_LOW (0x10) /**< L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4> */
|
||||
#define L3GXXXX_INT1_Y_HIGH (0x08) /**< L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3> */
|
||||
#define L3GXXXX_INT1_Y_LOW (0x04) /**< L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2> */
|
||||
#define L3GXXXX_INT1_X_HIGH (0x02) /**< L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1> */
|
||||
#define L3GXXXX_INT1_X_LOW (0x01) /**< L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0> */
|
||||
|
||||
#define L3GXXXX_INT1_AND_OR_S (7) /**< L3GXXXX_REG_IG_CFG<7> */
|
||||
#define L3GXXXX_INT1_LATCH_S (6) /**< L3GXXXX_REG_IG_CFG<6> */
|
||||
#define L3GXXXX_INT1_Z_HIGH_S (5) /**< L3GXXXX_REG_IG_CFG<5>, L3GXXXX_REG_IG_SRC<5> */
|
||||
#define L3GXXXX_INT1_Z_LOW_S (4) /**< L3GXXXX_REG_IG_CFG<4>, L3GXXXX_REG_IG_SRC<4> */
|
||||
#define L3GXXXX_INT1_Y_HIGH_S (3) /**< L3GXXXX_REG_IG_CFG<3>, L3GXXXX_REG_IG_SRC<3> */
|
||||
#define L3GXXXX_INT1_Y_LOW_S (2) /**< L3GXXXX_REG_IG_CFG<2>, L3GXXXX_REG_IG_SRC<2> */
|
||||
#define L3GXXXX_INT1_X_HIGH_S (1) /**< L3GXXXX_REG_IG_CFG<1>, L3GXXXX_REG_IG_SRC<1> */
|
||||
#define L3GXXXX_INT1_X_LOW_S (0) /**< L3GXXXX_REG_IG_CFG<0>, L3GXXXX_REG_IG_SRC<0> */
|
||||
|
||||
#define L3GXXXX_INT1_ACTIVE (0x40) /**< L3GXXXX_REG_IG_SRC<6> */
|
||||
|
||||
#define L3GXXXX_INT1_WAIT (0x80) /**< L3GXXXX_REG_IG_DURATION<7> */
|
||||
#define L3GXXXX_INT1_DURATION (0x3f) /**< L3GXXXX_REG_IG_DURATION<6:0> */
|
||||
|
||||
#define L3GXXXX_INT1_WAIT_S (7) /**< L3GXXXX_REG_IG_DURATION<7> */
|
||||
#define L3GXXXX_INT1_DURATION_S (0) /**< L3GXXXX_REG_IG_DURATION<6:0> */
|
||||
|
||||
#define L3GXXXX_DRDY_HL (0x20) /**< L3GXXXX_REG_LOW_ODR<5> */
|
||||
#define L3GXXXX_SW_RESET (0x04) /**< L3GXXXX_REG_LOW_ODR<2> */
|
||||
#define L3GXXXX_LOW_ODR (0x01) /**< L3GXXXX_REG_LOW_ODR<0> */
|
||||
|
||||
#define L3GXXXX_DRDY_HL_S (5) /**< L3GXXXX_REG_LOW_ODR<5> */
|
||||
#define L3GXXXX_SW_RESET_S (2) /**< L3GXXXX_REG_LOW_ODR<2> */
|
||||
#define L3GXXXX_LOW_ODR_S (0) /**< L3GXXXX_REG_LOW_ODR<0> */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* L3GXXXX_REGS_H */
|
||||
/** @} */
|
||||
1143
drivers/l3gxxxx/l3gxxxx.c
Normal file
1143
drivers/l3gxxxx/l3gxxxx.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user