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https://github.com/RIOT-OS/RIOT.git
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Merge pull request #1532 from cgundogan/remove_tabs_asm
cpu: removing tabs from asm files (#1439)
This commit is contained in:
Ludwig Ortmann
commit
153b577877
@ -129,7 +129,7 @@ task_return:
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*
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*----------------------------------------------------------------------------*/
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arm_irq_handler:
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sub lr, lr, #4
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sub lr, lr, #4
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/* save interrupted tasks PC onto stack */
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stmfd sp!, {lr}
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@ -151,7 +151,7 @@ arm_irq_handler:
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add lr,pc,#4
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.else
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/* mc1322x seems to lack a VIC, distinction of IRQ has to be done in SW */
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ldr r0, =isr /* mc1322x */
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ldr r0, =isr /* mc1322x */
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.endif
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mov pc, r0
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@ -13,91 +13,91 @@
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.global Copy_un2al
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.arm
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Copy_un2al:
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STMFD SP!, {R4-R8}
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ANDS IP, R1, #3
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BEQ lb_align
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STMFD SP!, {R4-R8}
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ANDS IP, R1, #3
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BEQ lb_align
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BIC R1, #3
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MOV IP, IP, LSL #3
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RSB R8, IP, #32
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LDMIA R1!, {R7}
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lb_l1: MOV R3, R7
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LDMIA R1!, {R4-R7}
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MOV R3, R3, LSR IP
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ORR R3, R3, R4, LSL R8
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MOV R4, R4, LSR IP
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ORR R4, R4, R5, LSL R8
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MOV R5, R5, LSR IP
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ORR R5, R5, R6, LSL R8
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MOV R6, R6, LSR IP
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ORR R6, R6, R7, LSL R8
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE lb_l1
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LDMFD SP!, {R4-R8}
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BX LR
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BIC R1, #3
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MOV IP, IP, LSL #3
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RSB R8, IP, #32
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LDMIA R1!, {R7}
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lb_l1: MOV R3, R7
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LDMIA R1!, {R4-R7}
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MOV R3, R3, LSR IP
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ORR R3, R3, R4, LSL R8
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MOV R4, R4, LSR IP
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ORR R4, R4, R5, LSL R8
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MOV R5, R5, LSR IP
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ORR R5, R5, R6, LSL R8
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MOV R6, R6, LSR IP
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ORR R6, R6, R7, LSL R8
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE lb_l1
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LDMFD SP!, {R4-R8}
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BX LR
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lb_align:
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LDMIA R1!, {R3-R6}
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE lb_align
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LDMFD SP!, {R4-R8}
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BX LR
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LDMIA R1!, {R3-R6}
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE lb_align
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LDMFD SP!, {R4-R8}
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BX LR
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.global Copy_al2un
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.arm
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Copy_al2un:
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STMFD SP!, {R4-R8}
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ANDS IP, R0, #3
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BEQ sb_align
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STMFD SP!, {R4-R8}
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ANDS IP, R0, #3
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BEQ sb_align
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MOV IP, IP, LSL #3
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RSB R8, IP, #32
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MOV IP, IP, LSL #3
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RSB R8, IP, #32
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LDMIA R1!, {R4-R7}
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sb_p1: STRB R4, [R0], #1
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MOV R4, R4, LSR #8
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TST R0, #3
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BNE sb_p1
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ORR R4, R4, R5, LSL IP
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MOV R5, R5, LSR R8
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ORR R5, R5, R6, LSL IP
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MOV R6, R6, LSR R8
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ORR R6, R6, R7, LSL IP
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SUBS R2, R2, #16
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STMIA R0!, {R4-R6}
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LDMIA R1!, {R4-R7}
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sb_p1: STRB R4, [R0], #1
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MOV R4, R4, LSR #8
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TST R0, #3
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BNE sb_p1
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ORR R4, R4, R5, LSL IP
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MOV R5, R5, LSR R8
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ORR R5, R5, R6, LSL IP
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MOV R6, R6, LSR R8
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ORR R6, R6, R7, LSL IP
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SUBS R2, R2, #16
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STMIA R0!, {R4-R6}
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sb_l1: MOV R3, R7
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LDMIA R1!, {R4-R7}
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MOV R3, R3, LSR R8
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ORR R3, R3, R4, LSL IP
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MOV R4, R4, LSR R8
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ORR R4, R4, R5, LSL IP
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MOV R5, R5, LSR R8
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ORR R5, R5, R6, LSL IP
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MOV R6, R6, LSR R8
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ORR R6, R6, R7, LSL IP
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE sb_l1
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sb_l1: MOV R3, R7
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LDMIA R1!, {R4-R7}
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MOV R3, R3, LSR R8
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ORR R3, R3, R4, LSL IP
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MOV R4, R4, LSR R8
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ORR R4, R4, R5, LSL IP
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MOV R5, R5, LSR R8
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ORR R5, R5, R6, LSL IP
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MOV R6, R6, LSR R8
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ORR R6, R6, R7, LSL IP
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SUBS R2, R2, #16
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STMIA R0!, {R3-R6}
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BNE sb_l1
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MOV R7, R7, LSR R8
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sb_p2: SUBS IP, IP, #8
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STRB R7, [R0], #1
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MOV R7, R7, LSR #8
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BNE sb_p2
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MOV R7, R7, LSR R8
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sb_p2: SUBS IP, IP, #8
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STRB R7, [R0], #1
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MOV R7, R7, LSR #8
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BNE sb_p2
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LDMFD SP!, {R4-R8}
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BX LR
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LDMFD SP!, {R4-R8}
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BX LR
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sb_align:
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LDMIA R1!, {R3-R6}
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SUBS R2, #16
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STMIA R0!, {R3-R6}
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BNE sb_align
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LDMFD SP!, {R4-R8}
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BX LR
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LDMIA R1!, {R3-R6}
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SUBS R2, #16
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STMIA R0!, {R3-R6}
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BNE sb_align
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LDMFD SP!, {R4-R8}
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BX LR
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.end
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@ -8,11 +8,11 @@
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/* ***************************************************************************************************************
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startup.s STARTUP ASSEMBLY CODE
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-----------------------
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startup.s STARTUP ASSEMBLY CODE
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-----------------------
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Module includes the interrupt vectors and start-up code.
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Module includes the interrupt vectors and start-up code.
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*************************************************************************************************************** */
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@ -29,16 +29,16 @@
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.extern __start_svc_start
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/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */
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.set MODE_USR, 0x10 /* Normal User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
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.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
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.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
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.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
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.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
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.set MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
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.set MODE_USR, 0x10 /* Normal User Mode */
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.set MODE_FIQ, 0x11 /* FIQ Processing Fast Interrupts Mode */
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.set MODE_IRQ, 0x12 /* IRQ Processing Standard Interrupts Mode */
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.set MODE_SVC, 0x13 /* Supervisor Processing Software Interrupts Mode */
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.set MODE_ABT, 0x17 /* Abort Processing memory Faults Mode */
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.set MODE_UND, 0x1B /* Undefined Processing Undefined Instructions Mode */
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.set MODE_SYS, 0x1F /* System Running Priviledged Operating System Tasks Mode */
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.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
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.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
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.set I_BIT, 0x80 /* when I bit is set, IRQ is disabled (program status registers) */
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.set F_BIT, 0x40 /* when F bit is set, FIQ is disabled (program status registers) */
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.text
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.arm
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@ -47,24 +47,24 @@
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It is 64 bytes and can be mapped (see documentation 1.4.2). */
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.section .vectors
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/* Exception Vectors */
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ldr PC, Reset_Addr /* Reset */
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ldr PC, Undef_Addr /* Undefined Instruction */
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ldr PC, SWI_Addr /* Software Interrupt */
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ldr PC, PAbt_Addr /* Prefetch Abort */
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ldr PC, DAbt_Addr /* Data Abort */
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nop /* Reserved Vector (holds Philips ISP checksum) */
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ldr PC, Reset_Addr /* Reset */
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ldr PC, Undef_Addr /* Undefined Instruction */
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ldr PC, SWI_Addr /* Software Interrupt */
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ldr PC, PAbt_Addr /* Prefetch Abort */
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ldr PC, DAbt_Addr /* Data Abort */
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nop /* Reserved Vector (holds Philips ISP checksum) */
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/* see page 71 of "Insiders Guide to the Philips ARM7-Based Microcontrollers" by Trevor Martin */
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/* ldr PC, [PC,#-0x0120] /* Interrupt Request Interrupt (load from VIC) */
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ldr PC, IRQ_Addr /* Interrupt Request Interrupt (load from VIC) */
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ldr r0, =__fiq_handler /* Fast Interrupt Request Interrupt */
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ldr pc, [r0] /* jump to handler in pointer at __fiq_handler */
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/* ldr PC, [PC,#-0x0120] /* Interrupt Request Interrupt (load from VIC) */
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ldr PC, IRQ_Addr /* Interrupt Request Interrupt (load from VIC) */
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ldr r0, =__fiq_handler /* Fast Interrupt Request Interrupt */
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ldr pc, [r0] /* jump to handler in pointer at __fiq_handler */
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/* Exception vector handlers branching table */
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Reset_Addr: .word Reset_Handler /* defined in this module below */
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Undef_Addr: .word UNDEF_Routine /* defined in main.c */
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SWI_Addr: .word ctx_switch /* defined in main.c */
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PAbt_Addr: .word PABT_Routine /* defined in main.c */
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DAbt_Addr: .word DABT_Routine /* defined in main.c */
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Reset_Addr: .word Reset_Handler /* defined in this module below */
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Undef_Addr: .word UNDEF_Routine /* defined in main.c */
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SWI_Addr: .word ctx_switch /* defined in main.c */
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PAbt_Addr: .word PABT_Routine /* defined in main.c */
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DAbt_Addr: .word DABT_Routine /* defined in main.c */
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IRQ_Addr: .word arm_irq_handler /* defined in main.c */
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/* Begin of boot code */
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@ -76,29 +76,29 @@ IRQ_Addr: .word arm_irq_handler /* defined in main.c */
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.func _startup
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_startup:
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ldr pc, =Reset_Handler
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ldr pc, =Reset_Handler
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/*.func Reset_Handler */
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Reset_Handler:
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.section .init0
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/* Setup a stack for each mode - note that this only sets up a usable stack
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for User mode. Also each mode is setup with interrupts initially disabled. */
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ldr r0, = __stack_end
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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ldr sp, =__stack_und_start
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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ldr sp, =__stack_abt_start
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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ldr sp, =__stack_fiq_start
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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ldr sp, =__stack_irq_start
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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ldr sp, =__stack_svc_start
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msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
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ldr sp, =__stack_usr_start
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/* Setup a stack for each mode - note that this only sets up a usable stack
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for User mode. Also each mode is setup with interrupts initially disabled. */
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ldr r0, = __stack_end
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msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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ldr sp, =__stack_und_start
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msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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ldr sp, =__stack_abt_start
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msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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ldr sp, =__stack_fiq_start
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msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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ldr sp, =__stack_irq_start
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msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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ldr sp, =__stack_svc_start
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msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* User Mode */
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ldr sp, =__stack_usr_start
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.section .init2 /* copy .data section (Copy from ROM to RAM) */
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.section .init2 /* copy .data section (Copy from ROM to RAM) */
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.extern _etext
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.extern _data
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.extern _edata
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@ -106,30 +106,30 @@ Reset_Handler:
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ldr R1, =_etext
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ldr R2, =_data
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ldr R3, =_edata
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LoopRel: cmp R2, R3
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LoopRel: cmp R2, R3
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ldrlo R0, [R1], #4
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strlo R0, [R2], #4
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blo LoopRel
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*/
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.section .init4 /* Clear .bss section (Zero init) */
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.section .init4 /* Clear .bss section (Zero init) */
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.extern __bss_start
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.extern __bss_end
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/*
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mov R0, #0
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ldr R1, =__bss_start
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ldr R2, =__bss_end
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LoopZI: cmp R1, R2
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LoopZI: cmp R1, R2
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strlo R0, [R1], #4
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blo LoopZI
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*/
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/* Enter the C code */
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/* Enter the C code */
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.section .init9
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bl bootloader
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b kernel_init
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/* Infinite Loop */
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.section .fini0
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__main_exit: B __main_exit
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__main_exit: B __main_exit
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.endfunc
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