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cpu/stm32/periph_i2c: improve DEBUG output

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This commit is contained in:
Marian Buschsieweke 2023-12-10 16:16:48 +01:00
parent fd3d92f1ba
commit 13f0a5062d
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GPG Key ID: 77AA882EC78084E6
1 changed files with 42 additions and 26 deletions
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68
cpu/stm32/periph/i2c_2.c
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@ -48,7 +48,9 @@
#include "periph/gpio.h"
#include "periph_conf.h"
/* Some DEBUG statements may cause delays that alter i2c functionality */
/* Some DEBUG statements may cause delays that alter i2c functionality.
* E.g. on STM32F1 the delay can cause issues in the state machine that
* prevent communication. Using faster stdio than UART can mitigate this. */
#define ENABLE_DEBUG 0
#include "debug.h"
@ -223,7 +225,7 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
assert(dev < I2C_NUMOF);
I2C_TypeDef *i2c = i2c_config[dev].dev;
DEBUG("[i2c] read_bytes: Starting\n");
DEBUG_PUTS("[i2c] i2c_read_bytes(): Starting");
/* Do not support repeated start reading
* The repeated start read requires the bus to be busy (I2C_SR2_BUSY == 1)
@ -260,11 +262,12 @@ int i2c_read_bytes(i2c_t dev, uint16_t address, void *data, size_t length,
/* Wait for reception to complete */
ret = _is_sr1_mask_set(i2c, I2C_SR1_RXNE, flags);
if (ret < 0) {
DEBUG_PUTS("[i2c] i2c_read_bytes(): Waiting for I2C_SR1_RXNE failed");
return ret;
}
((uint8_t*)data)[i] = i2c->DR;
}
DEBUG("[i2c] read_bytes: Finished reading bytes\n");
DEBUG_PUTS("[i2c] i2c_read_bytes(): Finished reading bytes");
if (flags & I2C_NOSTOP) {
return 0;
}
@ -280,7 +283,7 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
I2C_TypeDef *i2c = i2c_config[dev].dev;
assert(i2c != NULL);
DEBUG("[i2c] write_bytes: Starting\n");
DEBUG_PUTS("[i2c] i2c_write_bytes(): Starting");
/* Length is 0 in start since we don't need to preset the stop bit */
ret = _i2c_start(i2c, (address << 1) | I2C_FLAG_WRITE, flags, 0);
if (ret < 0) {
@ -292,17 +295,19 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
/* Send out data bytes */
for (size_t i = 0; i < length; i++) {
DEBUG("[i2c] write_bytes: Waiting for TX reg to be free\n");
DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for TX reg to be free");
ret = _is_sr1_mask_set(i2c, I2C_SR1_TXE, flags);
if (ret < 0) {
DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for I2C_SR1_TXE failed");
return ret;
}
DEBUG("[i2c] write_bytes: TX is free so send byte\n");
DEBUG_PUTS("[i2c] i2c_write_bytes(): TX is free so send byte");
i2c->DR = ((uint8_t*)data)[i];
}
/* Wait for tx reg to be empty so other calls will no interfere */
ret = _is_sr1_mask_set(i2c, I2C_SR1_TXE, flags);
if (ret < 0) {
DEBUG_PUTS("[i2c] i2c_write_bytes(): Waiting for I2C_SR1_TXE failed");
return ret;
}
if (flags & I2C_NOSTOP) {
@ -310,12 +315,12 @@ int i2c_write_bytes(i2c_t dev, uint16_t address, const void *data,
}
else {
/* End transmission */
DEBUG("[i2c] write_bytes: Ending transmission\n");
DEBUG_PUTS("[i2c] i2c_write_bytes(): Ending transmission");
ret = _stop(i2c);
if (ret < 0) {
return ret;
}
DEBUG("[i2c] write_bytes: STOP condition was send out\n");
DEBUG_PUTS("[i2c] i2c_write_bytes(): STOP condition was send out");
}
return _wait_for_bus(i2c);
@ -335,18 +340,19 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
i2c->SR1 &= ~ERROR_FLAG;
if (!(flags & I2C_NOSTART)) {
DEBUG("[i2c] start: Generate start condition\n");
DEBUG_PUTS("[i2c] _i2c_start(): Generate start condition");
/* Generate start condition */
i2c->CR1 |= I2C_CR1_START | I2C_CR1_ACK;
/* Wait for SB flag to be set */
int ret = _is_sr1_mask_set(i2c, I2C_SR1_SB, flags & ~I2C_NOSTOP);
if (ret < 0) {
DEBUG_PUTS("[i2c] _i2c_start(): Waiting for I2C_SR1_SB failed");
return ret;
}
DEBUG("[i2c] start: Start condition generated\n");
DEBUG_PUTS("[i2c] _i2c_start(): Start condition generated");
DEBUG("[i2c] start: Generating address\n");
DEBUG_PUTS("[i2c] _i2c_start(): Generating address");
/* Send address and read/write flag */
i2c->DR = (address_byte);
if (!(flags & I2C_NOSTOP) && length == 1) {
@ -354,8 +360,9 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
}
/* Wait for ADDR flag to be set */
ret = _is_sr1_mask_set(i2c, I2C_SR1_ADDR, flags & ~I2C_NOSTOP);
if (ret == -EIO){
if (ret == -EIO) {
/* Since NACK happened during start it means no device connected */
DEBUG_PUTS("[i2c] _i2c_start(): Address NACKED");
return -ENXIO;
}
/* Needed to clear address bit */
@ -364,7 +371,12 @@ static int _i2c_start(I2C_TypeDef *i2c, uint8_t address_byte, uint8_t flags,
/* Stop must also be sent before final read */
i2c->CR1 |= (I2C_CR1_STOP);
}
DEBUG("[i2c] start: Address generated\n");
if (ret) {
DEBUG_PUTS("[i2c] _i2c_start(): Waiting for I2C_SR1_ADDR failed");
}
else {
DEBUG_PUTS("[i2c] _i2c_start(): Address generated");
}
return ret;
}
return 0;
@ -377,7 +389,7 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
while (tick--) {
uint32_t sr1 = i2c->SR1;
if (sr1 & I2C_SR1_AF) {
DEBUG("[i2c] is_sr1_mask_set: NACK received\n");
DEBUG_PUTS("[i2c] _is_sr1_mask_set(): NACK received");
i2c->SR1 &= ~ERROR_FLAG;
if (!(flags & I2C_NOSTOP)) {
_stop(i2c);
@ -385,7 +397,7 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
return -EIO;
}
if ((sr1 & I2C_SR1_ARLO) || (sr1 & I2C_SR1_BERR)) {
DEBUG("[i2c] is_sr1_mask_set: arb lost or bus ERROR_FLAG\n");
DEBUG_PUTS("[i2c] _is_sr1_mask_set(): arb lost or bus ERROR_FLAG");
i2c->SR1 &= ~ERROR_FLAG;
_stop(i2c);
return -EAGAIN;
@ -401,25 +413,28 @@ static int _is_sr1_mask_set(I2C_TypeDef *i2c, uint32_t mask, uint8_t flags)
*/
i2c->SR1 &= ~ERROR_FLAG;
_stop(i2c);
DEBUG_PUTS("[i2c] _is_sr1_mask_set(): Timed out");
return -ETIMEDOUT;
}
static int _stop(I2C_TypeDef *i2c)
{
/* send STOP condition */
DEBUG("[i2c] stop: Generate stop condition\n");
DEBUG_PUTS("[i2c] _stop(): Generate stop condition");
i2c->CR1 &= ~(I2C_CR1_ACK);
i2c->CR1 |= I2C_CR1_STOP;
uint16_t tick = TICK_TIMEOUT;
while ((i2c->CR1 & I2C_CR1_STOP) && tick--) {}
if (!tick) {
DEBUG_PUTS("[i2c] _stop(): Stop condition timed out");
return -ETIMEDOUT;
}
DEBUG("[i2c] stop: Stop condition succeeded\n");
DEBUG_PUTS("[i2c] _stop(): Stop condition succeeded");
if (_wait_for_bus(i2c) < 0) {
DEBUG_PUTS("[i2c] _stop(): Bus free timed out");
return -ETIMEDOUT;
}
DEBUG("[i2c] stop: Bus is free\n");
DEBUG_PUTS("[i2c] _stop(): Bus is free");
return 0;
}
@ -428,6 +443,7 @@ static inline int _wait_for_bus(I2C_TypeDef *i2c)
uint16_t tick = TICK_TIMEOUT;
while ((i2c->SR2 & I2C_SR2_BUSY) && tick--) {}
if (!tick) {
DEBUG_PUTS("[i2c] _wait_for_bus(): Timed out");
return -ETIMEDOUT;
}
return 0;
@ -443,28 +459,28 @@ static inline void irq_handler(i2c_t dev)
assert(i2c != NULL);
unsigned state = i2c->SR1;
DEBUG("\n\n### I2C ERROR OCCURRED ###\n");
DEBUG_PUTS("\n\n### I2C ERROR OCCURRED ###");
DEBUG("status: %08x\n", state);
if (state & I2C_SR1_OVR) {
DEBUG("OVR\n");
DEBUG_PUTS("OVR");
}
if (state & I2C_SR1_AF) {
DEBUG("AF\n");
DEBUG_PUTS("AF");
}
if (state & I2C_SR1_ARLO) {
DEBUG("ARLO\n");
DEBUG_PUTS("ARLO");
}
if (state & I2C_SR1_BERR) {
DEBUG("BERR\n");
DEBUG_PUTS("BERR");
}
if (state & I2C_SR1_PECERR) {
DEBUG("PECERR\n");
DEBUG_PUTS("PECERR");
}
if (state & I2C_SR1_TIMEOUT) {
DEBUG("TIMEOUT\n");
DEBUG_PUTS("TIMEOUT");
}
if (state & I2C_SR1_SMBALERT) {
DEBUG("SMBALERT\n");
DEBUG_PUTS("SMBALERT");
}
core_panic(PANIC_GENERAL_ERROR, "I2C FAULT");
}