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build system: Fix compilation for RISC-V with newer GCC

A backward incompatible change in the RISC-V resulting in instructions
previously included by rv32imac to only be available with
rv32imac_zicsr. All RISC-V CPUs supported by RIOT are hence either
considered as rv32imac (from the old ISA spec point of view) or as
rv32imac_zicsr (from the new ISA spec point of view). This adds a
simple test if GCC understands rv32imac_zicsr and uses it then as march,
but uses rv32imac as march if not.
This commit is contained in:
Marian Buschsieweke 2022-04-14 16:52:48 +02:00
parent 32790eb8f2
commit 10f65f1631
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@ -30,8 +30,24 @@ TARGET_ARCH_RISCV ?= \
TARGET_ARCH ?= $(TARGET_ARCH_RISCV)
# define build specific options
CFLAGS_CPU = -march=rv32imac -mabi=ilp32
ifeq ($(TOOLCHAIN),gnu)
NEW_RISCV_ISA := $(shell echo "" | $(TARGET_ARCH)-as -march=rv32imac_zicsr -mabi=ilp32 - > /dev/null 2>&1 && echo 1 || echo 0)
endif
NEW_RISCV_ISA ?= 0
# Since RISC-V ISA specifications 20191213 instructions previously included in
# rv32imac have been moved to the ZICSR extension. See
# https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
#
# Select the march based on the ISA spec implemented by the used compiler:
ifeq (1,$(NEW_RISCV_ISA))
CFLAGS_CPU := -march=rv32imac_zicsr
else
CFLAGS_CPU := -march=rv32imac
endif
CFLAGS_CPU += -mabi=ilp32
ifeq ($(TOOLCHAIN),llvm)
# Always use riscv32-none-elf as target triple for clang, as some
# autodetected gcc target triples are incompatible with clang
@ -53,7 +69,7 @@ LINKFLAGS += -T$(LINKER_SCRIPT)
CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
# export linker flags
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
LINKFLAGS += -march=rv32imac -mabi=ilp32 $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
# Platform triple as used by Rust
RUST_TARGET = riscv32imac-unknown-none-elf