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build system: Fix compilation for RISC-V with newer GCC
A backward incompatible change in the RISC-V resulting in instructions previously included by rv32imac to only be available with rv32imac_zicsr. All RISC-V CPUs supported by RIOT are hence either considered as rv32imac (from the old ISA spec point of view) or as rv32imac_zicsr (from the new ISA spec point of view). This adds a simple test if GCC understands rv32imac_zicsr and uses it then as march, but uses rv32imac as march if not.
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@ -30,8 +30,24 @@ TARGET_ARCH_RISCV ?= \
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TARGET_ARCH ?= $(TARGET_ARCH_RISCV)
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# define build specific options
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CFLAGS_CPU = -march=rv32imac -mabi=ilp32
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ifeq ($(TOOLCHAIN),gnu)
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NEW_RISCV_ISA := $(shell echo "" | $(TARGET_ARCH)-as -march=rv32imac_zicsr -mabi=ilp32 - > /dev/null 2>&1 && echo 1 || echo 0)
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endif
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NEW_RISCV_ISA ?= 0
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# Since RISC-V ISA specifications 20191213 instructions previously included in
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# rv32imac have been moved to the ZICSR extension. See
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# https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf
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#
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# Select the march based on the ISA spec implemented by the used compiler:
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ifeq (1,$(NEW_RISCV_ISA))
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CFLAGS_CPU := -march=rv32imac_zicsr
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else
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CFLAGS_CPU := -march=rv32imac
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endif
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CFLAGS_CPU += -mabi=ilp32
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ifeq ($(TOOLCHAIN),llvm)
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# Always use riscv32-none-elf as target triple for clang, as some
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# autodetected gcc target triples are incompatible with clang
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@ -53,7 +69,7 @@ LINKFLAGS += -T$(LINKER_SCRIPT)
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CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
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ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
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# export linker flags
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LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
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LINKFLAGS += -march=rv32imac -mabi=ilp32 $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -nostartfiles -Wl,--gc-sections -static -lgcc
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# Platform triple as used by Rust
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RUST_TARGET = riscv32imac-unknown-none-elf
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