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cpu/qn908x: use bitarithm_test_and_clear() & fix cb

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Previously, the callback was incorrectly passed a channel of zero as
argument regardless of the channel that triggered the IRQ. This fixes
the issue and also uses `bitarithm_test_and_clear()` to only iterate
over the channels that actually have an IRQ flag set, rather than
all channels.
This commit is contained in:
Marian Buschsieweke 2022-11-28 16:36:34 +01:00
parent c95028655d
commit 0d85356180
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GPG Key ID: CB8E3238CE715A94
1 changed files with 12 additions and 10 deletions
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22
cpu/qn908x/periph/timer.c
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@ -25,10 +25,11 @@
#include <stdlib.h>
#include "cpu.h"
#include "bitarithm.h"
#include "board.h"
#include "periph_conf.h"
#include "cpu.h"
#include "periph/timer.h"
#include "periph_conf.h"
#include "vendor/drivers/fsl_clock.h"
@ -144,14 +145,15 @@ static inline void isr_ctimer_n(CTIMER_Type *dev, uint32_t ctimer_num)
{
DEBUG("isr_ctimer_%" PRIu32 " flags=0x%" PRIx32 "\n",
ctimer_num, dev->IR);
for (uint32_t i = 0; i < TIMER_CHANNELS; i++) {
if (dev->IR & (1u << i)) {
/* Note: setting the bit to 1 in the flag register will clear the
* bit. */
dev->IR = 1u << i;
dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (i * 3));
isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, 0);
}
unsigned state = dev->IR & ((1 << TIMER_CHANNELS) - 1);
while (state) {
uint8_t channel;
state = bitarithm_test_and_clear(state, &channel);
/* Note: setting the bit to 1 in the flag register will clear the
* bit. */
dev->IR = 1u << channel;
dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (channel * 3));
isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, channel);
}
cortexm_isr_end();
}