Merge pull request #7434 from gebart/pr/kinetis-update-headers

kinetis: update vendor headers

boards/frdm-k22f/include/periph_conf.h

@@ -103,7 +103,7 @@ static const uart_conf_t uart_config[] = {
         .pcr_rx = PORT_PCR_MUX(3),
         .pcr_tx = PORT_PCR_MUX(3),
         .irqn   = UART1_RX_TX_IRQn,
-        .scgc_addr = &SIM_SCGC4,
+        .scgc_addr = &SIM->SCGC4,
         .scgc_bit = SIM_SCGC4_UART1_SHIFT,
         .mode   = UART_MODE_8N1,
     },

cpu/k22f/include/vendor/MK22F12810.h

@@ -11770,5 +11770,3 @@ typedef struct {
     #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
   #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
 #endif  /* #if !defined(MK22F12810_H_) */
-
-/* MK22F12810.h, eof. */

cpu/k22f/include/vendor/MK22F25612.h

@@ -12639,5 +12639,3 @@ typedef struct {
     #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
   #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
 #endif  /* #if !defined(MK22F25612_H_) */
-
-/* MK22F25612.h, eof. */

cpu/k22f/include/vendor/MK22FA12.h

@@ -16502,5 +16502,3 @@ typedef struct {
     #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
   #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
 #endif  /* #if !defined(MK22FA12_H_) */
-
-/* MK22FA12.h, eof. */

cpu/k60/include/vendor/MK60D10.h

@@ -14576,13 +14576,6 @@ typedef struct {
 #define LPTimer_IRQn                             LPTMR0_IRQn
 #define LPTimer_IRQHandler                       LPTMR0_IRQHandler
 
-/* Compatibility defines for compatibility with differing module names between
- * MK60 and MKW22 headers */
-#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
-#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
-#define OSC0 OSC
-#define MCG_C7_OSCSEL(x) (((uint32_t)(x) << MCG_C7_OSCSEL_SHIFT) & MCG_C7_OSCSEL_MASK)
-
 /*!
  * @}
  */ /* end of group Backward_Compatibility_Symbols */
@@ -14600,5 +14593,3 @@ typedef struct {
 #ifdef __cplusplus
 }
 #endif
-
-/* MK60D10.h, eof. */

cpu/kinetis_common/include/cpu_conf_kinetis.h

@@ -55,6 +55,52 @@ extern "C"
 #define PIN_INTERRUPT_EDGE 0b1011
 /** @} */
 
+/**
+ * @name Compatibility definitions between vendor headers
+ * @{
+ */
+/* Different versions of vendor headers use some variations of register names.
+ * This section aims to eliminate these differences in the few places where it
+ * matters for the RIOT driver implementations.
+ */
+#if !defined(MCG_C2_RANGE0) && defined(MCG_C2_RANGE)
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#endif
+#if !defined(MCG_C2_RANGE0_MASK) && defined(MCG_C2_RANGE_MASK)
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#endif
+#if !defined(MCG_C7_OSCSEL) && defined(MCG_C7_OSCSEL_SHIFT)
+#define MCG_C7_OSCSEL(x) (((uint32_t)(x) << MCG_C7_OSCSEL_SHIFT) & MCG_C7_OSCSEL_MASK)
+#endif
+#if !defined(OSC0) && defined(OSC)
+#define OSC0 OSC
+#endif
+#if !defined(SIM_SCGC5_LPTMR_SHIFT) && defined(SIM_SCGC5_LPTIMER_SHIFT)
+#define SIM_SCGC5_LPTMR_SHIFT SIM_SCGC5_LPTIMER_SHIFT
+#endif
+#if !defined(SIM_SCGC5_LPTMR_MASK) && defined(SIM_SCGC5_LPTIMER_MASK)
+#define SIM_SCGC5_LPTMR_MASK SIM_SCGC5_LPTIMER_MASK
+#endif
+#if !defined(GPIOA_BASE) && defined(PTA_BASE)
+#define GPIOA_BASE PTA_BASE
+#define GPIOB_BASE PTB_BASE
+#define GPIOC_BASE PTC_BASE
+#define GPIOD_BASE PTD_BASE
+#define GPIOE_BASE PTE_BASE
+#define GPIOF_BASE PTF_BASE
+#define GPIOG_BASE PTG_BASE
+#endif
+#if !defined(GPIOA) && defined(PTA)
+#define GPIOA PTA
+#define GPIOB PTB
+#define GPIOC PTC
+#define GPIOD PTD
+#define GPIOE PTE
+#define GPIOF PTF
+#define GPIOG PTG
+#endif
+/** @} */
+
 /**
  * @name Timer hardware information
  * @{

cpu/kinetis_common/include/periph_cpu.h

@@ -241,6 +241,7 @@ typedef struct {
     uint8_t chan;           /**< ADC channel */
 } adc_conf_t;
 
+#if defined(DAC0_BASE) && (DAC0_BASE != This_symbol_has_been_deprecated)
 /**
  * @brief   CPU specific DAC configuration
  */
@@ -249,6 +250,7 @@ typedef struct {
     volatile uint32_t *scgc_addr;   /**< Clock enable register, in SIM module */
     uint8_t scgc_bit;               /**< Clock enable bit, within the register */
 } dac_conf_t;
+#endif
 
 /**
  * @brief   CPU specific timer PIT module configuration