From 0b648f44d4c3fc51c4b26ea0f0c19be39f44b56d Mon Sep 17 00:00:00 2001 From: hugues Date: Fri, 17 Jul 2020 16:52:36 +0200 Subject: [PATCH] boards/nucleo-f746zg: Add dma, eth, pwm and spi features --- boards/nucleo-f746zg/Kconfig | 4 + boards/nucleo-f746zg/Makefile | 5 + boards/nucleo-f746zg/Makefile.dep | 4 + boards/nucleo-f746zg/Makefile.features | 4 + boards/nucleo-f746zg/include/periph_conf.h | 163 +++++++++++++++++++-- 5 files changed, 169 insertions(+), 11 deletions(-) diff --git a/boards/nucleo-f746zg/Kconfig b/boards/nucleo-f746zg/Kconfig index 2cce12ccde..2763e3f7f7 100644 --- a/boards/nucleo-f746zg/Kconfig +++ b/boards/nucleo-f746zg/Kconfig @@ -15,9 +15,13 @@ config BOARD_NUCLEO_F746ZG select CPU_MODEL_STM32F746ZG # Put defined MCU peripherals here (in alphabetical order) + select HAS_PERIPH_DMA + select HAS_PERIPH_ETH select HAS_PERIPH_I2C + select HAS_PERIPH_PWM select HAS_PERIPH_RTC select HAS_PERIPH_RTT + select HAS_PERIPH_SPI select HAS_PERIPH_TIMER select HAS_PERIPH_UART select HAS_PERIPH_USBDEV diff --git a/boards/nucleo-f746zg/Makefile b/boards/nucleo-f746zg/Makefile index 4dd17b1d0c..b32944c106 100644 --- a/boards/nucleo-f746zg/Makefile +++ b/boards/nucleo-f746zg/Makefile @@ -2,3 +2,8 @@ MODULE = board DIRS = $(RIOTBOARD)/common/nucleo include $(RIOTBASE)/Makefile.base + +ifneq (,$(filter stm32_eth,$(USEMODULE))) + $(info Remapping MOSI of SPI_DEV(0) from PA7 to PB5 to solve pin conflict.\ + (PA7 is also connected to the RMII_DV of the Ethernet Phy.)) +endif diff --git a/boards/nucleo-f746zg/Makefile.dep b/boards/nucleo-f746zg/Makefile.dep index 7294858272..3e965d26ad 100644 --- a/boards/nucleo-f746zg/Makefile.dep +++ b/boards/nucleo-f746zg/Makefile.dep @@ -1 +1,5 @@ +ifneq (,$(filter netdev_default,$(USEMODULE))) + USEMODULE += stm32_eth +endif + include $(RIOTBOARD)/common/nucleo/Makefile.dep diff --git a/boards/nucleo-f746zg/Makefile.features b/boards/nucleo-f746zg/Makefile.features index 6c8f3ab757..1eddc8d8c2 100644 --- a/boards/nucleo-f746zg/Makefile.features +++ b/boards/nucleo-f746zg/Makefile.features @@ -2,9 +2,13 @@ CPU = stm32 CPU_MODEL = stm32f746zg # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_dma +FEATURES_PROVIDED += periph_eth FEATURES_PROVIDED += periph_i2c +FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc FEATURES_PROVIDED += periph_rtt +FEATURES_PROVIDED += periph_spi FEATURES_PROVIDED += periph_timer FEATURES_PROVIDED += periph_uart FEATURES_PROVIDED += periph_usbdev diff --git a/boards/nucleo-f746zg/include/periph_conf.h b/boards/nucleo-f746zg/include/periph_conf.h index 860762daf9..09f1139135 100644 --- a/boards/nucleo-f746zg/include/periph_conf.h +++ b/boards/nucleo-f746zg/include/periph_conf.h @@ -30,6 +30,65 @@ extern "C" { #endif +/** + * @name DMA streams configuration + * @{ + */ +static const dma_conf_t dma_config[] = { + { .stream = 4 }, /* DMA1 Stream 4 - USART3_TX */ + { .stream = 14 }, /* DMA2 Stream 6 - USART6_TX */ + { .stream = 6 }, /* DMA1 Stream 6 - USART2_TX */ + { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */ + { .stream = 13 }, /* DMA2 Stream 5 - SPI1_TX */ + { .stream = 11 }, /* DMA2 Stream 3 - SPI4_RX */ + { .stream = 12 }, /* DMA2 Stream 4 - SPI4_TX */ + { .stream = 8 }, /* DMA2 Stream 0 - ETH_TX */ +}; + +#define DMA_0_ISR isr_dma1_stream4 +#define DMA_1_ISR isr_dma2_stream6 +#define DMA_2_ISR isr_dma1_stream6 + +#define DMA_3_ISR isr_dma2_stream2 +#define DMA_4_ISR isr_dma2_stream5 +#define DMA_5_ISR isr_dma2_stream3 +#define DMA_6_ISR isr_dma2_stream4 + +#define DMA_7_ISR isr_dma2_stream0 + +#define DMA_NUMOF ARRAY_SIZE(dma_config) +/** @} */ + +/** + * @name PWM configuration + * @{ + */ +static const pwm_conf_t pwm_config[] = { + { + .dev = TIM1, + .rcc_mask = RCC_APB2ENR_TIM1EN, + .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 CN10-4 */, .cc_chan = 0}, + { .pin = GPIO_PIN(PORT_E, 11) /* D5 CN10-6 */, .cc_chan = 1}, + { .pin = GPIO_PIN(PORT_E, 13) /* D3 CN10-10 */, .cc_chan = 2}, + { .pin = GPIO_PIN(PORT_E, 14) /* D38 CN10-28 */, .cc_chan = 3} }, + .af = GPIO_AF1, + .bus = APB2 + }, + { + .dev = TIM4, + .rcc_mask = RCC_APB1ENR_TIM4EN, + .chan = { { .pin = GPIO_PIN(PORT_D, 12) /* D29 CN10-21 */, .cc_chan = 0}, + { .pin = GPIO_PIN(PORT_D, 13) /* D28 CN10-19 */, .cc_chan = 1}, + { .pin = GPIO_PIN(PORT_D, 14) /* D10 CN7-16 */, .cc_chan = 2}, + { .pin = GPIO_PIN(PORT_D, 15) /* D9 CN7-18 */, .cc_chan = 3} }, + .af = GPIO_AF2, + .bus = APB1 + }, +}; + +#define PWM_NUMOF ARRAY_SIZE(pwm_config) +/** @} */ + /** * @name UART configuration * @{ @@ -44,9 +103,9 @@ static const uart_conf_t uart_config[] = { .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART3_IRQn, -#ifdef UART_USE_DMA - .dma_stream = 6, - .dma_chan = 4 +#ifdef MODULE_PERIPH_DMA + .dma = 0, + .dma_chan = 7 #endif }, { @@ -58,9 +117,9 @@ static const uart_conf_t uart_config[] = { .tx_af = GPIO_AF8, .bus = APB2, .irqn = USART6_IRQn, -#ifdef UART_USE_DMA - .dma_stream = 5, - .dma_chan = 4 +#ifdef MODULE_PERIPH_DMA + .dma = 1, + .dma_chan = 5 #endif }, { @@ -72,23 +131,105 @@ static const uart_conf_t uart_config[] = { .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART2_IRQn, -#ifdef UART_USE_DMA - .dma_stream = 4, +#ifdef MODULE_PERIPH_DMA + .dma = 2, .dma_chan = 4 #endif } }; #define UART_0_ISR (isr_usart3) -#define UART_0_DMA_ISR (isr_dma1_stream6) #define UART_1_ISR (isr_usart6) -#define UART_1_DMA_ISR (isr_dma1_stream5) #define UART_2_ISR (isr_usart2) -#define UART_2_DMA_ISR (isr_dma1_stream4) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ +/** + * @name SPI configuration + * @{ + */ +static const spi_conf_t spi_config[] = { + { + .dev = SPI1, + /* PA7 is the default MOSI pin, as it is required for compatibility with + * Arduino(ish) shields. Sadly, it is also connected to the RMII_DV of + * Ethernet PHY. We work around this by remapping the MOSI to PB5 when + * the on-board Ethernet PHY is used. + */ +#ifdef MODULE_PERIPH_ETH + .mosi_pin = GPIO_PIN(PORT_B, 5), +#else + .mosi_pin = GPIO_PIN(PORT_A, 7), +#endif + .miso_pin = GPIO_PIN(PORT_A, 6), + .sclk_pin = GPIO_PIN(PORT_A, 5), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI1EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 4, + .tx_dma_chan = 3, + .rx_dma = 3, + .rx_dma_chan = 3, +#endif + }, + { + .dev = SPI4, + .mosi_pin = GPIO_PIN(PORT_E, 6), + .miso_pin = GPIO_PIN(PORT_E, 5), + .sclk_pin = GPIO_PIN(PORT_E, 2), + .cs_pin = GPIO_UNDEF, + .mosi_af = GPIO_AF5, + .miso_af = GPIO_AF5, + .sclk_af = GPIO_AF5, + .cs_af = GPIO_AF5, + .rccmask = RCC_APB2ENR_SPI4EN, + .apbbus = APB2, +#ifdef MODULE_PERIPH_DMA + .tx_dma = 6, + .tx_dma_chan = 5, + .rx_dma = 5, + .rx_dma_chan = 5, +#endif + } +}; + +#define SPI_NUMOF ARRAY_SIZE(spi_config) +/** @} */ + +/** + * @name ETH configuration + * @{ + */ +static const eth_conf_t eth_config = { + .mode = RMII, + .mac = { 0 }, + .speed = ETH_SPEED_100TX_FD, + .dma = 7, + .dma_chan = 8, + .phy_addr = 0x01, + .pins = { + GPIO_PIN(PORT_G, 13), + GPIO_PIN(PORT_B, 13), + GPIO_PIN(PORT_G, 11), + GPIO_PIN(PORT_C, 4), + GPIO_PIN(PORT_C, 5), + GPIO_PIN(PORT_A, 7), + GPIO_PIN(PORT_C, 1), + GPIO_PIN(PORT_A, 2), + GPIO_PIN(PORT_A, 1), + } +}; + +#define ETH_DMA_ISR isr_dma2_stream0 + +/** @} */ + #ifdef __cplusplus } #endif