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Merge pull request #18636 from benpicco/cpu/cortexm.ld

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cpu: make use of `cortexm.ld`
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benpicco 2022-09-28 14:41:23 +02:00 committed by GitHub
commit 09fd98c0c6
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13 changed files with 43 additions and 149 deletions
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8
cpu/lm4f120/Makefile.include
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@ -1,3 +1,11 @@
ROM_LEN ?= 0x40000
RAM_LEN ?= 0x8000
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
LINKER_SCRIPT ?= cortexm.ld
include $(RIOTMAKE)/arch/cortexm.inc.mk
include $(RIOTCPU)/stellaris_common/Makefile.include

26
cpu/lm4f120/ldscripts/LM4F120H5QR.ld
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@ -1,26 +0,0 @@
/*
* Copyright (C) 2015 Rakendra Thapa <rakendrathapa@gmail.com
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_lm4f120
* @{
*
* @file lm4f120_linkerscript.ld
* @brief Linker description file for LM4FXXX microcontrollers.
*
* @author Rakendra Thapa <rakendrathapa@gmail.com>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
}
INCLUDE cortexm_base.ld

6
cpu/lpc1768/Makefile.include
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@ -1 +1,7 @@
ROM_START_ADDR ?= 0x0
RAM_START_ADDR ?= 0x100000C8
ROM_LEN ?= 0x80000
RAM_LEN ?= 0x7f38 # 32K - 0xC8
include $(RIOTMAKE)/arch/cortexm.inc.mk

4
cpu/lpc1768/ldscripts/lpc1768.ld
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@ -20,10 +20,8 @@
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
ram (w!rx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
usb_ram : ORIGIN = 0x2007C000, LENGTH = 16K
eth_ram : ORIGIN = 0x20080000, LENGTH = 16K
}
INCLUDE cortexm_base.ld
INCLUDE cortexm.ld

16
cpu/nrf51/Makefile.include
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@ -1,2 +1,18 @@
ROM_START_ADDR ?= 0
# Set ROM and RAM lengths according to CPU model
ifneq (,$(filter nrf51x22xxaa nrf51x22xxab,$(CPU_MODEL)))
ROM_LEN ?= 0x40000
RAM_LEN ?= 0x4000
endif
ifneq (,$(filter nrf51x22xxaa,$(CPU_MODEL)))
ROM_LEN ?= 0x20000
RAM_LEN ?= 0x4000
endif
ifneq (,$(filter nrf51x22xxac,$(CPU_MODEL)))
ROM_LEN ?= 0x40000
RAM_LEN ?= 0x8000
endif
include $(RIOTCPU)/nrf5x_common/Makefile.include
include $(RIOTMAKE)/arch/cortexm.inc.mk

27
cpu/nrf51/ldscripts/nrf51x22xxaa.ld
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@ -1,27 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_nrf51822
* @{
*
* @file
* @brief Memory definitions for the NRF51X22XXAA
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 16K
}
INCLUDE cortexm_base.ld

27
cpu/nrf51/ldscripts/nrf51x22xxab.ld
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@ -1,27 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_nrf51822
* @{
*
* @file
* @brief Memory definitions for the NRF51X22XXAB
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 128K
ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 16K
}
INCLUDE cortexm_base.ld

27
cpu/nrf51/ldscripts/nrf51x22xxac.ld
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@ -1,27 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_nrf51822
* @{
*
* @file
* @brief Memory definitions for the NRF51X22XXAC
*
* @author Stephane D'Alu <sdalu@sdalu.com>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
}
INCLUDE cortexm_base.ld

5
cpu/nrf52/Makefile.include
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@ -35,11 +35,6 @@ ifneq (,$(filter nrf52840xxaa,$(CPU_MODEL)))
RAM_LEN ?= 0x40000
endif
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
LINKER_SCRIPT ?= cortexm.ld
VECTORS_O ?= $(BINDIR)/nrf52_vectors/vectors_$(CPU_MODEL).o
include $(RIOTCPU)/nrf5x_common/Makefile.include

5
cpu/nrf5x_common/Makefile.include
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@ -1,3 +1,8 @@
CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
LINKER_SCRIPT ?= cortexm.ld
INCLUDES += -I$(RIOTCPU)/nrf5x_common/include

5
cpu/nrf9160/Makefile.include
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@ -2,11 +2,6 @@
ROM_LEN ?= 0x100000
RAM_LEN ?= 0x40000
ROM_START_ADDR ?= 0x00000000
RAM_START_ADDR ?= 0x20000000
LINKER_SCRIPT ?= cortexm.ld
FLASHFILE ?= $(BINFILE)
PROGRAMMER ?= jlink

9
cpu/sam_common/Makefile.include
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@ -4,7 +4,12 @@ CFLAGS += -DCPU_FAM_$(call uppercase_and_underscore,$(CPU_FAM))
# this CPU implementation doesn't use CMSIS initialization
CFLAGS += -DDONT_USE_CMSIS_INIT
# for the sam[drl] CPUs we hold all linkerscripts in the sam0 common folder
LINKFLAGS += -L$(RIOTCPU)/sam_common/ldscripts
ROM_START_ADDR ?= 0x80000
RAM_START_ADDR ?= 0x20070000
ROM_LEN ?= 0x80000
RAM_LEN ?= 0x18000
LINKER_SCRIPT ?= cortexm.ld
INCLUDES += -I$(RIOTCPU)/sam_common/include

27
cpu/sam_common/ldscripts/sam3x8e.ld
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@ -1,27 +0,0 @@
/*
* Copyright (C) 2015 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @addtogroup cpu_sam3
* @{
*
* @file
* @brief Memory definitions for the SAM3X8E
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*
* @}
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00080000, LENGTH = 512K
ram (w!rx) : ORIGIN = 0x20070000, LENGTH = 96K
}
INCLUDE cortexm_base.ld