From 07d76d71270af4fff599802a23229338ca4dea93 Mon Sep 17 00:00:00 2001 From: Thomas Eichinger Date: Wed, 1 Oct 2014 19:39:55 +0200 Subject: [PATCH] stm32l1: initial port for the nucleo-l1 board and stm32l1 cpu --- boards/nucleo-l1/Makefile | 3 + boards/nucleo-l1/Makefile.features | 2 + boards/nucleo-l1/Makefile.include | 56 + boards/nucleo-l1/board.c | 60 + boards/nucleo-l1/dist/debug-server.sh | 10 + boards/nucleo-l1/dist/debug.sh | 11 + boards/nucleo-l1/dist/flash.sh | 13 + boards/nucleo-l1/dist/gdb.conf | 1 + boards/nucleo-l1/dist/openocd.cfg | 6 + boards/nucleo-l1/dist/reset.sh | 10 + boards/nucleo-l1/include/board.h | 93 + boards/nucleo-l1/include/periph_conf.h | 292 + cpu/stm32l1/Makefile | 7 + cpu/stm32l1/Makefile.include | 25 + cpu/stm32l1/cpu.c | 91 + cpu/stm32l1/hwtimer_arch.c | 75 + cpu/stm32l1/include/cpu-conf.h | 79 + cpu/stm32l1/include/hwtimer_cpu.h | 41 + cpu/stm32l1/include/stm32l1xx.h | 6677 +++++++++++++++++++ cpu/stm32l1/lpm_arch.c | 53 + cpu/stm32l1/periph/Makefile | 5 + cpu/stm32l1/periph/cpuid.c | 31 + cpu/stm32l1/periph/gpio.c | 587 ++ cpu/stm32l1/periph/i2c.c | 543 ++ cpu/stm32l1/periph/spi.c | 257 + cpu/stm32l1/periph/timer.c | 409 ++ cpu/stm32l1/periph/uart.c | 328 + cpu/stm32l1/startup.c | 266 + cpu/stm32l1/stm32l152ret6_linkerscript.ld | 144 + cpu/stm32l1/syscalls.c | 347 + dist/tools/licenses/patterns/mcd-st-liberty | 1 + doc/doxygen/riot.doxyfile | 1 + 32 files changed, 10524 insertions(+) create mode 100644 boards/nucleo-l1/Makefile create mode 100644 boards/nucleo-l1/Makefile.features create mode 100644 boards/nucleo-l1/Makefile.include create mode 100644 boards/nucleo-l1/board.c create mode 100755 boards/nucleo-l1/dist/debug-server.sh create mode 100755 boards/nucleo-l1/dist/debug.sh create mode 100755 boards/nucleo-l1/dist/flash.sh create mode 100755 boards/nucleo-l1/dist/gdb.conf create mode 100644 boards/nucleo-l1/dist/openocd.cfg create mode 100755 boards/nucleo-l1/dist/reset.sh create mode 100644 boards/nucleo-l1/include/board.h create mode 100644 boards/nucleo-l1/include/periph_conf.h create mode 100644 cpu/stm32l1/Makefile create mode 100644 cpu/stm32l1/Makefile.include create mode 100644 cpu/stm32l1/cpu.c create mode 100644 cpu/stm32l1/hwtimer_arch.c create mode 100644 cpu/stm32l1/include/cpu-conf.h create mode 100644 cpu/stm32l1/include/hwtimer_cpu.h create mode 100644 cpu/stm32l1/include/stm32l1xx.h create mode 100644 cpu/stm32l1/lpm_arch.c create mode 100644 cpu/stm32l1/periph/Makefile create mode 100644 cpu/stm32l1/periph/cpuid.c create mode 100644 cpu/stm32l1/periph/gpio.c create mode 100644 cpu/stm32l1/periph/i2c.c create mode 100644 cpu/stm32l1/periph/spi.c create mode 100644 cpu/stm32l1/periph/timer.c create mode 100644 cpu/stm32l1/periph/uart.c create mode 100644 cpu/stm32l1/startup.c create mode 100644 cpu/stm32l1/stm32l152ret6_linkerscript.ld create mode 100644 cpu/stm32l1/syscalls.c create mode 100644 dist/tools/licenses/patterns/mcd-st-liberty diff --git a/boards/nucleo-l1/Makefile b/boards/nucleo-l1/Makefile new file mode 100644 index 0000000000..ff5489888b --- /dev/null +++ b/boards/nucleo-l1/Makefile @@ -0,0 +1,3 @@ +MODULE =$(BOARD)_base + +include $(RIOTBASE)/Makefile.base diff --git a/boards/nucleo-l1/Makefile.features b/boards/nucleo-l1/Makefile.features new file mode 100644 index 0000000000..67643f6de2 --- /dev/null +++ b/boards/nucleo-l1/Makefile.features @@ -0,0 +1,2 @@ +FEATURES_PROVIDED += periph_gpio periph_uart periph_spi periph_i2c periph_cpuid +FEATURES_PROVIDED += cpp diff --git a/boards/nucleo-l1/Makefile.include b/boards/nucleo-l1/Makefile.include new file mode 100644 index 0000000000..bb862ce782 --- /dev/null +++ b/boards/nucleo-l1/Makefile.include @@ -0,0 +1,56 @@ +## the cpu to build for +export CPU = stm32l1 +export CPU_MODEL = stm32l152ret6 + +#define the default port depending on the host OS +OS := $(shell uname) +ifeq ($(OS),Linux) + PORT ?= /dev/ttyACM0 +else ifeq ($(OS),Darwin) + PORT ?= $(shell ls -1 /dev/tty.SLAB_USBtoUART* | head -n 1) +else + $(info CAUTION: No flash tool for your host system found!) + # TODO: add support for windows as host platform +endif +export PORT + +# define tools used for building the project +export PREFIX = arm-none-eabi- +export CC = $(PREFIX)gcc +export CXX = $(PREFIX)g++ +export AR = $(PREFIX)ar +export AS = $(PREFIX)as +export LINK = $(PREFIX)gcc +export SIZE = $(PREFIX)size +export OBJCOPY = $(PREFIX)objcopy +export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm +export FLASHER = $(RIOTBOARD)/$(BOARD)/dist/flash.sh +export DEBUGGER = $(RIOTBOARD)/$(BOARD)/dist/debug.sh +export DEBUGSERVER = $(RIOTBOARD)/$(BOARD)/dist/debug-server.sh +export RESET = $(RIOTBOARD)/$(BOARD)/dist/reset.sh + +# unwanted (CXXUWFLAGS) and extra (CXXEXFLAGS) flags for c++ +export CXXUWFLAGS += +export CXXEXFLAGS += + +# define build specific options +export CPU_USAGE = -mcpu=cortex-m3 +export FPU_USAGE = +export CFLAGS += -ggdb -g3 -std=gnu99 -Os -Wall -Wstrict-prototypes $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -mthumb -mthumb-interwork -nostartfiles +export CFLAGS += -ffunction-sections -fdata-sections -fno-builtin +export ASFLAGS += -ggdb -g3 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian +export LINKFLAGS += -ggdb -g3 -std=gnu99 $(CPU_USAGE) $(FPU_USAGE) -mlittle-endian -static -lgcc -mthumb -mthumb-interwork -nostartfiles +# $(LINKERSCRIPT) is specified in cpu/Makefile.include +export LINKFLAGS += -T$(LINKERSCRIPT) +export OFLAGS = -O binary +export FFLAGS = $(HEXFILE) +export DEBUGGER_FLAGS = $(RIOTBOARD)/$(BOARD)/dist/gdb.conf $(ELFFILE) +export TERMFLAGS += -p "$(PORT)" + +# use the nano-specs of the NewLib when available +ifeq ($(shell $(LINK) -specs=nano.specs -E - 2>/dev/null >/dev/null + * + * @} + */ + +#include "board.h" +#include "cpu.h" + +static void leds_init(void); + +void board_init(void) +{ + /* initialize the CPU */ + cpu_init(); + + /* initialize the boards LEDs */ + leds_init(); +} + +/** + * @brief Initialize the boards on-board LEDs + * + * The LED initialization is hard-coded in this function. As the LED is soldered + * onto the board it is fixed to its CPU pins. + * + * The green LED is connected to pin PA5 + */ +static void leds_init(void) +{ + /* enable clock for port GPIOE */ + RCC->AHBENR |= RCC_AHBENR_GPIOAEN; + + /* set output speed to 50MHz */ + LED_GREEN_PORT->OSPEEDR |= 0x00000c00; + /* set output type to push-pull */ + LED_GREEN_PORT->OTYPER &= ~(0x00000020); + /* configure pins as general outputs */ + LED_GREEN_PORT->MODER &= ~(0x00000c00); + LED_GREEN_PORT->MODER |= 0x00000400; + /* disable pull resistors */ + LED_GREEN_PORT->PUPDR &= ~(0x00000c00); + + /* turn all LEDs off */ + LED_GREEN_PORT->BRR = 0x00c0; +} diff --git a/boards/nucleo-l1/dist/debug-server.sh b/boards/nucleo-l1/dist/debug-server.sh new file mode 100755 index 0000000000..e2aa6fa64d --- /dev/null +++ b/boards/nucleo-l1/dist/debug-server.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +echo "##" +echo "## Starting debug server" +echo "##" + +openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \ + -c "init" \ + -c "targets" \ + -c "reset halt" diff --git a/boards/nucleo-l1/dist/debug.sh b/boards/nucleo-l1/dist/debug.sh new file mode 100755 index 0000000000..350187969d --- /dev/null +++ b/boards/nucleo-l1/dist/debug.sh @@ -0,0 +1,11 @@ +#!/bin/sh + +if [ ! -f "$2" ]; then + echo "ELF-file $2 does not exist" + exit 1 +fi + +echo "##" +echo "## Debugging $2" +echo "##" +arm-none-eabi-gdb -tui -command="$1" $2 diff --git a/boards/nucleo-l1/dist/flash.sh b/boards/nucleo-l1/dist/flash.sh new file mode 100755 index 0000000000..f5a2fd48d9 --- /dev/null +++ b/boards/nucleo-l1/dist/flash.sh @@ -0,0 +1,13 @@ +#!/bin/bash + +echo "##" +echo "## Flashing $1" +echo "##" + +openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \ + -c "init" \ + -c "targets" \ + -c "reset halt" \ + -c "program $1 0x8000000 verify" \ + -c "reset run"\ + -c "shutdown" diff --git a/boards/nucleo-l1/dist/gdb.conf b/boards/nucleo-l1/dist/gdb.conf new file mode 100755 index 0000000000..ba7908fdf3 --- /dev/null +++ b/boards/nucleo-l1/dist/gdb.conf @@ -0,0 +1 @@ +tar extended-remote :3333 diff --git a/boards/nucleo-l1/dist/openocd.cfg b/boards/nucleo-l1/dist/openocd.cfg new file mode 100644 index 0000000000..a2348de15b --- /dev/null +++ b/boards/nucleo-l1/dist/openocd.cfg @@ -0,0 +1,6 @@ +# stml1 Target +source [find interface/stlink-v2-1.cfg] + +transport select hla_swd + +source [find target/stm32l.cfg] diff --git a/boards/nucleo-l1/dist/reset.sh b/boards/nucleo-l1/dist/reset.sh new file mode 100755 index 0000000000..92d4d74a09 --- /dev/null +++ b/boards/nucleo-l1/dist/reset.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +echo "##" +echo "## Resetting $1" +echo "##" + +openocd -f "${RIOTBOARD}/${BOARD}/dist/openocd.cfg" \ + -c "init" \ + -c "reset run"\ + -c "shutdown" diff --git a/boards/nucleo-l1/include/board.h b/boards/nucleo-l1/include/board.h new file mode 100644 index 0000000000..64f70ee5a6 --- /dev/null +++ b/boards/nucleo-l1/include/board.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup board_nucleo-l1 nucleo-l1 + * @ingroup boards + * @brief Board specific files for the nucleo-l1 board. + * @{ + * + * @file + * @brief Board specific definitions for the nucleo-l1 board. + * + * @author Thomas Eichinger + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include + +#include "cpu.h" +#include "periph_conf.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Define the nominal CPU core clock in this board + */ +#define F_CPU CLOCK_CORECLOCK + +/** + * @name Define the UART to be used as stdio and its baudrate + * @{ + */ +#define STDIO UART_0 +#define STDIO_BAUDRATE (115200U) +#define STDIO_RX_BUFSIZE (64U) +/** @} */ + +/** + * @name Assign the hardware timer + */ +#define HW_TIMER TIMER_0 + +/** + * @name LED pin definitions + * @{ + */ +#define LED_GREEN_PORT (GPIOA) +#define LED_GREEN_PIN (5) +/** @} */ + +/** + * @name Macros for controlling the on-board LEDs. + * @{ + */ +#define LED_RED_ON +#define LED_RED_OFF +#define LED_RED_TOGGLE + +#define LED_GREEN_ON (LED_GREEN_PORT->ODR &= ~(1<ODR |= (1<ODR ^= (1< + */ + +#ifndef __PERIPH_CONF_H +#define __PERIPH_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Clock system configuration + * @{ + **/ +#define CLOCK_HSI (16000000U) /* frequency of external oscillator */ +#define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */ +/* configuration of PLL prescaler and multiply values */ +/* CORECLOCK := HSI / PLL_HSI_DIV * PLL_HSI_MUL */ +#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLDIV2 +#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMUL4 +/* configuration of peripheral bus clock prescalers */ +#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ +#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ +#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ +/* configuration of flash access cycles */ +#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY +/** @} */ + +/** + * @brief Timer configuration + * @{ + */ +#define TIMER_NUMOF (2U) +#define TIMER_0_EN 1 +#define TIMER_1_EN 1 + +/* Timer 0 configuration */ +#define TIMER_0_DEV_0 TIM2 +#define TIMER_0_DEV_1 TIM3 +#define TIMER_0_CHANNELS 4 +#define TIMER_0_PRESCALER (32U) +#define TIMER_0_MAX_VALUE (0xffff) +#define TIMER_0_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM3EN)) +#define TIMER_0_ISR_0 isr_tim2 +#define TIMER_0_ISR_1 isr_tim3 +#define TIMER_0_IRQ_CHAN_0 TIM2_IRQn +#define TIMER_0_IRQ_CHAN_1 TIM3_IRQn +#define TIMER_0_IRQ_PRIO 1 +#define TIMER_0_TRIG_SEL TIM_SMCR_TS_0 + +/* Timer 1 configuration */ +#define TIMER_1_DEV_0 TIM4 +#define TIMER_1_DEV_1 TIM5 +#define TIMER_1_CHANNELS 4 +#define TIMER_1_PRESCALER (32U) +#define TIMER_1_MAX_VALUE (0xffff) +#define TIMER_1_CLKEN() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN | RCC_APB1ENR_TIM5EN)) +#define TIMER_1_ISR_0 isr_tim4 +#define TIMER_1_ISR_1 isr_tim5 +#define TIMER_1_IRQ_CHAN_0 TIM4_IRQn +#define TIMER_1_IRQ_CHAN_1 TIM5_IRQn +#define TIMER_1_IRQ_PRIO 1 +#define TIMER_1_TRIG_SEL TIM_SMCR_TS_1 +/** @} */ + +/** + * @brief UART configuration + */ +#define UART_NUMOF (1U) +#define UART_0_EN 1 +#define UART_IRQ_PRIO 1 + +/* UART 0 device configuration */ +#define UART_0_DEV USART2 +#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN) +#define UART_0_CLK (CLOCK_CORECLOCK) /* UART clock runs with 32MHz (F_CPU / 1) */ +#define UART_0_IRQ USART2_IRQn +#define UART_0_ISR isr_usart2 +#define UART_0_BUS_FREQ 32000000 +/* UART 0 pin configuration */ +#define UART_0_PORT GPIOA +#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define UART_0_RX_PIN 3 +#define UART_0_TX_PIN 2 +#define UART_0_AF 7 + +/** + * @brief GPIO configuration + */ +#define GPIO_NUMOF 16 +#define GPIO_0_EN 1 +#define GPIO_1_EN 1 +#define GPIO_2_EN 1 +#define GPIO_3_EN 1 +#define GPIO_4_EN 1 +#define GPIO_5_EN 1 +#define GPIO_6_EN 1 +#define GPIO_7_EN 1 +#define GPIO_8_EN 1 +#define GPIO_9_EN 1 +#define GPIO_10_EN 1 +#define GPIO_11_EN 1 +#define GPIO_12_EN 1 +#define GPIO_13_EN 1 +#define GPIO_14_EN 1 +#define GPIO_15_EN 1 +#define GPIO_IRQ_PRIO 1 + +/* IRQ config */ +#define GPIO_IRQ_0 GPIO_13 +#define GPIO_IRQ_1 GPIO_14 +#define GPIO_IRQ_2 GPIO_7 +#define GPIO_IRQ_3 GPIO_0 +#define GPIO_IRQ_4 GPIO_5 +#define GPIO_IRQ_5 GPIO_12 +#define GPIO_IRQ_6 GPIO_11 +#define GPIO_IRQ_7 GPIO_1 +#define GPIO_IRQ_8 GPIO_3 +#define GPIO_IRQ_9 GPIO_2 +#define GPIO_IRQ_10 GPIO_4 +#define GPIO_IRQ_11 GPIO_6 +#define GPIO_IRQ_12 GPIO_15 +#define GPIO_IRQ_13 GPIO_8 +#define GPIO_IRQ_14 GPIO_9 +#define GPIO_IRQ_15 GPIO_10 + +/* GPIO channel 0 config */ +#define GPIO_0_PORT GPIOA /* Used for user button 1 */ +#define GPIO_0_PIN 3 +#define GPIO_0_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_0_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI3_PA) +#define GPIO_0_IRQ EXTI3_IRQn +/* GPIO channel 1 config */ +#define GPIO_1_PORT GPIOC +#define GPIO_1_PIN 7 +#define GPIO_1_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN) +#define GPIO_1_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI7_PC) +#define GPIO_1_IRQ EXTI9_5_IRQn +/* GPIO channel 2 config */ +#define GPIO_2_PORT GPIOA +#define GPIO_2_PIN 9 +#define GPIO_2_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_2_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI9_PA) +#define GPIO_2_IRQ EXTI9_5_IRQn +/* GPIO channel 3 config */ +#define GPIO_3_PORT GPIOA +#define GPIO_3_PIN 8 +#define GPIO_3_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_3_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI8_PA) +#define GPIO_3_IRQ EXTI9_5_IRQn +/* GPIO channel 4 config */ +#define GPIO_4_PORT GPIOB +#define GPIO_4_PIN 10 +#define GPIO_4_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN) +#define GPIO_4_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI10_PB) +#define GPIO_4_IRQ EXTI15_10_IRQn +/* GPIO channel 5 config */ +#define GPIO_5_PORT GPIOB +#define GPIO_5_PIN 4 +#define GPIO_5_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN) +#define GPIO_5_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI4_PB) +#define GPIO_5_IRQ EXTI4_IRQn +/* GPIO channel 6 config */ +#define GPIO_6_PORT GPIOC +#define GPIO_6_PIN 11 +#define GPIO_6_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN) +#define GPIO_6_EXTI_CFG() (SYSCFG->EXTICR[2] |= SYSCFG_EXTICR3_EXTI11_PC) +#define GPIO_6_IRQ EXTI15_10_IRQn +/* GPIO channel 7 config */ +#define GPIO_7_PORT GPIOC +#define GPIO_7_PIN 2 +#define GPIO_7_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN) +#define GPIO_7_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI2_PC) +#define GPIO_7_IRQ EXTI2_IRQn +/* GPIO channel 8 config */ +#define GPIO_8_PORT GPIOA +#define GPIO_8_PIN 13 +#define GPIO_8_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_8_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI13_PA) +#define GPIO_8_IRQ EXTI15_10_IRQn +/* GPIO channel 9 config */ +#define GPIO_9_PORT GPIOA +#define GPIO_9_PIN 14 +#define GPIO_9_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_9_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI14_PA) +#define GPIO_9_IRQ EXTI15_10_IRQn +/* GPIO channel 10 config */ +#define GPIO_10_PORT GPIOA +#define GPIO_10_PIN 15 +#define GPIO_10_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_10_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI15_PA) +#define GPIO_10_IRQ EXTI15_10_IRQn +/* GPIO channel 11 config */ +#define GPIO_11_PORT GPIOB /* SPI CS Pin */ +#define GPIO_11_PIN 6 +#define GPIO_11_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN) +#define GPIO_11_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI6_PB) +#define GPIO_11_IRQ EXTI9_5_IRQn +/* GPIO channel 12 config */ +#define GPIO_12_PORT GPIOC +#define GPIO_12_PIN 5 +#define GPIO_12_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN) +#define GPIO_12_EXTI_CFG() (SYSCFG->EXTICR[1] |= SYSCFG_EXTICR2_EXTI5_PC) +#define GPIO_12_IRQ EXTI9_5_IRQn +/* GPIO channel 13 config */ +#define GPIO_13_PORT GPIOA +#define GPIO_13_PIN 0 +#define GPIO_13_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_13_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI0_PA) +#define GPIO_13_IRQ EXTI0_IRQn +/* GPIO channel 14 config */ +#define GPIO_14_PORT GPIOA +#define GPIO_14_PIN 1 +#define GPIO_14_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define GPIO_14_EXTI_CFG() (SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PA) +#define GPIO_14_IRQ EXTI1_IRQn +/* GPIO channel 15 config */ +#define GPIO_15_PORT GPIOC +#define GPIO_15_PIN 12 +#define GPIO_15_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOCEN) +#define GPIO_15_EXTI_CFG() (SYSCFG->EXTICR[3] |= SYSCFG_EXTICR4_EXTI12_PC) +#define GPIO_15_IRQ EXTI15_10_IRQn + +/** + * @brief SPI configuration + * @{ + */ +#define SPI_NUMOF (1U) +#define SPI_0_EN 1 + +/* SPI 0 device configuration */ +#define SPI_0_DEV SPI1 +#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN) +#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define SPI_0_IRQ SPI1_IRQn +#define SPI_0_ISR isr_spi1 +/* SPI 0 pin configuration */ +#define SPI_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN) +#define SPI_0_PORT GPIOA +#define SPI_0_PIN_SCK 5 +#define SPI_0_PIN_MOSI 7 +#define SPI_0_PIN_MISO 6 +#define SPI_0_PIN_AF 5 +/** @} */ + +/** + * @name I2C configuration + * @{ + */ +#define I2C_NUMOF (1U) +#define I2C_0_EN 1 +#define I2C_IRQ_PRIO 1 +#define I2C_APBCLK (36000000U) + +/* I2C 0 device configuration */ +#define I2C_0_DEV I2C1 +#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN) +#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define I2C_0_EVT_IRQ I2C1_EV_IRQn +#define I2C_0_EVT_ISR isr_i2c1_ev +#define I2C_0_ERR_IRQ I2C1_ER_IRQn +#define I2C_0_ERR_ISR isr_i2c1_er +/* I2C 0 pin configuration */ +#define I2C_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOBEN) +#define I2C_0_PORT GPIOB +#define I2C_0_SCL_PIN 8 +#define I2C_0_SCL_AF 4 +#define I2C_0_SDA_PIN 9 +#define I2C_0_SDA_AF 4 +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PERIPH_CONF_H */ +/** @} */ diff --git a/cpu/stm32l1/Makefile b/cpu/stm32l1/Makefile new file mode 100644 index 0000000000..f89e766bdf --- /dev/null +++ b/cpu/stm32l1/Makefile @@ -0,0 +1,7 @@ +# define the module that is build +MODULE =cpu + +# add a list of subdirectories, that should also be build +DIRS += periph $(CORTEXM_COMMON) + +include $(RIOTBASE)/Makefile.base diff --git a/cpu/stm32l1/Makefile.include b/cpu/stm32l1/Makefile.include new file mode 100644 index 0000000000..daff441b21 --- /dev/null +++ b/cpu/stm32l1/Makefile.include @@ -0,0 +1,25 @@ +# this CPU implementation is using the new core/CPU interface +export CFLAGS += -DCOREIF_NG=1 + +# tell the build system that the CPU depends on the Cortex-M common files +export USEMODULE += cortex-m3_common + +# define path to cortex-m common module, which is needed for this CPU +export CORTEXM_COMMON = $(RIOTCPU)/cortex-m3_common/ + +# define the linker script to use for this CPU +export LINKERSCRIPT = $(RIOTCPU)/$(CPU)/$(CPU_MODEL)_linkerscript.ld + +# include CPU specific includes +export INCLUDES += -I$(RIOTCPU)/$(CPU)/include + +# explicitly tell the linker to link the syscalls and startup code. +# Without this the interrupt vectors will not be linked correctly! +export UNDEF += $(BINDIR)cpu/syscalls.o +export UNDEF += $(BINDIR)cpu/startup.o + +# export the peripheral drivers to be linked into the final binary +export USEMODULE += periph + +# CPU depends on the cortex-m common module, so include it +include $(CORTEXM_COMMON)Makefile.include diff --git a/cpu/stm32l1/cpu.c b/cpu/stm32l1/cpu.c new file mode 100644 index 0000000000..6ca8a82dc0 --- /dev/null +++ b/cpu/stm32l1/cpu.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32l1 + * @{ + * + * @file cpu.c + * @brief Implementation of the kernel cpu functions + * + * @author Thomas Eichinger + * + * @} + */ + +#include "cpu.h" +#include "board.h" +#include "periph_conf.h" + +static void clk_init(void); + +void cpu_init(void) +{ + /* set PendSV priority to the lowest possible priority */ + NVIC_SetPriority(PendSV_IRQn, 0xff); + + /* initialize system clocks */ + clk_init(); + + /* configure the vector table location to internal flash */ + SCB->VTOR = FLASH_BASE; +} + +/** + * @brief Configure the clock system of the stm32f1 + * + */ +static void clk_init(void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */ + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL); + /* Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON); + /* Disable all interruptss */ + RCC->CIR = 0x0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */ + /* Enable HSE */ + RCC->CR |= RCC_CR_HSION; + /* Wait till HSE is ready, + * NOTE: the MCU will stay here forever if no HSE clock is connected */ + while (!(RCC->CR & RCC_CR_HSIRDY)); + FLASH->ACR |= FLASH_ACR_ACC64; + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + /* Flash 1 wait state */ + FLASH->ACR |= CLOCK_FLASH_LATENCY; + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != 0); + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV; + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV; + /* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */ + RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLDIV | RCC_CFGR_PLLMUL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL); + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + /* Wait till PLL is ready */ + while ((RCC->CR & RCC_CR_PLLRDY) == 0); + /* Select PLL as system clock source */ + RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); +} diff --git a/cpu/stm32l1/hwtimer_arch.c b/cpu/stm32l1/hwtimer_arch.c new file mode 100644 index 0000000000..e8d58d6316 --- /dev/null +++ b/cpu/stm32l1/hwtimer_arch.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32l1 + * @{ + * + * @file hwtimer_arch.c + * @brief Implementation of the kernels hwtimer interface + * + * The hardware timer implementation uses the Cortex build-in system timer as backend. + * + * @author Thomas Eichinger + * + * @} + */ + +#include "arch/hwtimer_arch.h" +#include "thread.h" +#include "board.h" +#include "periph/timer.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + + +void irq_handler(int channel); +void (*timeout_handler)(int); + + +void hwtimer_arch_init(void (*handler)(int), uint32_t fcpu) +{ + timeout_handler = handler; + timer_init(HW_TIMER, 1, &irq_handler); +} + +void hwtimer_arch_enable_interrupt(void) +{ + timer_irq_enable(HW_TIMER); +} + +void hwtimer_arch_disable_interrupt(void) +{ + timer_irq_disable(HW_TIMER); +} + +void hwtimer_arch_set(unsigned long offset, short timer) +{ + timer_set(HW_TIMER, timer, offset); +} + +void hwtimer_arch_set_absolute(unsigned long value, short timer) +{ + timer_set_absolute(HW_TIMER, timer, value); +} + +void hwtimer_arch_unset(short timer) +{ + timer_clear(HW_TIMER, timer); +} + +unsigned long hwtimer_arch_now(void) +{ + return timer_read(HW_TIMER); +} + +void irq_handler(int channel) +{ + timeout_handler((short)channel); +} diff --git a/cpu/stm32l1/include/cpu-conf.h b/cpu/stm32l1/include/cpu-conf.h new file mode 100644 index 0000000000..5e9b6b8f1c --- /dev/null +++ b/cpu/stm32l1/include/cpu-conf.h @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @defgroup cpu_stm32l1 stm32l1 + * @addtogroup cpu + * @brief CPU specific implementations for the STM32F1 + * @{ + * + * @file + * @brief Implementation specific CPU configuration options + * + * @author Thomas Eichinger + */ + +#ifndef CPUCONF_H_ +#define CPUCONF_H_ + +#include "stm32l1xx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Kernel configuration + * + * @{ + */ +#define KERNEL_CONF_STACKSIZE_PRINTF (1024) + +#ifndef KERNEL_CONF_STACKSIZE_DEFAULT +#define KERNEL_CONF_STACKSIZE_DEFAULT (1024) +#endif + +#define KERNEL_CONF_STACKSIZE_IDLE (256) +/** @} */ + +/** + * @name UART0 buffer size definition for compatibility reasons + * + * TODO: remove once the remodeling of the uart0 driver is done + * @{ + */ +#ifndef UART0_BUFSIZE +#define UART0_BUFSIZE (128) +#endif +/** @} */ + +/** + * @name Length for reading CPU_ID + */ +#define CPUID_ID_LEN (12) + +/** + * @name Definition of different panic modes + */ +typedef enum { + HARD_FAULT, + WATCHDOG, + BUS_FAULT, + USAGE_FAULT, + DUMMY_HANDLER +} panic_t; + +#define TRANSCEIVER_BUFFER_SIZE (3) + +#ifdef __cplusplus +} +#endif + +#endif /* __CPU_CONF_H */ +/** @} */ +/** @} */ diff --git a/cpu/stm32l1/include/hwtimer_cpu.h b/cpu/stm32l1/include/hwtimer_cpu.h new file mode 100644 index 0000000000..072f26e959 --- /dev/null +++ b/cpu/stm32l1/include/hwtimer_cpu.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32l1 + * @{ + * + * @file + * @brief CPU specific hwtimer configuration options + * + * @author Thomas Eichinger + */ + +#ifndef HWTIMER_CPU_H_ +#define HWTIMER_CPU_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @name Hardware timer configuration + * @{ + */ +#define HWTIMER_MAXTIMERS (4) /**< the CPU implementation supports 4 HW timers */ +#define HWTIMER_SPEED (1000000U) /**< the HW timer runs with 1MHz */ +#define HWTIMER_MAXTICKS (0xFFFFFFFF) /**< 32-bit timer */ +#define HWTIMER_WAIT_OVERHEAD (3) +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* HWTIMER_CPU_H_ */ +/** @} */ diff --git a/cpu/stm32l1/include/stm32l1xx.h b/cpu/stm32l1/include/stm32l1xx.h new file mode 100644 index 0000000000..1ffc15f346 --- /dev/null +++ b/cpu/stm32l1/include/stm32l1xx.h @@ -0,0 +1,6677 @@ +/** + ****************************************************************************** + * @file stm32l1xx.h + * @author MCD Application Team + * @version V1.3.2 + * @date 10-April-2014 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32L1xx High-density, Medium-density, + * Medium-density and XL-density Plus devices. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The device used in the target application + * - To use or not the peripheralís drivers in application code(i.e. + * code will be based on direct access to peripheralís registers + * rather than drivers API), this option is controlled by + * "#define USE_STDPERIPH_DRIVER" + * - To change few application-specific parameters such as the HSE + * crystal frequency + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheralís registers hardware + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup cpu_specific_stm32l1xx + * @{ + */ + +#ifndef __STM32L1XX_H +#define __STM32L1XX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup cpu_specific_Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32L device used in your + application + */ + +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL) + +/* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx, + STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx, + STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA, + STM32L152x8xxA and STM32L152xBxxA. + - Ultra Low Power Medium-density Value Line devices: STM32L100x6xx, + STM32L100x8xx and STM32L100xBxx. */ + +/* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx + - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */ + +/* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */ + +/* #define STM32L1XX_XL */ /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#define STM32L1XX_XL (1U) +#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL) + #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" +#endif + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +#endif + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */ +#endif + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */ +#endif + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif + +/** + * @brief STM32L1xx Standard Peripheral Library version number V1.3.2 + */ +#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */ +#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__STM32L1XX_STDPERIPH_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief STM32L1xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */ +#define __MPU_PRESENT 1 /*!< STM32L1 provides MPU */ +#define __NVIC_PRIO_BITS 4 /*!< STM32L1 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*!< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32L specific Interrupt Numbers ***********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ + USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ + DAC_IRQn = 21, /*!< DAC Interrupt */ + COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + LCD_IRQn = 24, /*!< LCD Interrupt */ + TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ + TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ + TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ + TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ + +#ifdef STM32L1XX_MD + TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ +#endif /* STM32L1XX_MD */ + +#ifdef STM32L1XX_MDP + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif /* STM32L1XX_MDP */ + +#ifdef STM32L1XX_HD + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + SDIO_IRQn = 45, /*!< SDIO global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif /* STM32L1XX_HD */ + +#ifdef STM32L1XX_XL + TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ + TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ + UART4_IRQn = 48, /*!< UART4 global Interrupt */ + UART5_IRQn = 49, /*!< UART5 global Interrupt */ + DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ + AES_IRQn = 55, /*!< AES global Interrupt */ + COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ +#endif /* STM32L1XX_XL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +// #include "system_stm32l1xx.h" +#include + +/** @addtogroup cpu_specific_Exported_types + * @{ + */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) +/* ARM Compiler + ------------ + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ + #define __RAM_FUNC FLASH_Status + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ + #define __RAM_FUNC __ramfunc FLASH_Status + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ + #define __RAM_FUNC FLASH_Status __attribute__((section(".RamFunc"))) + +#elif defined ( __TASKING__ ) +/* TASKING Compiler + ---------------- + RAM functions are defined using a specific toolchain pragma. This pragma is + defined in the stm32l1xx_flash_ramfunc.c +*/ + #define __RAM_FUNC FLASH_Status + +#endif + +/** + * @} + */ + +/** @addtogroup cpu_specific_Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ + __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ + __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ +} ADC_Common_TypeDef; + + +/** + * @brief AES hardware accelerator + */ + +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ +} AES_TypeDef; + +/** + * @brief Comparator + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ + __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ + __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ + __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ + __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ + __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ + __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */ + __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ + uint32_t RESERVED[23]; /*!< Reserved, 0x24 */ + __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */ + __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ + __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ + __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */ + __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */ + __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */ + __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */ + __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */ + __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */ +} OB_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FSMC_Bank1E_TypeDef; + +/** + * @brief General Purpose IO + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + uint16_t RESERVED0; /*!< Reserved, 0x06 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + uint16_t RESERVED1; /*!< Reserved, 0x12 */ + __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + uint16_t RESERVED2; /*!< Reserved, 0x16 */ + __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */ + __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */ +#if defined (STM32L1XX_HD) || defined (STM32L1XX_XL) + __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ + uint16_t RESERVED3; /*!< Reserved, 0x2A */ +#endif +} GPIO_TypeDef; + +/** + * @brief SysTem Configuration + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + + +/** + * @brief LCD + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ + __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ + __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ +} LCD_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ + __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ + __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ + __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ +} RCC_TypeDef; + +/** + * @brief Routing Interface + */ + +typedef struct +{ + __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */ + __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */ + __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */ + __IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */ + __IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */ + __IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */ + __IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */ + __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */ + __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */ + __IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */ + __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */ + __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */ + __IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */ + __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */ + __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */ + __IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */ + __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */ + __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */ + __IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */ + __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */ + __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */ + __IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */ +} RI_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved, 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ + __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + uint16_t RESERVED7; /*!< Reserved, 0x1E */ + __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + uint16_t RESERVED8; /*!< Reserved, 0x22 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + uint16_t RESERVED10; /*!< Reserved, 0x2A */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + uint32_t RESERVED12; /*!< Reserved, 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + uint32_t RESERVED17; /*!< Reserved, 0x44 */ + __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + uint16_t RESERVED18; /*!< Reserved, 0x4A */ + __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + uint16_t RESERVED19; /*!< Reserved, 0x4E */ + __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ + uint16_t RESERVED20; /*!< Reserved, 0x52 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ + uint16_t RESERVED0; /*!< Reserved, 0x02 */ + __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + uint16_t RESERVED2; /*!< Reserved, 0x0A */ + __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + uint16_t RESERVED3; /*!< Reserved, 0x0E */ + __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + uint16_t RESERVED4; /*!< Reserved, 0x12 */ + __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + uint16_t RESERVED5; /*!< Reserved, 0x16 */ + __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ + uint16_t RESERVED6; /*!< Reserved, 0x1A */ +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup cpu_specific_Peripheral_memory_map + * @{ + */ + +#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ + +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define LCD_BASE (APB1PERIPH_BASE + 0x2400) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) +#define RI_BASE (APB1PERIPH_BASE + 0x7C04) +#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) + +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) +#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) +#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC_BASE (APB2PERIPH_BASE + 0x2700) +#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) + +#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define RCC_BASE (AHBPERIPH_BASE + 0x3800) + + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ +#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ + +#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) + +#define DMA2_BASE (AHBPERIPH_BASE + 0x6400) +#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) +#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) +#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) +#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) +#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) + +#define AES_BASE ((uint32_t)0x50060000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup cpu_specific_Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define COMP ((COMP_TypeDef *) COMP_BASE) +#define RI ((RI_TypeDef *) RI_BASE) +#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) + +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) + +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) + +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) + +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) + +#define AES ((AES_TypeDef *) AES_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup cpu_specific_Exported_constants + * @{ + */ + +/** @addtogroup cpu_specific_Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for ADC_SR register ********************/ +#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ +#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ +#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ +#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ +#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ +#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ +#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ +#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ +#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ + +/******************* Bit definition for ADC_CR1 register ********************/ +#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ +#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ +#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ +#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ +#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ +#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ +#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ +#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ + +#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ +#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ + +#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ +#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ + +#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ +#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ + +#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ +#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ + +/******************* Bit definition for ADC_CR2 register ********************/ +#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ +#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ +#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */ + +#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ +#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + +#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ +#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ +#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ +#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ + +#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ +#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ +#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ + +#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ +#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ + +#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ +#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + +#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ +#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ + +/****************** Bit definition for ADC_SMPR1 register *******************/ +#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ +#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ +#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ +#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ +#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ +#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ +#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */ +#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */ +#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */ +#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */ +#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR2 register *******************/ +#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ +#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ +#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_SMPR3 register *******************/ +#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ +#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ +#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ +#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ +#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ +#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ + +/****************** Bit definition for ADC_JOFR1 register *******************/ +#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_JOFR2 register *******************/ +#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_JOFR3 register *******************/ +#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_JOFR4 register *******************/ +#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_HTR register ********************/ +#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ + +/******************* Bit definition for ADC_LTR register ********************/ +#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ + +/******************* Bit definition for ADC_SQR1 register *******************/ +#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ +#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ + +#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ +#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ +#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ +#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR2 register *******************/ +#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ +#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ +#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ +#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ +#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ +#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ +#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR3 register *******************/ +#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ +#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ +#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR4 register *******************/ +#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + +/******************* Bit definition for ADC_SQR5 register *******************/ +#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ +#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ +#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ +#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ + +#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ +#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ +#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ +#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ +#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ + + +/******************* Bit definition for ADC_JSQR register *******************/ +#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ +#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ +#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ +#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ +#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ +#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ +#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ + +#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ +#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ +#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ +#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ +#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ + +#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ +#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +/******************* Bit definition for ADC_JDR1 register *******************/ +#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR2 register *******************/ +#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR3 register *******************/ +#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************* Bit definition for ADC_JDR4 register *******************/ +#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ + +/****************** Bit definition for ADC_SMPR0 register *******************/ +#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */ +#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */ +#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + +#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */ +#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */ +#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */ + +/******************* Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ +#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ +#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ +#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ +#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ +#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ +#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ + +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ +#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ +#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ + +/******************************************************************************/ +/* */ +/* Advanced Encryption Standard (AES) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for AES_CR register *********************/ +#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */ +#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */ +#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */ +#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */ + +#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */ +#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */ +#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */ + +#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */ +#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */ +#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */ + +#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */ +#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */ +#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */ +#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */ +#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */ +#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */ + +/******************* Bit definition for AES_SR register *********************/ +#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */ +#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */ +#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */ + +/******************* Bit definition for AES_DINR register *******************/ +#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */ + +/******************* Bit definition for AES_DOUTR register ******************/ +#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */ + +/******************* Bit definition for AES_KEYR0 register ******************/ +#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */ + +/******************* Bit definition for AES_KEYR1 register ******************/ +#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */ + +/******************* Bit definition for AES_KEYR2 register ******************/ +#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */ + +/******************* Bit definition for AES_KEYR3 register ******************/ +#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */ + +/******************* Bit definition for AES_IVR0 register *******************/ +#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */ + +/******************* Bit definition for AES_IVR1 register *******************/ +#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */ + +/******************* Bit definition for AES_IVR2 register *******************/ +#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */ + +/******************* Bit definition for AES_IVR3 register *******************/ +#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for COMP_CSR register ********************/ +#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ +#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ +#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ +#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ + +#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ +#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */ +#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ + +#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ +#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ + +#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ +#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ + +#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ +#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ + +#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ +#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ +#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ +#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ + +#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */ +#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */ +#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */ + +#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */ +#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */ +#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for OPAMP_CSR register ******************/ +#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */ +#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */ +#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */ +#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */ +#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */ +#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */ +#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */ +#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */ +#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */ +#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */ +#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */ +#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */ +#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */ +#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */ +#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */ +#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */ +#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */ +#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */ +#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */ +#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */ +#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */ +#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */ +#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */ +#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */ +#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */ +#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */ +#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */ +#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */ + +/******************* Bit definition for OPAMP_OTR register ******************/ +#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */ +#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */ +#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */ + +/******************* Bit definition for OPAMP_LPOTR register ****************/ +#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */ +#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */ +#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter (DAC) */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1 ((uint32_t)0x00000001) /*! + * + * @} + */ + +#include "arch/lpm_arch.h" + +void lpm_arch_init(void) +{ + /* TODO */ +} + +enum lpm_mode lpm_arch_set(enum lpm_mode target) +{ + /* TODO */ + return 0; +} + +enum lpm_mode lpm_arch_get(void) +{ + /* TODO */ + return 0; +} + +void lpm_arch_awake(void) +{ + /* TODO */ +} + +void lpm_arch_begin_awake(void) +{ + /* TODO */ +} + +void lpm_arch_end_awake(void) +{ + /* TODO */ +} diff --git a/cpu/stm32l1/periph/Makefile b/cpu/stm32l1/periph/Makefile new file mode 100644 index 0000000000..1be36f440e --- /dev/null +++ b/cpu/stm32l1/periph/Makefile @@ -0,0 +1,5 @@ +# define the module name +MODULE = periph + +# include RIOTs generic Makefile +include $(RIOTBASE)/Makefile.base diff --git a/cpu/stm32l1/periph/cpuid.c b/cpu/stm32l1/periph/cpuid.c new file mode 100644 index 0000000000..f8443b9cfa --- /dev/null +++ b/cpu/stm32l1/periph/cpuid.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014 FU Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file cpuid.c + * @brief Low-level CPUID driver implementation + * + * @author Thomas Eichinger + */ + +#include +#include "cpu-conf.h" + +#include "periph/cpuid.h" + +#define STM32L1_CPUID_ADDR (0x1ff800d0) + +void cpuid_get(void *id) +{ + memcpy(id, (void *)(STM32L1_CPUID_ADDR), CPUID_ID_LEN); +} + +/** @} */ diff --git a/cpu/stm32l1/periph/gpio.c b/cpu/stm32l1/periph/gpio.c new file mode 100644 index 0000000000..39d29743a3 --- /dev/null +++ b/cpu/stm32l1/periph/gpio.c @@ -0,0 +1,587 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file + * @brief Low-level GPIO driver implementation + * + * @author Thomas Eichinger + * + * @} + */ + +#include "cpu.h" +#include "sched.h" +#include "thread.h" +#include "periph/gpio.h" +#include "periph_conf.h" + +/* guard file in case no GPIO devices are defined */ +#if GPIO_NUMOF + +typedef struct { + gpio_cb_t cb; + void *arg; +} gpio_state_t; + +static gpio_state_t gpio_config[GPIO_NUMOF]; + +/* static port mappings */ +static GPIO_TypeDef *const gpio_port_map[GPIO_NUMOF] = { +#if GPIO_0_EN + [GPIO_0] = GPIO_0_PORT, +#endif +#if GPIO_1_EN + [GPIO_1] = GPIO_1_PORT, +#endif +#if GPIO_2_EN + [GPIO_2] = GPIO_2_PORT, +#endif +#if GPIO_3_EN + [GPIO_3] = GPIO_3_PORT, +#endif +#if GPIO_4_EN + [GPIO_4] = GPIO_4_PORT, +#endif +#if GPIO_5_EN + [GPIO_5] = GPIO_5_PORT, +#endif +#if GPIO_6_EN + [GPIO_6] = GPIO_6_PORT, +#endif +#if GPIO_7_EN + [GPIO_7] = GPIO_7_PORT, +#endif +#if GPIO_8_EN + [GPIO_8] = GPIO_8_PORT, +#endif +#if GPIO_9_EN + [GPIO_9] = GPIO_9_PORT, +#endif +#if GPIO_10_EN + [GPIO_10] = GPIO_10_PORT, +#endif +#if GPIO_11_EN + [GPIO_11] = GPIO_11_PORT, +#endif +#if GPIO_12_EN + [GPIO_12] = GPIO_12_PORT, +#endif +#if GPIO_13_EN + [GPIO_13] = GPIO_13_PORT, +#endif +#if GPIO_14_EN + [GPIO_14] = GPIO_14_PORT, +#endif +#if GPIO_15_EN + [GPIO_15] = GPIO_15_PORT, +#endif +}; + +/* static pin mappings */ +static const uint8_t gpio_pin_map[GPIO_NUMOF] = { +#if GPIO_0_EN + [GPIO_0] = GPIO_0_PIN, +#endif +#if GPIO_1_EN + [GPIO_1] = GPIO_1_PIN, +#endif +#if GPIO_2_EN + [GPIO_2] = GPIO_2_PIN, +#endif +#if GPIO_3_EN + [GPIO_3] = GPIO_3_PIN, +#endif +#if GPIO_4_EN + [GPIO_4] = GPIO_4_PIN, +#endif +#if GPIO_5_EN + [GPIO_5] = GPIO_5_PIN, +#endif +#if GPIO_6_EN + [GPIO_6] = GPIO_6_PIN, +#endif +#if GPIO_7_EN + [GPIO_7] = GPIO_7_PIN, +#endif +#if GPIO_8_EN + [GPIO_8] = GPIO_8_PIN, +#endif +#if GPIO_9_EN + [GPIO_9] = GPIO_9_PIN, +#endif +#if GPIO_10_EN + [GPIO_10] = GPIO_10_PIN, +#endif +#if GPIO_11_EN + [GPIO_11] = GPIO_11_PIN, +#endif +#if GPIO_12_EN + [GPIO_12] = GPIO_12_PIN, +#endif +#if GPIO_13_EN + [GPIO_13] = GPIO_13_PIN, +#endif +#if GPIO_14_EN + [GPIO_14] = GPIO_14_PIN, +#endif +#if GPIO_15_EN + [GPIO_15] = GPIO_15_PIN, +#endif +}; + +/* static irq mappings */ +static const IRQn_Type gpio_irq_map[GPIO_NUMOF] = { +#if GPIO_0_EN + [GPIO_0] = GPIO_0_IRQ, +#endif +#if GPIO_1_EN + [GPIO_1] = GPIO_1_IRQ, +#endif +#if GPIO_2_EN + [GPIO_2] = GPIO_2_IRQ, +#endif +#if GPIO_3_EN + [GPIO_3] = GPIO_3_IRQ, +#endif +#if GPIO_4_EN + [GPIO_4] = GPIO_4_IRQ, +#endif +#if GPIO_5_EN + [GPIO_5] = GPIO_5_IRQ, +#endif +#if GPIO_6_EN + [GPIO_6] = GPIO_6_IRQ, +#endif +#if GPIO_7_EN + [GPIO_7] = GPIO_7_IRQ, +#endif +#if GPIO_8_EN + [GPIO_8] = GPIO_8_IRQ, +#endif +#if GPIO_9_EN + [GPIO_9] = GPIO_9_IRQ, +#endif +#if GPIO_10_EN + [GPIO_10] = GPIO_10_IRQ, +#endif +#if GPIO_11_EN + [GPIO_11] = GPIO_11_IRQ, +#endif +#if GPIO_12_EN + [GPIO_12] = GPIO_12_IRQ, +#endif +#if GPIO_13_EN + [GPIO_13] = GPIO_13_IRQ, +#endif +#if GPIO_14_EN + [GPIO_14] = GPIO_14_IRQ, +#endif +#if GPIO_15_EN + [GPIO_15] = GPIO_15_IRQ, +#endif +}; + +int gpio_init_out(gpio_t dev, gpio_pp_t pullup) +{ + GPIO_TypeDef *port; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return -1; + } + + port = gpio_port_map[dev]; + pin = gpio_pin_map[dev]; + + port->MODER &= ~(2 << (2 * pin)); /* set pin to output mode */ + port->MODER |= (1 << (2 * pin)); + port->OTYPER &= ~(1 << pin); /* set to push-pull configuration */ + port->OSPEEDR |= (3 << (2 * pin)); /* set to high speed */ + port->PUPDR &= ~(3 << (2 * pin)); /* configure push-pull resistors */ + port->PUPDR |= (pullup << (2 * pin)); + port->ODR &= ~(1 << pin); /* set pin to low signal */ + + return 0; /* all OK */ +} + +int gpio_init_in(gpio_t dev, gpio_pp_t pullup) +{ + GPIO_TypeDef *port; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return -1; + } + + port = gpio_port_map[dev]; + pin = gpio_pin_map[dev]; + + port->MODER &= ~(3 << (2 * pin)); /* configure pin as input */ + port->PUPDR &= ~(3 << (2 * pin)); /* configure push-pull resistors */ + port->PUPDR |= (pullup << (2 * pin)); + + return 0; /* everything alright here */ +} + +int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg) +{ + int res; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return -1; + } + + pin = gpio_pin_map[dev]; + + /* configure pin as input */ + res = gpio_init_in(dev, pullup); + if (res < 0) { + return res; + } + + /* enable clock of the SYSCFG module for EXTI configuration */ + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + + /* read pin number, set EXIT channel and enable global interrupt for EXTI channel */ + switch (dev) { +#ifdef GPIO_0_EN + case GPIO_0: + GPIO_0_EXTI_CFG(); + break; +#endif +#ifdef GPIO_1_EN + case GPIO_1: + GPIO_1_EXTI_CFG(); + break; +#endif +#ifdef GPIO_2_EN + case GPIO_2: + GPIO_2_EXTI_CFG(); + break; +#endif +#ifdef GPIO_3_EN + case GPIO_3: + GPIO_3_EXTI_CFG(); + break; +#endif +#ifdef GPIO_4_EN + case GPIO_4: + GPIO_4_EXTI_CFG(); + break; +#endif +#ifdef GPIO_5_EN + case GPIO_5: + GPIO_5_EXTI_CFG(); + break; +#endif +#ifdef GPIO_6_EN + case GPIO_6: + GPIO_6_EXTI_CFG(); + break; +#endif +#ifdef GPIO_7_EN + case GPIO_7: + GPIO_7_EXTI_CFG(); + break; +#endif +#ifdef GPIO_8_EN + case GPIO_8: + GPIO_8_EXTI_CFG(); + break; +#endif +#ifdef GPIO_9_EN + case GPIO_9: + GPIO_9_EXTI_CFG(); + break; +#endif +#ifdef GPIO_10_EN + case GPIO_10: + GPIO_10_EXTI_CFG(); + break; +#endif +#ifdef GPIO_11_EN + case GPIO_11: + GPIO_11_EXTI_CFG(); + break; +#endif +#ifdef GPIO_12_EN + case GPIO_12: + GPIO_12_EXTI_CFG(); + break; +#endif +#ifdef GPIO_13_EN + case GPIO_13: + GPIO_13_EXTI_CFG(); + break; +#endif +#ifdef GPIO_14_EN + case GPIO_14: + GPIO_14_EXTI_CFG(); + break; +#endif +#ifdef GPIO_15_EN + case GPIO_15: + GPIO_15_EXTI_CFG(); + break; +#endif + } + + NVIC_EnableIRQ(gpio_irq_map[dev]); + + /* set callback */ + gpio_config[dev].cb = cb; + gpio_config[dev].arg = arg; + + /* configure the event that triggers an interrupt */ + switch (flank) { + case GPIO_RISING: + EXTI->RTSR |= (1 << pin); + EXTI->FTSR &= ~(1 << pin); + break; + case GPIO_FALLING: + EXTI->RTSR &= ~(1 << pin); + EXTI->FTSR |= (1 << pin); + break; + case GPIO_BOTH: + EXTI->RTSR |= (1 << pin); + EXTI->FTSR |= (1 << pin); + break; + } + + /* clear any pending requests */ + EXTI->PR = (1 << pin); + /* unmask the pins interrupt channel */ + EXTI->IMR |= (1 << pin); + + return 0; +} + +void gpio_irq_enable(gpio_t dev) +{ + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return; + } + + pin = gpio_pin_map[dev]; + EXTI->IMR |= (1 << pin); +} + +void gpio_irq_disable(gpio_t dev) +{ + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return; + } + + pin = gpio_pin_map[dev]; + EXTI->IMR &= ~(1 << pin); +} + +int gpio_read(gpio_t dev) +{ + GPIO_TypeDef *port; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return -1; + } + + port = gpio_port_map[dev]; + pin = gpio_pin_map[dev]; + + if (port->MODER & (1 << (pin * 2))) { /* if configured as output */ + return port->ODR & (1 << pin); /* read output data register */ + } else { + return port->IDR & (1 << pin); /* else read input data register */ + } +} + +void gpio_set(gpio_t dev) +{ + GPIO_TypeDef *port; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return; + } + + port = gpio_port_map[dev]; + pin = gpio_pin_map[dev]; + + port->ODR |= (1 << pin); +} + +void gpio_clear(gpio_t dev) +{ + GPIO_TypeDef *port; + uint8_t pin; + + if (dev >= GPIO_NUMOF) { + return; + } + + port = gpio_port_map[dev]; + pin = gpio_pin_map[dev]; + + port->ODR &= ~(1 << pin); +} + +void gpio_toggle(gpio_t dev) +{ + if (gpio_read(dev)) { + gpio_clear(dev); + } else { + gpio_set(dev); + } +} + +void gpio_write(gpio_t dev, int value) +{ + if (value) { + gpio_set(dev); + } else { + gpio_clear(dev); + } +} + +#ifdef GPIO_IRQ_0 +void isr_exti0(void) +{ + if (EXTI->PR & EXTI_PR_PR0) { + EXTI->PR |= EXTI_PR_PR0; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_0].cb(gpio_config[GPIO_IRQ_0].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#ifdef GPIO_IRQ_1 +void isr_exti1(void) +{ + if (EXTI->PR & EXTI_PR_PR1) { + EXTI->PR |= EXTI_PR_PR1; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_1].cb(gpio_config[GPIO_IRQ_1].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#ifdef GPIO_IRQ_2 +void isr_exti2(void) +{ + if (EXTI->PR & EXTI_PR_PR2) { + EXTI->PR |= EXTI_PR_PR2; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_2].cb(gpio_config[GPIO_IRQ_2].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#ifdef GPIO_IRQ_3 +void isr_exti3(void) +{ + if (EXTI->PR & EXTI_PR_PR3) { + EXTI->PR |= EXTI_PR_PR3; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_3].cb(gpio_config[GPIO_IRQ_3].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#ifdef GPIO_IRQ_4 +void isr_exti4(void) +{ + if (EXTI->PR & EXTI_PR_PR4) { + EXTI->PR |= EXTI_PR_PR4; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_4].cb(gpio_config[GPIO_IRQ_4].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#if defined(GPIO_IRQ_5) || defined(GPIO_IRQ_6) || defined(GPIO_IRQ_7) || defined(GPIO_IRQ_8) || defined(GPIO_IRQ_9) +void isr_exti9_5(void) +{ + if (EXTI->PR & EXTI_PR_PR5) { + EXTI->PR |= EXTI_PR_PR5; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_5].cb(gpio_config[GPIO_IRQ_5].arg); + } + else if (EXTI->PR & EXTI_PR_PR6) { + EXTI->PR |= EXTI_PR_PR6; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_6].cb(gpio_config[GPIO_IRQ_6].arg); + } + else if (EXTI->PR & EXTI_PR_PR7) { + EXTI->PR |= EXTI_PR_PR7; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_7].cb(gpio_config[GPIO_IRQ_7].arg); + } + else if (EXTI->PR & EXTI_PR_PR8) { + EXTI->PR |= EXTI_PR_PR8; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_8].cb(gpio_config[GPIO_IRQ_8].arg); + } + else if (EXTI->PR & EXTI_PR_PR9) { + EXTI->PR |= EXTI_PR_PR9; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_9].cb(gpio_config[GPIO_IRQ_9].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#if defined(GPIO_IRQ_10) || defined(GPIO_IRQ_11) || defined(GPIO_IRQ_12) || defined(GPIO_IRQ_13) || defined(GPIO_IRQ_14) || defined(GPIO_IRQ_15) +void isr_exti15_10(void) +{ + if (EXTI->PR & EXTI_PR_PR10) { + EXTI->PR |= EXTI_PR_PR10; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_10].cb(gpio_config[GPIO_IRQ_10].arg); + } + else if (EXTI->PR & EXTI_PR_PR11) { + EXTI->PR |= EXTI_PR_PR11; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_11].cb(gpio_config[GPIO_IRQ_11].arg); + } + else if (EXTI->PR & EXTI_PR_PR12) { + EXTI->PR |= EXTI_PR_PR12; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_12].cb(gpio_config[GPIO_IRQ_12].arg); + } + else if (EXTI->PR & EXTI_PR_PR13) { + EXTI->PR |= EXTI_PR_PR13; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_13].cb(gpio_config[GPIO_IRQ_13].arg); + } + else if (EXTI->PR & EXTI_PR_PR14) { + EXTI->PR |= EXTI_PR_PR14; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_14].cb(gpio_config[GPIO_IRQ_14].arg); + } + else if (EXTI->PR & EXTI_PR_PR15) { + EXTI->PR |= EXTI_PR_PR15; /* clear status bit by writing a 1 to it */ + gpio_config[GPIO_IRQ_15].cb(gpio_config[GPIO_IRQ_15].arg); + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif + +#endif /* GPIO_NUMOF */ diff --git a/cpu/stm32l1/periph/i2c.c b/cpu/stm32l1/periph/i2c.c new file mode 100644 index 0000000000..c9631c96e5 --- /dev/null +++ b/cpu/stm32l1/periph/i2c.c @@ -0,0 +1,543 @@ +/* + * Copyright (C) 2014 FU Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser + * General Public License v2.1. See the file LICENSE in the top level + * directory for more details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file + * @brief Low-level I2C driver implementation + * + * @note This implementation only implements the 7-bit addressing mode. + * + * @author Peter Kietzmann + * @author Hauke Petersen + * @author Thomas Eichinger + * + * @} + */ + +#include + + +#include "cpu.h" +#include "periph/i2c.h" +#include "periph_conf.h" + + +#define ENABLE_DEBUG (0) +#include "debug.h" + +/* guard file in case no I2C device is defined */ +#if I2C_NUMOF + +/* static function definitions */ +static void _i2c_init(I2C_TypeDef *i2c, int ccr); +static void _toggle_pins(GPIO_TypeDef *port, int pin_scl, int pin_sda); +static void _pin_config(GPIO_TypeDef *port, int pin_scl, int pin_sda); +static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t rw_flag); +static inline void _clear_addr(I2C_TypeDef *dev); +static inline void _write(I2C_TypeDef *dev, char *data, int length); +static inline void _stop(I2C_TypeDef *dev); + +int i2c_init_master(i2c_t dev, i2c_speed_t speed) +{ + I2C_TypeDef *i2c; + GPIO_TypeDef *port; + int pin_scl = 0, pin_sda = 0; + int ccr; + + /* read speed configuration */ + switch (speed) { + case I2C_SPEED_NORMAL: + ccr = I2C_APBCLK / 200000; + break; + + case I2C_SPEED_FAST: + ccr = I2C_APBCLK / 800000; + break; + + default: + return -2; + } + + /* read static device configuration */ + switch (dev) { +#if I2C_0_EN + case I2C_0: + i2c = I2C_0_DEV; + port = I2C_0_PORT; + pin_scl = I2C_0_SCL_PIN; + pin_sda = I2C_0_SDA_PIN; + I2C_0_CLKEN(); + I2C_0_PORT_CLKEN(); + NVIC_SetPriority(I2C_0_ERR_IRQ, I2C_IRQ_PRIO); + NVIC_EnableIRQ(I2C_0_ERR_IRQ); + break; +#endif + + default: + return -1; + } + + /* configure pins */ + _pin_config(port, pin_scl, pin_sda); + + /* configure device */ + _i2c_init(i2c, ccr); + + /* make sure the analog filters don't hang -> see errata sheet 2.14.7 */ + if (i2c->SR2 & I2C_SR2_BUSY) { + DEBUG("LINE BUSY AFTER RESET -> toggle pins now\n"); + /* disable peripheral */ + i2c->CR1 &= ~I2C_CR1_PE; + /* toggle both pins to reset analog filter */ + _toggle_pins(port, pin_scl, pin_sda); + /* reset pins for alternate function */ + _pin_config(port, pin_scl, pin_sda); + /* make peripheral soft reset */ + i2c->CR1 |= I2C_CR1_SWRST; + i2c->CR1 &= ~I2C_CR1_SWRST; + /* enable device */ + _i2c_init(i2c, ccr); + } + return 0; +} + +static void _i2c_init(I2C_TypeDef *i2c, int ccr) +{ + /* disable device and set ACK bit */ + i2c->CR1 = I2C_CR1_ACK; + /* configure I2C clock */ + i2c->CR2 = (I2C_APBCLK / 1000000) | I2C_CR2_ITERREN; + i2c->CCR = ccr; + i2c->TRISE = (I2C_APBCLK / 1000000) + 1; + /* configure device */ + i2c->OAR1 = 0; /* makes sure we are in 7-bit address mode */ + /* enable device */ + i2c->CR1 |= I2C_CR1_PE; +} + +static void _pin_config(GPIO_TypeDef *port, int pin_scl, int pin_sda) +{ + /* Set GPIOs to AF mode */ + port->MODER &= ~(3 << (2 * pin_scl)); + port->MODER |= (2 << (2 * pin_scl)); + port->MODER &= ~(3 << (2 * pin_sda)); + port->MODER |= (2 << (2 * pin_sda)); + + /* Set speed high*/ + port->OSPEEDR |= (3 << (2 * pin_scl)); + port->OSPEEDR |= (3 << (2 * pin_sda)); + + /* Set to push-pull configuration open drain*/ + port->OTYPER |= (1 << pin_scl); + port->OTYPER |= (1 << pin_sda); + + /* Enable pull-up resistors */ + port->PUPDR &= ~(3 << (2 * pin_scl)); + port->PUPDR |= (1 << (2 * pin_scl)); + port->PUPDR &= ~(3 << (2 * pin_sda)); + port->PUPDR |= (1 << (2 * pin_sda)); + + /* Configure GPIOs to for the I2C alternate function */ + if (pin_scl < 8) { + port->AFR[0] &= ~(0xf << (4 * pin_scl)); + port->AFR[0] |= (I2C_0_SCL_AF << (4 * pin_scl)); + } + else { + port->AFR[1] &= ~(0xf << (4 * (pin_scl - 8))); + port->AFR[1] |= (I2C_0_SCL_AF << (4 * (pin_scl - 8))); + } + + if (pin_sda < 8) { + port->AFR[0] &= ~(0xf << (4 * pin_sda)); + port->AFR[0] |= (I2C_0_SDA_AF << (4 * pin_sda)); + } + else { + port->AFR[1] &= ~(0xf << (4 * (pin_sda - 8))); + port->AFR[1] |= (I2C_0_SDA_AF << (4 * (pin_sda - 8))); + } +} + +static void _toggle_pins(GPIO_TypeDef *port, int pin_scl, int pin_sda) +{ + /* Set GPIOs to General purpose output mode mode */ + port->MODER &= ~(3 << (2 * pin_scl)); + port->MODER |= (1 << (2 * pin_scl)); + port->MODER &= ~(3 << (2 * pin_sda)); + port->MODER |= (1 << (2 * pin_sda)); + + /* Set speed high*/ + port->OSPEEDR |= (3 << (2 * pin_scl)); + port->OSPEEDR |= (3 << (2 * pin_sda)); + + /* Set to push-pull configuration open drain*/ + port->OTYPER |= (1 << pin_scl); + port->OTYPER |= (1 << pin_sda); + + /* set both to high */ + port->ODR |= (1 << pin_scl); + port->ODR |= (1 << pin_sda); + /* set SDA to low */ + port->ODR &= ~(1 << pin_sda); + /* set SCL to low */ + port->ODR &= ~(1 << pin_scl); + /* set SCL to high */ + port->ODR |= (1 << pin_scl); + /* set SDA to high */ + port->ODR |= (1 << pin_sda); +} + +int i2c_init_slave(i2c_t dev, uint8_t address) +{ + /* TODO: implement slave mode */ + return -1; +} + +int i2c_read_byte(i2c_t dev, uint8_t address, char *data) +{ + return i2c_read_bytes(dev, address, data, 1); +} + +int i2c_read_bytes(i2c_t dev, uint8_t address, char *data, int length) +{ + unsigned int state; + int i = 0; + I2C_TypeDef *i2c; + + switch (dev) { +#if I2C_0_EN + case I2C_0: + i2c = I2C_0_DEV; + break; +#endif + + default: + return -1; + } + + switch (length) { + case 1: + DEBUG("Send Slave address and wait for ADDR == 1\n"); + _start(i2c, address, I2C_FLAG_READ); + + DEBUG("Set ACK = 0\n"); + i2c->CR1 &= ~(I2C_CR1_ACK); + + DEBUG("Clear ADDR and set STOP = 1\n"); + state = disableIRQ(); + _clear_addr(i2c); + i2c->CR1 |= (I2C_CR1_STOP); + restoreIRQ(state); + + DEBUG("Wait for RXNE == 1\n"); + + while (!(i2c->SR1 & I2C_SR1_RXNE)); + + DEBUG("Read received data\n"); + *data = (char)i2c->DR; + + /* wait until STOP is cleared by hardware */ + while (i2c->CR1 & I2C_CR1_STOP); + + /* reset ACK to be able to receive new data */ + i2c->CR1 |= (I2C_CR1_ACK); + break; + + case 2: + DEBUG("Send Slave address and wait for ADDR == 1\n"); + _start(i2c, address, I2C_FLAG_READ); + DEBUG("Set POS bit\n"); + i2c->CR1 |= (I2C_CR1_POS | I2C_CR1_ACK); + DEBUG("Crit block: Clear ADDR bit and clear ACK flag\n"); + state = disableIRQ(); + _clear_addr(i2c); + i2c->CR1 &= ~(I2C_CR1_ACK); + restoreIRQ(state); + + DEBUG("Wait for transfer to be completed\n"); + + while (!(i2c->SR1 & I2C_SR1_BTF)); + + DEBUG("Crit block: set STOP and read first byte\n"); + state = disableIRQ(); + i2c->CR1 |= (I2C_CR1_STOP); + data[0] = (char)i2c->DR; + restoreIRQ(state); + + DEBUG("read second byte\n"); + data[1] = (char)i2c->DR; + + DEBUG("wait for STOP bit to be cleared again\n"); + + while (i2c->CR1 & I2C_CR1_STOP); + + DEBUG("reset POS = 0 and ACK = 1\n"); + i2c->CR1 &= ~(I2C_CR1_POS); + i2c->CR1 |= (I2C_CR1_ACK); + break; + + default: + DEBUG("Send Slave address and wait for ADDR == 1\n"); + _start(i2c, address, I2C_FLAG_READ); + _clear_addr(i2c); + + while (i < (length - 3)) { + DEBUG("Wait until byte was received\n"); + + while (!(i2c->SR1 & I2C_SR1_RXNE)); + + DEBUG("Copy byte from DR\n"); + data[i++] = (char)i2c->DR; + } + + DEBUG("Reading the last 3 bytes, waiting for BTF flag\n"); + + while (!(i2c->SR1 & I2C_SR1_BTF)); + + DEBUG("Disable ACK\n"); + i2c->CR1 &= ~(I2C_CR1_ACK); + + DEBUG("Crit block: set STOP and read N-2 byte\n"); + state = disableIRQ(); + data[i++] = (char)i2c->DR; + i2c->CR1 |= (I2C_CR1_STOP); + restoreIRQ(state); + + DEBUG("Read N-1 byte\n"); + data[i++] = (char)i2c->DR; + + while (!(i2c->SR1 & I2C_SR1_RXNE)); + + DEBUG("Read last byte\n"); + + data[i++] = (char)i2c->DR; + + DEBUG("wait for STOP bit to be cleared again\n"); + + while (i2c->CR1 & I2C_CR1_STOP); + + DEBUG("reset POS = 0 and ACK = 1\n"); + i2c->CR1 &= ~(I2C_CR1_POS); + i2c->CR1 |= (I2C_CR1_ACK); + } + + return length; +} + +int i2c_read_reg(i2c_t dev, uint8_t address, uint8_t reg, char *data) +{ + return i2c_read_regs(dev, address, reg, data, 1); +} + +int i2c_read_regs(i2c_t dev, uint8_t address, uint8_t reg, char *data, int length) +{ + I2C_TypeDef *i2c; + + switch (dev) { +#if I2C_0_EN + case I2C_0: + i2c = I2C_0_DEV; + break; +#endif + + default: + return -1; + } + + /* send start condition and slave address */ + DEBUG("Send slave address and clear ADDR flag\n"); + _start(i2c, address, I2C_FLAG_WRITE); + _clear_addr(i2c); + DEBUG("Write reg into DR\n"); + i2c->DR = reg; + _stop(i2c); + DEBUG("Now start a read transaction\n"); + return i2c_read_bytes(dev, address, data, length); +} + +int i2c_write_byte(i2c_t dev, uint8_t address, char data) +{ + return i2c_write_bytes(dev, address, &data, 1); +} + +int i2c_write_bytes(i2c_t dev, uint8_t address, char *data, int length) +{ + I2C_TypeDef *i2c; + + switch (dev) { +#if I2C_0_EN + case I2C_0: + i2c = I2C_0_DEV; + break; +#endif + + default: + return -1; + } + + /* start transmission and send slave address */ + DEBUG("sending start sequence\n"); + _start(i2c, address, I2C_FLAG_WRITE); + _clear_addr(i2c); + /* send out data bytes */ + _write(i2c, data, length); + /* end transmission */ + DEBUG("Ending transmission\n"); + _stop(i2c); + DEBUG("STOP condition was send out\n"); + return length; +} + +int i2c_write_reg(i2c_t dev, uint8_t address, uint8_t reg, char data) +{ + return i2c_write_regs(dev, address, reg, &data, 1); +} + +int i2c_write_regs(i2c_t dev, uint8_t address, uint8_t reg, char *data, int length) +{ + I2C_TypeDef *i2c; + + switch (dev) { +#if I2C_0_EN + case I2C_0: + i2c = I2C_0_DEV; + break; +#endif + + default: + return -1; + } + + /* start transmission and send slave address */ + _start(i2c, address, I2C_FLAG_WRITE); + _clear_addr(i2c); + /* send register address and wait for complete transfer to be finished*/ + _write(i2c, (char *)(®), 1); + /* write data to register */ + _write(i2c, data, length); + /* finish transfer */ + _stop(i2c); + /* return number of bytes send */ + return length; +} + +void i2c_poweron(i2c_t dev) +{ + switch (dev) { +#if I2C_0_EN + case I2C_0: + I2C_0_CLKEN(); + break; +#endif + } +} + +void i2c_poweroff(i2c_t dev) +{ + switch (dev) { +#if I2C_0_EN + case I2C_0: + while (I2C_0_DEV->SR2 & I2C_SR2_BUSY); + + I2C_0_CLKDIS(); + break; +#endif + } +} + +static void _start(I2C_TypeDef *dev, uint8_t address, uint8_t rw_flag) +{ + /* wait for device to be ready */ + DEBUG("Wait for device to be ready\n"); + + while (dev->SR2 & I2C_SR2_BUSY); + + /* generate start condition */ + DEBUG("Generate start condition\n"); + dev->CR1 |= I2C_CR1_START; + DEBUG("Wait for SB flag to be set\n"); + + while (!(dev->SR1 & I2C_SR1_SB)); + + /* send address and read/write flag */ + DEBUG("Send address\n"); + dev->DR = (address << 1) | rw_flag; + /* clear ADDR flag by reading first SR1 and then SR2 */ + DEBUG("Wait for ADDR flag to be set\n"); + + while (!(dev->SR1 & I2C_SR1_ADDR)); +} + +static inline void _clear_addr(I2C_TypeDef *dev) +{ + dev->SR1; + dev->SR2; + DEBUG("Cleared address\n"); +} + +static inline void _write(I2C_TypeDef *dev, char *data, int length) +{ + DEBUG("Looping through bytes\n"); + + for (int i = 0; i < length; i++) { + /* write data to data register */ + dev->DR = (uint8_t)data[i]; + DEBUG("Written %i byte to data reg, now waiting for DR to be empty again\n", i); + + /* wait for transfer to finish */ + while (!(dev->SR1 & I2C_SR1_TXE)); + + DEBUG("DR is now empty again\n"); + } +} + +static inline void _stop(I2C_TypeDef *dev) +{ + /* make sure last byte was send */ + DEBUG("Wait if last byte hasn't been sent\n"); + + while (!(dev->SR1 & I2C_SR1_BTF)); + + /* send STOP condition */ + dev->CR1 |= I2C_CR1_STOP; +} + +#if I2C_0_EN +void I2C_0_ERR_ISR(void) +{ + unsigned state = I2C_0_DEV->SR1; + DEBUG("\n\n### I2C ERROR OCCURED ###\n"); + DEBUG("status: %08x\n", state); + if (state & I2C_SR1_OVR) { + DEBUG("OVR\n"); + } + if (state & I2C_SR1_AF) { + DEBUG("AF\n"); + } + if (state & I2C_SR1_ARLO) { + DEBUG("ARLO\n"); + } + if (state & I2C_SR1_BERR) { + DEBUG("BERR\n"); + } + if (state & I2C_SR1_PECERR) { + DEBUG("PECERR\n"); + } + if (state & I2C_SR1_TIMEOUT) { + DEBUG("TIMEOUT\n"); + } + if (state & I2C_SR1_SMBALERT) { + DEBUG("SMBALERT\n"); + } + while (1); +} +#endif /* I2C_0_EN */ + +#endif /* I2C_NUMOF */ diff --git a/cpu/stm32l1/periph/spi.c b/cpu/stm32l1/periph/spi.c new file mode 100644 index 0000000000..5d983ab5b9 --- /dev/null +++ b/cpu/stm32l1/periph/spi.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file + * @brief Low-level SPI driver implementation + * + * @author Peter Kietzmann + * @author Hauke Petersen + * @author Fabian Nack + * @author Thomas Eichinger + * + * @} + */ + +#include "cpu.h" +#include "periph/spi.h" +#include "periph_conf.h" +#include "thread.h" +#include "sched.h" + +/* guard file in case no SPI device is defined */ +#if SPI_NUMOF + +int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed) +{ + SPI_TypeDef *spi; + + /* power on the SPI device */ + spi_poweron(dev); + + switch (dev) { +#if SPI_0_EN + case SPI_0: + spi = SPI_0_DEV; + SPI_0_PORT_CLKEN(); + break; +#endif +#if SPI_1_EN + case SPI_1: + spi = SPI_1_DEV; + SPI_1_PORT_CLKEN(); + break; +#endif + default: + return -1; + } + + /* configure SCK, MISO and MOSI pin */ + spi_conf_pins(dev); + + /* reset SPI configuration registers */ + spi->CR1 = 0; + spi->CR2 = 0; + spi->I2SCFGR = 0; /* this makes sure SPI mode is selected */ + + /* configure bus clock speed */ + switch (speed) { + case SPI_SPEED_100KHZ: + spi->CR1 |= (7 << 3); /* actual clock: 125KHz (lowest possible) */ + break; + case SPI_SPEED_400KHZ: + spi->CR1 |= (5 << 3); /* actual clock: 500KHz */ + break; + case SPI_SPEED_1MHZ: + spi->CR1 |= (4 << 3); /* actual clock: 1MHz */ + break; + case SPI_SPEED_5MHZ: + spi->CR1 |= (2 << 3); /* actual clock: 4MHz */ + break; + case SPI_SPEED_10MHZ: + spi->CR1 |= (1 << 3); /* actual clock 8MHz */ + } + + /* select clock polarity and clock phase */ + spi->CR1 |= conf; + /* select master mode */ + spi->CR1 |= SPI_CR1_MSTR; + /* the NSS (chip select) is managed purely by software */ + spi->CR1 |= SPI_CR1_SSM | SPI_CR1_SSI; + /* enable the SPI device */ + spi->CR1 |= SPI_CR1_SPE; + return 0; +} + +int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data)) +{ + /* due to issues with the send buffer, the slave mode is not (yet) supported */ + return -1; +} + +int spi_conf_pins(spi_t dev) +{ + GPIO_TypeDef *port; + int pin[3]; /* 3 pins: sck, miso, mosi */ + int af = 0; + + switch (dev) { +#if SPI_0_EN + case SPI_0: + port = SPI_0_PORT; + pin[0] = SPI_0_PIN_SCK; + pin[1] = SPI_0_PIN_MISO; + pin[2] = SPI_0_PIN_MOSI; + af = SPI_0_PIN_AF; + break; +#endif +#if SPI_1_EN + case SPI_1: + port = SPI_1_PORT; + pin[0] = SPI_1_PIN_SCK; + pin[1] = SPI_1_PIN_MISO; + pin[2] = SPI_1_PIN_MOSI; + af = SPI_1_PIN_AF; + break; +#endif + default: + return -1; + } + + /* configure pins for their correct alternate function */ + for (int i = 0; i < 3; i++) { + port->MODER &= ~(3 << (pin[i] * 2)); + port->MODER |= (2 << (pin[i] * 2)); + int hl = (pin[i] < 8) ? 0 : 1; + port->AFR[hl] &= ~(0xf << ((pin[i] - (hl * 8)) * 4)); + port->AFR[hl] |= (af << ((pin[i] - (hl * 8)) * 4)); + } + + return 0; +} + +int spi_transfer_byte(spi_t dev, char out, char *in) +{ + char tmp; + SPI_TypeDef *spi = 0; + + switch (dev) { +#if SPI_0_EN + case SPI_0: + spi = SPI_0_DEV; + break; +#endif +#if SPI_1_EN + case SPI_1: + spi = SPI_1_DEV; + break; +#endif + default: + return 0; + } + + /* wait for an eventually previous byte to be readily transferred */ + while(!(spi->SR & SPI_SR_TXE)); + /* put next byte into the output register */ + spi->DR = out; + /* wait until the current byte was successfully transferred */ + while(!(spi->SR & SPI_SR_RXNE)); + /* read response byte to reset flags */ + tmp = spi->DR; + /* 'return' response byte if wished for */ + if (in) { + *in = tmp; + } + +#if ENABLE_DEBUG + if (in != NULL) { + DEBUG("\nout: %x in: %x \n", out, *in, transferred); + } + else { + DEBUG("\nout: %x in: was nullPointer\n", out, transferred); + } +#endif /*ENABLE_DEBUG */ + + return 1; +} + +int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length) +{ + char res; + int count = 0; + + for (int i = 0; i < length; i++) { + if (out) { + count += spi_transfer_byte(dev, out[i], &res); + } + else { + count += spi_transfer_byte(dev, 0, &res); + } + if (in) { + in[i] = res; + } + } + + return count; +} + +int spi_transfer_reg(spi_t dev, uint8_t reg, char out, char *in) +{ + spi_transfer_byte(dev, reg, 0); + return spi_transfer_byte(dev, out, in); +} + +int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int length) +{ + spi_transfer_byte(dev, reg, 0); + return spi_transfer_bytes(dev, out, in, length); +} + +void spi_transmission_begin(spi_t dev, char reset_val) +{ + /* slave mode is not (yet) supported */ +} + +void spi_poweron(spi_t dev) +{ + switch (dev) { +#if SPI_0_EN + case SPI_0: + SPI_0_CLKEN(); + break; +#endif +#if SPI_1_EN + case SPI_1: + SPI_1_CLKEN(); + break; +#endif + } +} + +void spi_poweroff(spi_t dev) +{ + switch (dev) { +#if SPI_0_EN + case SPI_0: + while (SPI_0_DEV->SR & SPI_SR_BSY); + SPI_0_CLKDIS(); + break; +#endif +#if SPI_1_EN + case SPI_1: + while (SPI_1_DEV->SR & SPI_SR_BSY); + SPI_1_CLKDIS(); + break; +#endif + } +} + +#endif /* SPI_NUMOF */ diff --git a/cpu/stm32l1/periph/timer.c b/cpu/stm32l1/periph/timer.c new file mode 100644 index 0000000000..0bc04e54fb --- /dev/null +++ b/cpu/stm32l1/periph/timer.c @@ -0,0 +1,409 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file + * @brief Low-level timer driver implementation + * + * @author Thomas Eichinger + * + * @} + */ + +#include + +#include "cpu.h" +#include "board.h" +#include "periph_conf.h" +#include "periph/timer.h" + +#include "thread.h" + +#define ENABLE_DEBUG (0) +#include "debug.h" + +/* guard file in case no TIMER device is defined */ +#if TIMER_0_EN || TIMER_1_EN + +static inline void irq_handler(tim_t timer, TIM_TypeDef *dev0, TIM_TypeDef *dev1); + +typedef struct { + void (*cb)(int); +} timer_conf_t; + +/** + * Timer state memory + */ +static timer_conf_t config[TIMER_NUMOF]; + +int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int)) +{ + TIM_TypeDef *timer0; + TIM_TypeDef *timer1; + uint8_t trigger_selector; + + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + /* enable timer peripheral clock */ + TIMER_0_CLKEN(); + /* set timer's IRQ priority */ + NVIC_SetPriority(TIMER_0_IRQ_CHAN_0, TIMER_0_IRQ_PRIO); + NVIC_SetPriority(TIMER_0_IRQ_CHAN_1, TIMER_0_IRQ_PRIO); + /* select timer */ + timer0 = TIMER_0_DEV_0; + timer1 = TIMER_0_DEV_1; + trigger_selector = TIMER_0_TRIG_SEL; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + /* enable timer peripheral clock */ + TIMER_1_CLKEN(); + /* set timer's IRQ priority */ + NVIC_SetPriority(TIMER_1_IRQ_CHAN_0, TIMER_1_IRQ_PRIO); + NVIC_SetPriority(TIMER_1_IRQ_CHAN_1, TIMER_1_IRQ_PRIO); + /* select timer */ + timer0 = TIMER_1_DEV_0; + timer1 = TIMER_1_DEV_1; + trigger_selector = TIMER_1_TRIG_SEL; + break; +#endif + case TIMER_UNDEFINED: + default: + return -1; + } + + /* set callback function */ + config[dev].cb = callback; + + /* set timer to run in counter mode */ + timer0->CR1 = (TIM_CR1_ARPE | TIM_CR1_URS); + timer1->CR1 = TIM_CR1_URS; + + /* configure master timer0 */ + /* send update event as trigger output */ + timer0->CR2 |= TIM_CR2_MMS_1; + /* set auto-reload and prescaler values and load new values */ + timer0->ARR = TIMER_0_MAX_VALUE; + timer0->PSC = TIMER_0_PRESCALER * ticks_per_us; + + /* configure slave timer1 */ + /* get input trigger */ + timer1->SMCR |= trigger_selector; + /* external clock mode 1 */ + timer1->SMCR |= TIM_SMCR_SMS; + + /* enable the timer's interrupt */ + timer_irq_enable(dev); + + /* start the timer */ + timer_start(dev); + + return 0; +} + +int timer_set(tim_t dev, int channel, unsigned int timeout) +{ + int now = timer_read(dev); + return timer_set_absolute(dev, channel, now + timeout - 1); +} + +int timer_set_absolute(tim_t dev, int channel, unsigned int value) +{ + TIM_TypeDef *timer0; + TIM_TypeDef *timer1; + + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + /* select timer */ + timer0 = TIMER_0_DEV_0; + timer1 = TIMER_0_DEV_1; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + /* select timer */ + timer0 = TIMER_1_DEV_0; + timer1 = TIMER_1_DEV_1; + break; +#endif + case TIMER_UNDEFINED: + default: + return -1; + } + + timer0->DIER &= ~TIM_DIER_UIE; + + switch (channel) { + case 0: + timer0->CCR1 = (0xffff & value); + timer1->CCR1 = (value >> 16); + timer0->SR &= ~TIM_SR_CC1IF; + timer0->DIER |= TIM_DIER_CC1IE; + DEBUG("Channel 1 set to %x\n", value); + break; + case 1: + timer0->CCR2 = (0xffff & value); + timer1->CCR2 = (value >> 16); + timer0->SR &= ~TIM_SR_CC2IF; + timer0->DIER |= TIM_DIER_CC2IE; + DEBUG("Channel 2 set to %x\n", value); + break; + case 2: + timer0->CCR3 = (0xffff & value); + timer1->CCR3 = (value >> 16); + timer0->SR &= ~TIM_SR_CC3IF; + timer0->DIER |= TIM_DIER_CC3IE; + DEBUG("Channel 3 set to %x\n", value); + break; + case 3: + timer0->CCR4 = (0xffff & value); + timer1->CCR4 = (value >> 16); + timer0->SR &= ~TIM_SR_CC4IF; + timer0->DIER |= TIM_DIER_CC4IE; + DEBUG("Channel 4 set to %x\n", value); + break; + default: + return -1; + } + return 0; +} + +int timer_clear(tim_t dev, int channel) +{ + TIM_TypeDef *timer0; + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + timer0 = TIMER_0_DEV_0; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + timer0 = TIMER_1_DEV_0; + break; +#endif + case TIMER_UNDEFINED: + default: + return -1; + } + switch (channel) { + case 0: + timer0->DIER &= ~TIM_DIER_CC1IE; + break; + case 1: + timer0->DIER &= ~TIM_DIER_CC2IE; + break; + case 2: + timer0->DIER &= ~TIM_DIER_CC3IE; + break; + case 3: + timer0->DIER &= ~TIM_DIER_CC4IE; + break; + default: + return -1; + } + return 0; +} + +unsigned int timer_read(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + return (((unsigned int)(0xffff & TIMER_0_DEV_0->CNT)) | (TIMER_0_DEV_1->CNT<<16)); + break; +#endif +#if TIMER_1_EN + case TIMER_1: + return (((unsigned int)(0xffff & TIMER_1_DEV_0->CNT)) | (TIMER_1_DEV_1->CNT<<16)); + break; +#endif + case TIMER_UNDEFINED: + default: + return 0; + } +} + +void timer_start(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + /* slave has to be enabled first */ + TIMER_0_DEV_1->CR1 |= TIM_CR1_CEN; + TIMER_0_DEV_0->CR1 |= TIM_CR1_CEN; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + /* slave has to be enabled first */ + TIMER_1_DEV_1->CR1 |= TIM_CR1_CEN; + TIMER_1_DEV_0->CR1 |= TIM_CR1_CEN; + break; +#endif + case TIMER_UNDEFINED: + break; + } +} + +void timer_stop(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + TIMER_0_DEV_0->CR1 &= ~TIM_CR1_CEN; + TIMER_0_DEV_1->CR1 &= ~TIM_CR1_CEN; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + TIMER_1_DEV_0->CR1 &= ~TIM_CR1_CEN; + TIMER_1_DEV_1->CR1 &= ~TIM_CR1_CEN; + break; +#endif + case TIMER_UNDEFINED: + break; + } +} + +void timer_irq_enable(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + NVIC_EnableIRQ(TIMER_0_IRQ_CHAN_0); + NVIC_EnableIRQ(TIMER_0_IRQ_CHAN_1); + break; +#endif +#if TIMER_1_EN + case TIMER_1: + NVIC_EnableIRQ(TIMER_1_IRQ_CHAN_0); + NVIC_EnableIRQ(TIMER_1_IRQ_CHAN_1); + break; +#endif + case TIMER_UNDEFINED: + break; + } +} + +void timer_irq_disable(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + NVIC_DisableIRQ(TIMER_0_IRQ_CHAN_0); + NVIC_DisableIRQ(TIMER_0_IRQ_CHAN_1); + break; +#endif +#if TIMER_1_EN + case TIMER_1: + NVIC_DisableIRQ(TIMER_1_IRQ_CHAN_0); + NVIC_DisableIRQ(TIMER_1_IRQ_CHAN_1); + break; +#endif + case TIMER_UNDEFINED: + break; + } +} + +void timer_reset(tim_t dev) +{ + switch (dev) { +#if TIMER_0_EN + case TIMER_0: + TIMER_0_DEV_0->CNT = 0; + TIMER_0_DEV_1->CNT = 0; + break; +#endif +#if TIMER_1_EN + case TIMER_1: + TIMER_1_DEV_0->CNT = 0; + TIMER_1_DEV_1->CNT = 0; + break; +#endif + case TIMER_UNDEFINED: + break; + } +} + + +#if TIMER_0_EN +void TIMER_0_ISR_0(void) +{ + DEBUG("\nenter ISR\n"); + irq_handler(TIMER_0, TIMER_0_DEV_0, TIMER_0_DEV_1); + DEBUG("leave ISR\n\n"); +} +#endif + +#if TIMER_1_EN +void TIMER_1_ISR_0(void) +{ + irq_handler(TIMER_0, TIMER_1_DEV_0, TIMER_1_DEV_1); +} +#endif + +static inline void irq_handler(tim_t timer, TIM_TypeDef *dev0, TIM_TypeDef *dev1) +{ + DEBUG("CNT: %08x SR/DIER: %08x\n", ((dev1->CNT<<16) | (0xffff & dev0->CNT)), + ((dev0->SR<<16) | (0xffff & dev0->DIER))); + + if ((dev0->SR & TIM_SR_CC1IF) && (dev0->DIER & TIM_DIER_CC1IE)) { + /* clear interrupt anyway */ + dev0->SR &= ~TIM_SR_CC1IF; + /* if higher 16bit also match */ + if (dev1->CNT >= dev1->CCR1) { + dev0->DIER &= ~TIM_DIER_CC1IE; + config[timer].cb(0); + } + DEBUG("channel 1 CCR: %08x\n", ((dev1->CCR1<<16) | (0xffff & dev0->CCR1))); + } + else if ((dev0->SR & TIM_SR_CC2IF) && (dev0->DIER & TIM_DIER_CC2IE)) { + /* clear interrupt anyway */ + dev0->SR &= ~TIM_SR_CC2IF; + /* if higher 16bit also match */ + if (dev1->CNT >= dev1->CCR2) { + dev0->DIER &= ~TIM_DIER_CC2IE; + config[timer].cb(1); + } + DEBUG("channel 2 CCR: %08x\n", ((dev1->CCR2<<16) | (0xffff & dev0->CCR2))); + } + else if ((dev0->SR & TIM_SR_CC3IF) && (dev0->DIER & TIM_DIER_CC3IE)) { + /* clear interrupt anyway */ + dev0->SR &= ~TIM_SR_CC3IF; + /* if higher 16bit also match */ + if (dev1->CNT >= dev1->CCR3) { + dev0->DIER &= ~TIM_DIER_CC3IE; + config[timer].cb(2); + } + DEBUG("channel 3 CCR: %08x\n", ((dev1->CCR3<<16) | (0xffff & dev0->CCR3))); + } + else if ((dev0->SR & TIM_SR_CC4IF) && (dev0->DIER & TIM_DIER_CC4IE)) { + /* clear interrupt anyway */ + dev0->SR &= ~TIM_SR_CC4IF; + /* if higher 16bit also match */ + if (dev1->CNT >= dev1->CCR4) { + dev0->DIER &= ~TIM_DIER_CC4IE; + config[timer].cb(3); + } + DEBUG("channel 4 CCR: %08x\n", ((dev1->CCR4<<16) | (0xffff & dev0->CCR4))); + } + else { + dev0->SR = 0; + } + if (sched_context_switch_request) { + thread_yield(); + } +} +#endif /* TIMER_0_EN || TIMER_1_EN */ diff --git a/cpu/stm32l1/periph/uart.c b/cpu/stm32l1/periph/uart.c new file mode 100644 index 0000000000..0de6490662 --- /dev/null +++ b/cpu/stm32l1/periph/uart.c @@ -0,0 +1,328 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @addtogroup driver_periph + * @{ + * + * @file + * @brief Low-level UART driver implementation + * + * @author Hauke Petersen + * + * @} + */ + +#include "cpu.h" +#include "sched.h" +#include "thread.h" +#include "periph_conf.h" +#include "periph/uart.h" + +/* guard file in case no UART device was specified */ +#if UART_NUMOF + +/** + * @brief Each UART device has to store two callbacks. + */ +typedef struct { + uart_rx_cb_t rx_cb; + uart_tx_cb_t tx_cb; + void *arg; +} uart_conf_t; + +/** + * @brief Unified interrupt handler for all UART devices + * + * @param uartnum the number of the UART that triggered the ISR + * @param uart the UART device that triggered the ISR + */ +static inline void irq_handler(uart_t uartnum, USART_TypeDef *uart); + +/** + * @brief Allocate memory to store the callback functions. + */ +static uart_conf_t uart_config[UART_NUMOF]; + +int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, uart_tx_cb_t tx_cb, void *arg) +{ + /* do basic initialization */ + int res = uart_init_blocking(uart, baudrate); + if (res < 0) { + return res; + } + + /* remember callback addresses */ + uart_config[uart].rx_cb = rx_cb; + uart_config[uart].tx_cb = tx_cb; + uart_config[uart].arg = arg; + + + /* enable receive interrupt */ + switch (uart) { +#if UART_0_EN + case UART_0: + NVIC_SetPriority(UART_0_IRQ, UART_IRQ_PRIO); + NVIC_EnableIRQ(UART_0_IRQ); + UART_0_DEV->CR1 |= USART_CR1_RXNEIE; + break; +#endif +#if UART_1_EN + case UART_1: + NVIC_SetPriority(UART_1_IRQ, UART_IRQ_PRIO); + NVIC_EnableIRQ(UART_1_IRQ); + UART_1_DEV->CR1 |= USART_CR1_RXNEIE; + break; +#endif +#if UART_2_EN + case UART_2: + NVIC_SetPriority(UART_2_IRQ, UART_IRQ_PRIO); + NVIC_EnableIRQ(UART_2_IRQ); + UART_2_DEV->CR1 |= USART_CR1_RXNEIE; + break; +#endif + } + + return 0; +} + +int uart_init_blocking(uart_t uart, uint32_t baudrate) +{ + USART_TypeDef *dev = 0; + GPIO_TypeDef *port = 0; + uint32_t tx_pin = 0; + uint32_t rx_pin = 0; + uint8_t af = 0; + float clk = 0; + float divider; + uint16_t mantissa; + uint8_t fraction; + + switch (uart) { +#if UART_0_EN + case UART_0: + dev = UART_0_DEV; + port = UART_0_PORT; + clk = UART_0_CLK; + tx_pin = UART_0_TX_PIN; + rx_pin = UART_0_RX_PIN; + af = UART_0_AF; + UART_0_CLKEN(); + UART_0_PORT_CLKEN(); + break; +#endif +#if UART_1_EN + case UART_1: + dev = UART_1_DEV; + port = UART_1_PORT; + clk = UART_1_CLK; + tx_pin = UART_1_TX_PIN; + rx_pin = UART_1_RX_PIN; + af = UART_1_AF; + UART_1_CLKEN(); + UART_1_PORT_CLKEN(); + break; +#endif +#if UART_2_EN + case UART_2: + dev = UART_2_DEV; + port = UART_2_PORT; + clk = UART_2_CLK; + tx_pin = UART_2_TX_PIN; + rx_pin = UART_2_RX_PIN; + af = UART_2_AF; + UART_2_CLKEN(); + UART_2_PORT_CLKEN(); + break; +#endif + default: + return -1; + } + + /* uart_configure RX and TX pins, set pin to use alternative function mode */ + port->MODER &= ~(3 << (rx_pin * 2) | 3 << (tx_pin * 2)); + port->MODER |= 2 << (rx_pin * 2) | 2 << (tx_pin * 2); + /* and assign alternative function */ + if (rx_pin < 8) { + port->AFR[0] &= ~(0xf << (rx_pin * 4)); + port->AFR[0] |= af << (rx_pin * 4); + } + else { + port->AFR[1] &= ~(0xf << ((rx_pin - 8) * 4)); + port->AFR[1] |= af << ((rx_pin - 8) * 4); + } + if (tx_pin < 8) { + port->AFR[0] &= ~(0xf << (tx_pin * 4)); + port->AFR[0] |= af << (tx_pin * 4); + } + else { + port->AFR[1] &= ~(0xf << ((tx_pin - 8) * 4)); + port->AFR[1] |= af << ((tx_pin - 8) * 4); + } + + /* uart_configure UART to mode 8N1 with given baudrate */ + divider = clk / (16 * baudrate); + mantissa = (uint16_t)divider; + fraction = (uint8_t)((divider - mantissa) * 16); + dev->BRR = ((mantissa & 0x0fff) << 4) | (0x0f & fraction); + + /* enable receive and transmit mode */ + dev->CR3 = 0; + dev->CR2 = 0; + dev->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE; + + return 0; +} + + +void uart_tx_begin(uart_t uart) +{ + switch (uart) { +#if UART_0_EN + case UART_0: + UART_0_DEV->CR1 |= USART_CR1_TXEIE; + break; +#endif +#if UART_1_EN + case UART_1: + UART_1_DEV->CR1 |= USART_CR1_TXEIE; + break; +#endif +#if UART_2_EN + case UART_2: + UART_2_DEV->CR1 |= USART_CR1_TXEIE; + break; +#endif + } +} + +int uart_write(uart_t uart, char data) +{ + USART_TypeDef *dev = 0; + + switch (uart) { +#if UART_0_EN + case UART_0: + dev = UART_0_DEV; + break; +#endif +#if UART_1_EN + case UART_1: + dev = UART_1_DEV; + break; +#endif +#if UART_2_EN + case UART_2: + dev = UART_2_DEV; + break; +#endif + default: + return -1; + } + + if (dev->SR & USART_SR_TXE) { + dev->DR = (uint8_t)data; + } + + return 0; +} + +int uart_read_blocking(uart_t uart, char *data) +{ + USART_TypeDef *dev = 0; + + switch (uart) { +#if UART_0_EN + case UART_0: + dev = UART_0_DEV; + break; +#endif +#if UART_1_EN + case UART_1: + dev = UART_1_DEV; + break; +#endif +#if UART_2_EN + case UART_2: + dev = UART_2_DEV; + break; +#endif + } + + while (!(dev->SR & USART_SR_RXNE)); + *data = (char)dev->DR; + + return 1; +} + +int uart_write_blocking(uart_t uart, char data) +{ + USART_TypeDef *dev = 0; + + switch (uart) { +#if UART_0_EN + case UART_0: + dev = UART_0_DEV; + break; +#endif +#if UART_1_EN + case UART_1: + dev = UART_1_DEV; + break; +#endif +#if UART_2_EN + case UART_2: + dev = UART_2_DEV; + break; +#endif + } + + while (!(dev->SR & USART_SR_TXE)); + dev->DR = (uint8_t)data; + + return 1; +} + +#if UART_0_EN +void UART_0_ISR(void) +{ + irq_handler(UART_0, UART_0_DEV); +} +#endif + +#if UART_1_EN +void UART_1_ISR(void) +{ + irq_handler(UART_1, UART_1_DEV); +} +#endif + +#if UART_2_EN +void UART_2_ISR(void) +{ + irq_handler(UART_2, UART_2_DEV); +} +#endif + +static inline void irq_handler(uint8_t uartnum, USART_TypeDef *dev) +{ + if (dev->SR & USART_SR_RXNE) { + char data = (char)dev->DR; + uart_config[uartnum].rx_cb(uart_config[uartnum].arg, data); + } + else if (dev->SR & USART_SR_TXE) { + if (uart_config[uartnum].tx_cb(uart_config[uartnum].arg) == 0) { + dev->CR1 &= ~(USART_CR1_TXEIE); + } + } + if (sched_context_switch_request) { + thread_yield(); + } +} + +#endif /* UART_NUMOF */ diff --git a/cpu/stm32l1/startup.c b/cpu/stm32l1/startup.c new file mode 100644 index 0000000000..83f453badb --- /dev/null +++ b/cpu/stm32l1/startup.c @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32l1 + * @{ + * + * @file startup.c + * @brief Startup code and interrupt vector definition + * + * @author Hauke Petersen + * @author Thomas Eichinger + * + * @} + */ + +#include +#include "crash.h" + + +/** + * memory markers as defined in the linker script + */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + + +/** + * @brief functions for initializing the board, std-lib and kernel + */ +extern void board_init(void); +extern void kernel_init(void); +extern void __libc_init_array(void); + +/** + * @brief This function is the entry point after a system reset + * + * After a system reset, the following steps are necessary and carried out: + * 1. load data section from flash to ram + * 2. overwrite uninitialized data section (BSS) with zeros + * 3. initialize the newlib + * 4. initialize the board (sync clock, setup std-IO) + * 5. initialize and start RIOTs kernel + */ +void reset_handler(void) +{ + uint32_t *dst; + uint32_t *src = &_etext; + + /* load data section from flash to ram */ + for (dst = &_srelocate; dst < &_erelocate; ) { + *(dst++) = *(src++); + } + + /* default bss section to zero */ + for (dst = &_szero; dst < &_ezero; ) { + *(dst++) = 0; + } + + /* initialize the board and startup the kernel */ + board_init(); + /* initialize std-c library (this should be done after board_init) */ + __libc_init_array(); + /* startup the kernel */ + kernel_init(); +} + +/** + * @brief Default handler is called in case no interrupt handler was defined + */ +void dummy_handler(void) +{ + core_panic(DUMMY_HANDLER, "DUMMY HANDLER"); + while (1) {asm ("nop");} +} + +void isr_nmi(void) +{ + while (1) {asm ("nop");} +} + +void isr_mem_manage(void) +{ + while (1) {asm ("nop");} +} + +void isr_debug_mon(void) +{ + while (1) {asm ("nop");} +} + +void isr_hard_fault(void) +{ + core_panic(HARD_FAULT, "HARD FAULT"); + while (1) {asm ("nop");} +} + +void isr_bus_fault(void) +{ + core_panic(BUS_FAULT, "BUS FAULT"); + while (1) {asm ("nop");} +} + +void isr_usage_fault(void) +{ + core_panic(USAGE_FAULT, "USAGE FAULT"); + while (1) {asm ("nop");} +} + +/* Cortex-M specific interrupt vectors */ +void isr_svc(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pendsv(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_systick(void) __attribute__ ((weak, alias("dummy_handler"))); + +/* stm32f1 specific interrupt vector */ +void isr_wwdg(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_pvd(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tamper_stamp(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_rtc_wkup(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_flash(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_rcc(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti0(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti4(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch4(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch5(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch6(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma1_ch7(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_adc1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usb_hp(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usb_lp(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dac(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_comp(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti9_5(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_lcd(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim9(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim10(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim11(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim4(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c1_ev(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c1_er(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c2_ev(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_i2c2_er(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_spi1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_spi2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usart1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usart2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usart3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_exti15_10(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_rtc_alarm(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_usb_fs_wkup(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim6(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim7(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_sdio(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_tim5(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_spi3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart4(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_uart5(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma2_ch1(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma2_ch2(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma2_ch3(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma2_ch4(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_dma2_ch5(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_aes(void) __attribute__ ((weak, alias("dummy_handler"))); +void isr_comp_acq(void) __attribute__ ((weak, alias("dummy_handler"))); + + +/* interrupt vector table */ +__attribute__ ((section(".vectors"))) +const void *interrupt_vector[] = { + /* Stack pointer */ + (void*) (&_estack), /* pointer to the top of the empty stack */ + /* Cortex-M handlers */ + (void*) reset_handler, /* entry point of the program */ + (void*) isr_nmi, /* non maskable interrupt handler */ + (void*) isr_hard_fault, /* if you end up here its not good */ + (void*) isr_mem_manage, /* memory controller interrupt */ + (void*) isr_bus_fault, /* also not good to end up here */ + (void*) isr_usage_fault, /* autsch */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) (0UL), /* Reserved */ + (void*) isr_svc, /* system call interrupt */ + (void*) isr_debug_mon, /* debug interrupt */ + (void*) (0UL), /* Reserved */ + (void*) isr_pendsv, /* pendSV interrupt, used for task switching in RIOT */ + (void*) isr_systick, /* SysTick interrupt, not used in RIOT */ + /* STM specific peripheral handlers */ + (void*) isr_wwdg, + (void*) isr_pvd, + (void*) isr_tamper_stamp, + (void*) isr_rtc_wkup, + (void*) isr_flash, + (void*) isr_rcc, + (void*) isr_exti0, + (void*) isr_exti1, + (void*) isr_exti2, + (void*) isr_exti3, + (void*) isr_exti4, + (void*) isr_dma1_ch1, + (void*) isr_dma1_ch2, + (void*) isr_dma1_ch3, + (void*) isr_dma1_ch4, + (void*) isr_dma1_ch5, + (void*) isr_dma1_ch6, + (void*) isr_dma1_ch7, + (void*) isr_adc1, + (void*) isr_usb_hp, + (void*) isr_usb_lp, + (void*) isr_dac, + (void*) isr_comp, + (void*) isr_exti9_5, + (void*) isr_lcd, + (void*) isr_tim9, + (void*) isr_tim10, + (void*) isr_tim11, + (void*) isr_tim2, + (void*) isr_tim3, + (void*) isr_tim4, + (void*) isr_i2c1_ev, + (void*) isr_i2c1_er, + (void*) isr_i2c2_ev, + (void*) isr_i2c2_er, + (void*) isr_spi1, + (void*) isr_spi2, + (void*) isr_usart1, + (void*) isr_usart2, + (void*) isr_usart3, + (void*) isr_exti15_10, + (void*) isr_rtc_alarm, + (void*) isr_usb_fs_wkup, + (void*) isr_tim6, + (void*) isr_tim7, + (void*) isr_sdio, + (void*) isr_tim5, + (void*) isr_spi3, + (void*) isr_uart4, + (void*) isr_uart5, + (void*) isr_dma2_ch1, + (void*) isr_dma2_ch2, + (void*) isr_dma2_ch3, + (void*) isr_dma2_ch4, + (void*) isr_dma2_ch5, + (void*) isr_aes, + (void*) isr_comp_acq, +}; diff --git a/cpu/stm32l1/stm32l152ret6_linkerscript.ld b/cpu/stm32l1/stm32l152ret6_linkerscript.ld new file mode 100644 index 0000000000..ae545ee326 --- /dev/null +++ b/cpu/stm32l1/stm32l152ret6_linkerscript.ld @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following condition is met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.)*/ + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram (xrw) : ORIGIN = 0x20000000, LENGTH = 80K +} + +/* The stack size used by the application. NOTE: you need to adjust */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x200 ; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD) : + { + . = ALIGN(4); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(4); + _estack = .; + } > ram + + /* heap section */ + . = ALIGN(4); + _sheap = . ; + _eheap = ORIGIN(ram) + LENGTH(ram); +} diff --git a/cpu/stm32l1/syscalls.c b/cpu/stm32l1/syscalls.c new file mode 100644 index 0000000000..3c60a16cf4 --- /dev/null +++ b/cpu/stm32l1/syscalls.c @@ -0,0 +1,347 @@ +/* + * Copyright (C) 2014 Freie Universität Berlin + * + * This file is subject to the terms and conditions of the GNU Lesser General + * Public License v2.1. See the file LICENSE in the top level directory for more + * details. + */ + +/** + * @ingroup cpu_stm32l1 + * @{ + * + * @file syscalls.c + * @brief NewLib system calls implementations for stm32l1 + * + * @author Michael Baar + * @author Stefan Pfeiffer + * @author Hauke Petersen + * @author Thomas Eichinger + * + * @} + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "board.h" +#include "thread.h" +#include "kernel.h" +#include "mutex.h" +#include "ringbuffer.h" +#include "irq.h" +#include "periph/uart.h" + +#ifdef MODULE_UART0 +#include "board_uart0.h" +#endif + +/** + * manage the heap + */ +extern char _sheap; /* start of the heap */ +extern char _eheap; /* end of the heap */ +caddr_t heap_top = (caddr_t)&_sheap + 4; + +#ifndef MODULE_UART0 +/** + * @brief use mutex for waiting on incoming UART chars + */ +static mutex_t uart_rx_mutex; +static char rx_buf_mem[STDIO_RX_BUFSIZE]; +static ringbuffer_t rx_buf; +#endif + +/** + * @brief Receive a new character from the UART and put it into the receive buffer + */ +void rx_cb(void *arg, char data) +{ +#ifndef MODULE_UART0 + (void)arg; + + ringbuffer_add_one(&rx_buf, data); + mutex_unlock(&uart_rx_mutex); +#else + if (uart0_handler_pid) { + uart0_handle_incoming(data); + + uart0_notify_thread(); + } +#endif +} + +/** + * @brief Initialize NewLib, called by __libc_init_array() from the startup script + */ +void _init(void) +{ +#ifndef MODULE_UART0 + mutex_init(&uart_rx_mutex); + ringbuffer_init(&rx_buf, rx_buf_mem, STDIO_RX_BUFSIZE); +#endif + uart_init(STDIO, STDIO_BAUDRATE, rx_cb, 0, 0); +} + +/** + * @brief Free resources on NewLib de-initialization, not used for RIOT + */ +void _fini(void) +{ + /* nothing to do here */ +} + +/** + * @brief Exit a program without cleaning up files + * + * If your system doesn't provide this, it is best to avoid linking with subroutines that + * require it (exit, system). + * + * @param n the exit code, 0 for all OK, >0 for not OK + */ +void _exit(int n) +{ + printf("#! exit %i: resetting\n", n); + NVIC_SystemReset(); + while(1); +} + +/** + * @brief Allocate memory from the heap. + * + * The current heap implementation is very rudimentary, it is only able to allocate + * memory. But it does not + * - check if the returned address is valid (no check if the memory very exists) + * - have any means to free memory again + * + * TODO: check if the requested memory is really available + * + * @return [description] + */ +caddr_t _sbrk_r(struct _reent *r, ptrdiff_t incr) +{ + unsigned int state = disableIRQ(); + caddr_t res = heap_top; + + if (((incr > 0) && ((heap_top + incr > &_eheap) || (heap_top + incr < res))) || + ((incr < 0) && ((heap_top + incr < &_sheap) || (heap_top + incr > res)))) { + r->_errno = ENOMEM; + res = (void *) -1; + } + else { + heap_top += incr; + } + + restoreIRQ(state); + return res; +} + +/** + * @brief Get the process-ID of the current thread + * + * @return the process ID of the current thread + */ +int _getpid(void) +{ + return sched_active_thread->pid; +} + +/** + * @brief Send a signal to a given thread + * + * @param r TODO + * @param pid TODO + * @param sig TODO + * + * @return TODO + */ +__attribute__ ((weak)) +int _kill_r(struct _reent *r, int pid, int sig) +{ + r->_errno = ESRCH; /* not implemented yet */ + return -1; +} + +/** + * @brief Send a signal to a given thread (non-reentrant syscall) + * + * @param r TODO + * @param pid TODO + * @param sig TODO + * + * @return TODO + */ +__attribute__ ((weak)) +int _kill(int pid, int sig) +{ + errno = ESRCH; /* not implemented yet */ + return -1; +} + +/** + * @brief Open a file + * + * @param r TODO + * @param name TODO + * @param mode TODO + * + * @return TODO + */ +int _open_r(struct _reent *r, const char *name, int mode) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Read from a file + * + * All input is read from UART_0. The function will block until a byte is actually read. + * + * Note: the read function does not buffer - data will be lost if the function is not + * called fast enough. + * + * TODO: implement more sophisticated read call. + * + * @param r TODO + * @param fd TODO + * @param buffer TODO + * @param int TODO + * + * @return TODO + */ +int _read_r(struct _reent *r, int fd, void *buffer, unsigned int count) +{ +#ifndef MODULE_UART0 + while (rx_buf.avail == 0) { + mutex_lock(&uart_rx_mutex); + } + return ringbuffer_get(&rx_buf, (char*)buffer, rx_buf.avail); +#else + char *res = (char*)buffer; + res[0] = (char)uart0_readc(); + return 1; +#endif +} + +/** + * @brief Write characters to a file + * + * All output is currently directed to UART_0, independent of the given file descriptor. + * The write call will further block until the byte is actually written to the UART. + * + * TODO: implement more sophisticated write call. + * + * @param r TODO + * @param fd TODO + * @param data TODO + * @param int TODO + * + * @return TODO + */ +int _write_r(struct _reent *r, int fd, const void *data, unsigned int count) +{ + char *c = (char*)data; + for (int i = 0; i < count; i++) { + uart_write_blocking(UART_0, c[i]); + } + return count; +} + +/** + * @brief Close a file + * + * @param r TODO + * @param fd TODO + * + * @return TODO + */ +int _close_r(struct _reent *r, int fd) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Set position in a file + * + * @param r TODO + * @param fd TODO + * @param pos TODO + * @param dir TODO + * + * @return TODO + */ +_off_t _lseek_r(struct _reent *r, int fd, _off_t pos, int dir) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Status of an open file + * + * @param r TODO + * @param fd TODO + * @param stat TODO + * + * @return TODO + */ +int _fstat_r(struct _reent *r, int fd, struct stat * st) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Status of a file (by name) + * + * @param r TODO + * @param name TODO + * @param stat TODO + * + * @return TODO + */ +int _stat_r(struct _reent *r, char *name, struct stat *st) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} + +/** + * @brief Query whether output stream is a terminal + * + * @param r TODO + * @param fd TODO + * + * @return TODO + */ +int _isatty_r(struct _reent *r, int fd) +{ + r->_errno = 0; + if(fd == STDOUT_FILENO || fd == STDERR_FILENO) { + return 1; + } + else { + return 0; + } +} + +/** + * @brief Remove a file's directory entry + * + * @param r TODO + * @param path TODO + * + * @return TODO + */ +int _unlink_r(struct _reent *r, char* path) +{ + r->_errno = ENODEV; /* not implemented yet */ + return -1; +} diff --git a/dist/tools/licenses/patterns/mcd-st-liberty b/dist/tools/licenses/patterns/mcd-st-liberty new file mode 100644 index 0000000000..0bfded7e3f --- /dev/null +++ b/dist/tools/licenses/patterns/mcd-st-liberty @@ -0,0 +1 @@ +Licensed under MCD-ST Liberty SW License Agreement V2, \(the "License"\); You may not use this file except in compliance with the License\. You may obtain a copy of the License at: http: www\.st\.com software_license_agreement_liberty_v2 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied\. See the License for the specific language governing permissions and limitations under the License\. \ No newline at end of file diff --git a/doc/doxygen/riot.doxyfile b/doc/doxygen/riot.doxyfile index 8c6614ed13..fe636757ef 100644 --- a/doc/doxygen/riot.doxyfile +++ b/doc/doxygen/riot.doxyfile @@ -825,6 +825,7 @@ EXCLUDE_PATTERNS = */board/*/tools/* \ */boards/*/include/periph_conf.h \ */cpu/x86/include/x86_pci.h \ */cpu/sam3x8e/include/sam3x8e.h \ + */cpu/stm32l1/include/stm32l1xx.h \ # The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names