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boards: add support for SODAQ Autonomo
The following features were tested (briefly): * UART (the first) * I2C using a BMP180 on a SODAQ TPH board * SPI0, connected to the on-board serial data flash (only DevID was read using the periph_spi test program) * xtimer is working (it's the same code as in samr21) boards/sodaq-autonomo: Disable the "big" unittests because it does not fit
This commit is contained in:
parent
6aa346fbad
commit
076d5bda11
3
boards/sodaq-autonomo/Makefile
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3
boards/sodaq-autonomo/Makefile
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@ -0,0 +1,3 @@
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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3
boards/sodaq-autonomo/Makefile.dep
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3
boards/sodaq-autonomo/Makefile.dep
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@ -0,0 +1,3 @@
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ifneq (,$(filter saul_default,$(USEMODULE)))
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USEMODULE += saul_gpio
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endif
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16
boards/sodaq-autonomo/Makefile.features
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16
boards/sodaq-autonomo/Makefile.features
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@ -0,0 +1,16 @@
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_cpuid
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FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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# Various other features (if any)
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FEATURES_PROVIDED += cpp
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# The board MPU family (used for grouping by the CI system)
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FEATURES_MCU_GROUP = cortex_m0_2
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31
boards/sodaq-autonomo/Makefile.include
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31
boards/sodaq-autonomo/Makefile.include
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@ -0,0 +1,31 @@
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# define the cpu used by SODAQ Autonomo board
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export CPU = samd21
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export CPU_MODEL = samd21j18a
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CFLAGS += -D__SAMD21J18A__
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# set default port depending on operating system
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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export OFLAGS = -O binary
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# setup the boards dependencies
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include $(RIOTBOARD)/$(BOARD)/Makefile.dep
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# setup serial terminal
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include $(RIOTBOARD)/Makefile.include.serial
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# Add board selector (USB serial) to OpenOCD options if specified.
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# Use /dist/tools/usb-serial/list-ttys.sh to find out serial number.
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# Usage: SERIAL="AAA..." BOARD="sodaq-autonomo" make flash
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ifneq (,$(SERIAL))
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export OPENOCD_EXTRA_INIT += "-c cmsis_dap_serial $(SERIAL)"
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SERIAL_TTY = $(shell $(RIOTBASE)/dist/tools/usb-serial/find-tty.sh $(SERIAL))
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ifeq (,$(SERIAL_TTY))
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$(error Did not find a device with serial $(SERIAL))
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endif
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PORT_LINUX := $(SERIAL_TTY)
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endif
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# this board uses openocd
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include $(RIOTBOARD)/Makefile.include.openocd
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32
boards/sodaq-autonomo/board.c
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32
boards/sodaq-autonomo/board.c
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@ -0,0 +1,32 @@
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/*
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* Copyright (C) 2016 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-autonomo
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* @{
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*
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* @file
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* @brief Board specific implementations for the SODAQ Autonomo
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* Pro board
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*
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* @author Kees Bakker <kees@sodaq.com>
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*
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* @}
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*/
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#include "board.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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/* initialize the on-board LED */
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gpio_init(LED0_PIN, GPIO_OUT);
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/* initialize the CPU */
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cpu_init();
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}
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1
boards/sodaq-autonomo/dist/openocd.cfg
vendored
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1
boards/sodaq-autonomo/dist/openocd.cfg
vendored
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@ -0,0 +1 @@
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source [find board/sodaq_autonomo.cfg]
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64
boards/sodaq-autonomo/include/board.h
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64
boards/sodaq-autonomo/include/board.h
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@ -0,0 +1,64 @@
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/*
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* Copyright (C) 2016 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_sodaq-autonomo SODAQ Autonomo
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* @ingroup boards
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* @brief Support for the SODAQ Autonomo board.
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* @{
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*
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* @file
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* @brief Board specific definitions for the SODAQ Autonomo board
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include "cpu.h"
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#include "periph_conf.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief xtimer configuration
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* @{
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*/
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#define XTIMER TIMER_1
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#define XTIMER_CHAN (0)
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/** @} */
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/**
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* @brief LED pin definitions and handlers
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* @{
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*/
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#define LED0_PIN GPIO_PIN(PA, 18)
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#define LED_PORT PORT->Group[PA]
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#define LED0_MASK (1 << 18)
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#define LED0_ON (LED_PORT.OUTSET.reg = LED0_MASK)
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#define LED0_OFF (LED_PORT.OUTCLR.reg = LED0_MASK)
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#define LED0_TOGGLE (LED_PORT.OUTTGL.reg = LED0_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */
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/** @} */
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46
boards/sodaq-autonomo/include/gpio_params.h
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46
boards/sodaq-autonomo/include/gpio_params.h
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/*
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* Copyright (C) 2016 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-autonomo
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* @{
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*
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* @file
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* @brief Board specific configuration of direct mapped GPIOs
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef GPIO_PARAMS_H
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#define GPIO_PARAMS_H
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#include "board.h"
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#include "saul/periph.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief GPIO pin configuration
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*/
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static const saul_gpio_params_t saul_gpio_params[] =
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{
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{
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.name = "LED(green)",
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.pin = LED0_PIN,
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.mode = GPIO_OUT
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},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_PARAMS_H */
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/** @} */
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232
boards/sodaq-autonomo/include/periph_conf.h
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232
boards/sodaq-autonomo/include/periph_conf.h
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/*
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* Copyright (C) 2016 Kees Bakker, SODAQ
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_sodaq-autonomo
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* @{
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*
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* @file
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* @brief Configuration of CPU peripherals for the SODAQ Autonomo board
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*
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* @author Kees Bakker <kees@sodaq.com>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#include <stdint.h>
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#include "cpu.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief External oscillator and clock configuration
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*
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* For selection of the used CORECLOCK, we have implemented two choices:
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*
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* - usage of the PLL fed by the internal 8MHz oscillator divided by 8
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* - usage of the internal 8MHz oscillator directly, divided by N if needed
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*
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*
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* The PLL option allows for the usage of a wider frequency range and a more
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* stable clock with less jitter. This is why we use this option as default.
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*
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* The target frequency is computed from the PLL multiplier and the PLL divisor.
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* Use the following formula to compute your values:
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*
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* CORECLOCK = ((PLL_MUL + 1) * 1MHz) / PLL_DIV
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*
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* NOTE: The PLL circuit does not run with less than 32MHz while the maximum PLL
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* frequency is 96MHz. So PLL_MULL must be between 31 and 95!
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*
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*
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* The internal Oscillator used directly can lead to a slightly better power
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* efficiency to the cost of a less stable clock. Use this option when you know
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* what you are doing! The actual core frequency is adjusted as follows:
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*
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* CORECLOCK = 8MHz / DIV
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*
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* NOTE: A core clock frequency below 1MHz is not recommended
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*
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* @{
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*/
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#define CLOCK_USE_PLL (1)
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#if CLOCK_USE_PLL
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/* edit these values to adjust the PLL output frequency */
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#define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
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#define CLOCK_PLL_DIV (1U) /* adjust to your needs */
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/* generate the actual used core clock frequency */
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#define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
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#else
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/* edit this value to your needs */
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#define CLOCK_DIV (1U)
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/* generate the actual core clock frequency */
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#define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
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#endif
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/** @} */
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/**
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* @name Timer peripheral configuration
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* @{
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*/
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#define TIMER_NUMOF (2U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TC3->COUNT16
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#define TIMER_0_CHANNELS 2
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#define TIMER_0_MAX_VALUE (0xffff)
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#define TIMER_0_ISR isr_tc3
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/* Timer 1 configuration */
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#define TIMER_1_DEV TC4->COUNT32
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#define TIMER_1_CHANNELS 2
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#define TIMER_1_MAX_VALUE (0xffffffff)
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#define TIMER_1_ISR isr_tc4
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/** @} */
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/**
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* @name UART configuration
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* @{
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* See Table 6.1 of the SAM D21 Datasheet
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*/
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static const uart_conf_t uart_config[] = {
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/* device, RX pin, TX pin, mux, RX pad, TX pad */
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{&SERCOM0->USART, GPIO_PIN(PA,9), GPIO_PIN(PA,10), GPIO_MUX_C, SERCOM_RX_PAD_1, UART_TX_PAD_2},
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{&SERCOM5->USART, GPIO_PIN(PB,31), GPIO_PIN(PB,30), GPIO_MUX_D, SERCOM_RX_PAD_1, UART_TX_RTS_CTS_PAD_0_2_3},
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{&SERCOM4->USART, GPIO_PIN(PB,13), GPIO_PIN(PA,14), GPIO_MUX_C, SERCOM_RX_PAD_1, UART_TX_PAD_2},
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{&SERCOM1->USART, GPIO_PIN(PA,17), GPIO_PIN(PA,18), GPIO_MUX_C, SERCOM_RX_PAD_1, UART_TX_PAD_2},
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};
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/* interrupt function name mapping */
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#define UART_0_ISR isr_sercom0
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#define UART_1_ISR isr_sercom5
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#define UART_2_ISR isr_sercom4
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#define UART_3_ISR isr_sercom1
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 3
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/* for compatibility with test application */
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#define PWM_0_CHANNELS PWM_MAX_CHANNELS
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#define PWM_1_CHANNELS PWM_MAX_CHANNELS
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/* PWM device configuration */
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static const pwm_conf_t pwm_config[] = {
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#if PWM_0_EN
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{TCC1, {
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/* GPIO pin, MUX value, TCC channel */
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{ GPIO_PIN(PA, 6), GPIO_MUX_E, 0 },
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{ GPIO_PIN(PA, 7), GPIO_MUX_E, 1 },
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{ GPIO_UNDEF, (gpio_mux_t)0, 2 }
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}},
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#endif
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#if PWM_1_EN
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{TCC0, {
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/* GPIO pin, MUX value, TCC channel */
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{ GPIO_PIN(PA, 16), GPIO_MUX_F, 0 },
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{ GPIO_PIN(PA, 18), GPIO_MUX_F, 2 },
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{ GPIO_PIN(PA, 19), GPIO_MUX_F, 3 }
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}}
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#endif
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};
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/* number of devices that are actually defined */
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#define PWM_NUMOF (2U)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1)
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#define SPI_0_EN 1
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#define SPI_1_EN 0
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/* SPI0 */
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#define SPI_0_DEV SERCOM3->SPI
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#define SPI_IRQ_0 SERCOM3_IRQn
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#define SPI_0_GCLK_ID SERCOM3_GCLK_ID_CORE
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/* SPI 0 pin configuration */
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#define SPI_0_SCLK GPIO_PIN(PA, 21)
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#define SPI_0_SCLK_MUX GPIO_MUX_D
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#define SPI_0_MISO GPIO_PIN(PA, 22)
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#define SPI_0_MISO_MUX GPIO_MUX_C
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#define SPI_0_MISO_PAD SERCOM_RX_PAD_0
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#define SPI_0_MOSI GPIO_PIN(PA, 20)
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#define SPI_0_MOSI_MUX GPIO_MUX_D
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#define SPI_0_MOSI_PAD SPI_PAD_2_SCK_3
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// How/where do we define SS?
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#define SPI_0_SS GPIO_PIN(PA, 23)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_1_EN 0
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#define I2C_2_EN 0
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#define I2C_3_EN 0
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#define I2C_IRQ_PRIO 1
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#define I2C_0_DEV SERCOM2->I2CM
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#define I2C_0_IRQ SERCOM2_IRQn
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#define I2C_0_ISR isr_sercom2
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/* I2C 0 GCLK */
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#define I2C_0_GCLK_ID SERCOM2_GCLK_ID_CORE
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#define I2C_0_GCLK_ID_SLOW SERCOM2_GCLK_ID_SLOW
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/* I2C 0 pin configuration */
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#define I2C_0_SDA GPIO_PIN(PA, 12)
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#define I2C_0_SCL GPIO_PIN(PA, 13)
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#define I2C_0_MUX GPIO_MUX_C
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/**
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* @name RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1U)
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#define RTC_DEV RTC->MODE2
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/** @} */
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/**
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* @name RTT configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTT_DEV RTC->MODE0
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#define RTT_IRQ RTC_IRQn
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#define RTT_IRQ_PRIO 10
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#define RTT_ISR isr_rtc
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
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#define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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@ -27,6 +27,8 @@ extern "C" {
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#include "cmsis/samr21/include/samr21g18a.h"
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#elif defined(__SAMR21E18A__) || defined(__ATSAMR21E18A__)
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#include "cmsis/samr21/include/samr21e18a.h"
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#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
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#include "cmsis/samd21/include/samd21j18a.h"
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#else
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#error "Unsupported SAM0 variant."
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#endif
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27
cpu/samd21/ldscripts/samd21j18a.ld
Normal file
27
cpu/samd21/ldscripts/samd21j18a.ld
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/*
|
||||
* Copyright (C) 2015, 2016 Freie Universität Berlin
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup cpu_samd21
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Memory definitions for the SAMD21J18A
|
||||
*
|
||||
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
|
||||
*
|
||||
* @}
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
INCLUDE cortexm_base.ld
|
@ -7,7 +7,7 @@ BOARD_INSUFFICIENT_MEMORY := airfy-beacon cc2650stk chronos msb-430 msb-430h pca
|
||||
nucleo-f334 yunjia-nrf51822 samr21-xpro \
|
||||
arduino-mega2560 airfy-beacon nrf51dongle nrf6310 \
|
||||
weio waspmote-pro nucleo-f072 arduino-uno \
|
||||
arduino-duemilanove
|
||||
arduino-duemilanove sodaq-autonomo
|
||||
|
||||
USEMODULE += embunit
|
||||
|
||||
@ -25,7 +25,7 @@ ARM_CORTEX_M_BOARDS := airfy-beacon arduino-due cc2538dk ek-lm4f120xl f4vi1 fox
|
||||
nucleo-f091 nucleo-f303 nucleo-f334 nucleo-f401 nucleo-l1 openmote-cc2538 \
|
||||
pba-d-01-kw2x pca10000 pca10005 remote saml21-xpro samr21-xpro slwstk6220a \
|
||||
spark-core stm32f0discovery stm32f3discovery stm32f4discovery udoo weio \
|
||||
yunjia-nrf51822
|
||||
yunjia-nrf51822 sodaq-autonomo
|
||||
DISABLE_TEST_FOR_ARM_CORTEX_M := tests-relic
|
||||
|
||||
AVR_BOARDS := arduino-mega2560 waspmote-pro arduino-uno arduino-duemilanove
|
||||
|
Loading…
Reference in New Issue
Block a user