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cpu/esp32: add ESP32-S2 support in peripheral drivers

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This commit is contained in:
Gunar Schorcht 2022-06-14 13:27:31 +02:00
parent dac197031e
commit 06bb755c03
9 changed files with 288 additions and 7 deletions
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124
cpu/esp32/periph/adc_arch_esp32s2.c Normal file
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@ -0,0 +1,124 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser General
* Public License v2.1. See the file LICENSE in the top level directory for more
* details.
*/
/**
* @ingroup cpu_esp32
* @{
*
* @file
* @brief Architecture-specific ADC/DAC definitions for ESP32-S2 variant (family)
*
* @author Gunar Schorcht <gunar@schorcht.net>
*
* @}
*/
#include "board.h"
#include "adc_arch_private.h"
#include "esp_common.h"
#include "soc/adc_channel.h"
#define ENABLE_DEBUG 0
#include "debug.h"
/**
* @brief ADC hardware descriptor table (for internal use only)
*
* Reference: Technical Reference Manual, Section 5.12 Table 38
* https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf
*
* @note The index of entries in the table MUST correspond to the
* RTCIO GPIO number.
*/
const _adc_hw_desc_t _adc_hw[] = {
/* rtcio, gpio, adc_ctrl, adc_channel, pad_name */
{ RTCIO_GPIO(0), GPIO0, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO0" },
{ RTCIO_GPIO(1), ADC1_CHANNEL_0_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_0, "TOUCH1" },
{ RTCIO_GPIO(2), ADC1_CHANNEL_1_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_1, "TOUCH2" },
{ RTCIO_GPIO(3), ADC1_CHANNEL_2_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_2, "TOUCH3" },
{ RTCIO_GPIO(4), ADC1_CHANNEL_3_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_3, "TOUCH4" },
{ RTCIO_GPIO(5), ADC1_CHANNEL_4_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_4, "TOUCH5" },
{ RTCIO_GPIO(6), ADC1_CHANNEL_5_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_5, "TOUCH6" },
{ RTCIO_GPIO(7), ADC1_CHANNEL_6_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_6, "TOUCH7" },
{ RTCIO_GPIO(8), ADC1_CHANNEL_7_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_7, "TOUCH8" },
{ RTCIO_GPIO(9), ADC1_CHANNEL_8_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_8, "TOUCH9" },
{ RTCIO_GPIO(10), ADC1_CHANNEL_9_GPIO_NUM, ADC_UNIT_1, ADC_CHANNEL_9, "TOUCH10" },
{ RTCIO_GPIO(11), ADC2_CHANNEL_0_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_0, "TOUCH11" },
{ RTCIO_GPIO(12), ADC2_CHANNEL_1_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_1, "TOUCH12" },
{ RTCIO_GPIO(13), ADC2_CHANNEL_2_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_2, "TOUCH13" },
{ RTCIO_GPIO(14), ADC2_CHANNEL_3_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_3, "TOUCH14" },
{ RTCIO_GPIO(15), ADC2_CHANNEL_4_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_4, "XTAL_32K_P" },
{ RTCIO_GPIO(16), ADC2_CHANNEL_5_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_5, "XTAL_32K_N" },
{ RTCIO_GPIO(17), ADC2_CHANNEL_6_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_6, "DAC1" },
{ RTCIO_GPIO(18), ADC2_CHANNEL_7_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_7, "DAC2" },
{ RTCIO_GPIO(19), ADC2_CHANNEL_8_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_8, "USB_D-" },
{ RTCIO_GPIO(20), ADC2_CHANNEL_9_GPIO_NUM, ADC_UNIT_2, ADC_CHANNEL_9, "USB_D+" },
{ RTCIO_GPIO(21), GPIO21, ADC_UNIT_MAX, ADC_CHANNEL_MAX, "GPIO21" },
};
/**
* @brief GPIO to RTC IO map (for internal use only)
*
* Reference: Technical Reference Manual, Section 5.12 Table 38
* https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf
*/
const gpio_t _gpio_rtcio_map[] = {
RTCIO_GPIO(0), /* GPIO0 */
RTCIO_GPIO(1), /* GPIO1 TOUCH1 */
RTCIO_GPIO(2), /* GPIO2 TOUCH2 */
RTCIO_GPIO(3), /* GPIO3 TOUCH3 */
RTCIO_GPIO(4), /* GPIO4 TOUCH4 */
RTCIO_GPIO(5), /* GPIO5 TOUCH5 */
RTCIO_GPIO(6), /* GPIO6 TOUCH6 */
RTCIO_GPIO(7), /* GPIO7 TOUCH7 */
RTCIO_GPIO(8), /* GPIO8 TOUCH8 */
RTCIO_GPIO(9), /* GPIO9 TOUCH9 */
RTCIO_GPIO(10), /* GPIO10 TOUCH10 */
RTCIO_GPIO(11), /* GPIO11 TOUCH11 */
RTCIO_GPIO(12), /* GPIO12 TOUCH12 */
RTCIO_GPIO(13), /* GPIO13 TOUCH13 */
RTCIO_GPIO(14), /* GPIO14 TOUCH14 */
RTCIO_GPIO(15), /* GPIO15 XTAL_32K_P */
RTCIO_GPIO(16), /* GPIO16 XTAL_32K_N */
RTCIO_GPIO(17), /* GPIO17 DAC1 */
RTCIO_GPIO(18), /* GPIO18 DAC2 */
RTCIO_GPIO(19), /* GPIO19 USB_D- */
RTCIO_GPIO(20), /* GPIO20 USB_D+ */
RTCIO_GPIO(21), /* GPIO21 */
RTCIO_NA, /* GPIO22 */
RTCIO_NA, /* GPIO23 */
RTCIO_NA, /* GPIO24 */
RTCIO_NA, /* GPIO25 */
RTCIO_NA, /* GPIO26 */
RTCIO_NA, /* GPIO27 */
RTCIO_NA, /* GPIO28 */
RTCIO_NA, /* GPIO29 */
RTCIO_NA, /* GPIO30 */
RTCIO_NA, /* GPIO31 */
RTCIO_NA, /* GPIO32 */
RTCIO_NA, /* GPIO33 */
RTCIO_NA, /* GPIO34 */
RTCIO_NA, /* GPIO35 */
RTCIO_NA, /* GPIO36 */
RTCIO_NA, /* GPIO37 */
RTCIO_NA, /* GPIO38 */
RTCIO_NA, /* GPIO39 */
RTCIO_NA, /* GPIO40 */
RTCIO_NA, /* GPIO41 */
RTCIO_NA, /* GPIO42 */
RTCIO_NA, /* GPIO43 */
RTCIO_NA, /* GPIO44 */
RTCIO_NA, /* GPIO45 */
RTCIO_NA, /* GPIO46 */
};
_Static_assert(ARRAY_SIZE(_adc_hw) == SOC_RTCIO_PIN_COUNT,
"size of _adc_hw does not match SOC_RTCIO_PIN_COUNT");
_Static_assert(ARRAY_SIZE(_gpio_rtcio_map) == SOC_GPIO_PIN_COUNT,
"size of _gpio_rtcio_map does not match SOC_GPIO_PIN_COUNT");

2
cpu/esp32/periph/can.c
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@ -637,7 +637,7 @@ static void _esp_can_power_down(can_t *dev)
twai_hal_deinit(&hw);
/* power down the CAN controller */
periph_module_disable(PERIPH_CAN_MODULE);
periph_module_disable(PERIPH_TWAI_MODULE);
dev->powered_up = false;
}

2
cpu/esp32/periph/gpio.c
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@ -101,7 +101,7 @@ static bool _gpio_pin_pu[GPIO_PIN_NUMOF] = { };
static bool _gpio_pin_pd[GPIO_PIN_NUMOF] = { };
#endif
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#define GPIO_IN_GET(b) (b < 32) ? GPIO.in & BIT(b) : GPIO.in1.val & BIT(b-32)
#define GPIO_OUT_SET(b) if (b < 32) { GPIO.out_w1ts = BIT(b); } else { GPIO.out1_w1ts.val = BIT(b-32); }

141
cpu/esp32/periph/gpio_arch_esp32s2.c Normal file
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@ -0,0 +1,141 @@
/*
* Copyright (C) 2022 Gunar Schorcht
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_esp32
* @ingroup drivers_periph_gpio
* @{
*
* @file
* @brief Architecture-specific GPIO definitions for ESP32-S2 variant (family)
*
* @author Gunar Schorcht <gunar@schorcht.net>
* @}
*/
#include "gpio_arch.h"
#include "soc/io_mux_reg.h"
#if !IS_USED(MODULE_ESP_IDF_GPIO_HAL)
/* GPIO to IOMUX register mapping (see Technical Reference, Section 5.14.2 Register Summary)
https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf */
const uint32_t _gpio_to_iomux_reg[GPIO_PIN_NUMOF] =
{
PERIPHS_IO_MUX_GPIO0_U, /* GPIO0 */
PERIPHS_IO_MUX_GPIO1_U, /* GPIO1 */
PERIPHS_IO_MUX_GPIO2_U, /* GPIO2 */
PERIPHS_IO_MUX_GPIO3_U, /* GPIO3 */
PERIPHS_IO_MUX_GPIO4_U, /* GPIO4 */
PERIPHS_IO_MUX_GPIO5_U, /* GPIO5 */
PERIPHS_IO_MUX_GPIO6_U, /* GPIO6 */
PERIPHS_IO_MUX_GPIO7_U, /* GPIO7 */
PERIPHS_IO_MUX_GPIO8_U, /* GPIO8 */
PERIPHS_IO_MUX_GPIO9_U, /* GPIO9 */
PERIPHS_IO_MUX_GPIO10_U, /* GPIO10 */
PERIPHS_IO_MUX_GPIO11_U, /* GPIO11 */
PERIPHS_IO_MUX_GPIO12_U, /* GPIO12 */
PERIPHS_IO_MUX_GPIO13_U, /* GPIO13 */
PERIPHS_IO_MUX_GPIO14_U, /* GPIO14 */
PERIPHS_IO_MUX_XTAL_32K_P_U, /* GPIO15 used for 32k XTAL */
PERIPHS_IO_MUX_XTAL_32K_N_U, /* GPIO16 used for 32k XTAL */
PERIPHS_IO_MUX_DAC_1_U, /* GPIO17 */
PERIPHS_IO_MUX_DAC_2_U, /* GPIO18 */
PERIPHS_IO_MUX_GPIO19_U, /* GPIO19 */
PERIPHS_IO_MUX_GPIO20_U, /* GPIO20 */
PERIPHS_IO_MUX_GPIO21_U, /* GPIO21 */
0, /* GPIO22 is not available */
0, /* GPIO23 is not available */
0, /* GPIO24 is not available */
0, /* GPIO25 is not available */
PERIPHS_IO_MUX_SPICS1_U, /* GPIO26 used as SPI CS1 */
PERIPHS_IO_MUX_SPIHD_U, /* GPIO27 used as SPI HS for Flash */
PERIPHS_IO_MUX_SPIWP_U, /* GPIO28 used as SPI WP for Flash */
PERIPHS_IO_MUX_SPICS0_U, /* GPIO29 used as SPI CS0 for Flash */
PERIPHS_IO_MUX_SPICLK_U, /* GPIO30 used as SPI CLK for Flash */
PERIPHS_IO_MUX_SPID_U, /* GPIO31 used as SPI D for Flash */
PERIPHS_IO_MUX_SPIQ_U, /* GPIO32 used as SPI Q for Flash */
PERIPHS_IO_MUX_GPIO33_U, /* GPIO33 */
PERIPHS_IO_MUX_GPIO34_U, /* GPIO34 */
PERIPHS_IO_MUX_GPIO35_U, /* GPIO35 */
PERIPHS_IO_MUX_GPIO36_U, /* GPIO36 */
PERIPHS_IO_MUX_GPIO37_U, /* GPIO37 */
PERIPHS_IO_MUX_GPIO38_U, /* GPIO38 */
PERIPHS_IO_MUX_MTCK_U, /* GPIO39 used as JTAG*/
PERIPHS_IO_MUX_MTDO_U, /* GPIO40 used as JTAG*/
PERIPHS_IO_MUX_MTDI_U, /* GPIO41 used as JTAG*/
PERIPHS_IO_MUX_MTMS_U, /* GPIO42 used as JTAG*/
PERIPHS_IO_MUX_U0TXD_U, /* GPIO43 used as UART0 TxD */
PERIPHS_IO_MUX_U0RXD_U, /* GPIO44 used as UART0 RxD */
PERIPHS_IO_MUX_GPIO45_U, /* GPIO45 */
PERIPHS_IO_MUX_GPIO46_U, /* GPIO46 */
};
#endif /* !IS_USED(MODULE_ESP_IDF_GPIO_HAL) */
/* Table of the usage type of each GPIO pin */
gpio_pin_usage_t _gpio_pin_usage[GPIO_PIN_NUMOF] = {
_GPIO, /* GPIO0 */
_GPIO, /* GPIO1 */
_GPIO, /* GPIO2 */
_GPIO, /* GPIO3 */
_GPIO, /* GPIO4 */
_GPIO, /* GPIO5 */
_GPIO, /* GPIO6 */
_GPIO, /* GPIO7 */
_GPIO, /* GPIO8 */
_GPIO, /* GPIO9 */
_GPIO, /* GPIO10 */
_GPIO, /* GPIO11 */
_GPIO, /* GPIO12 */
_GPIO, /* GPIO13 */
_GPIO, /* GPIO14 */
#if MODULE_ESP_RTC_TIMER_32K
_NOT_EXIST, /* GPIO15 is used for external 32K crystal */
_NOT_EXIST, /* GPIO16 is used for external 32K crystal */
#else
_GPIO, /* GPIO15 */
_GPIO, /* GPIO16 */
#endif
_GPIO, /* GPIO17 */
_GPIO, /* GPIO18 */
_GPIO, /* GPIO19 could be used for ESP USB/builtin USB2JTAG bridge */
_GPIO, /* GPIO20 could be used for ESP USB/builtin USB2JTAG bridge */
_GPIO, /* GPIO21 */
_NOT_EXIST, /* GPIO22 does not exist */
_NOT_EXIST, /* GPIO23 does not exist */
_NOT_EXIST, /* GPIO24 does not exist */
_NOT_EXIST, /* GPIO25 does not exist */
_NOT_EXIST, /* GPIO26 is used as direct I/O SPI CS1 for Flash/PSRAM */
#if defined(FLASH_MODE_QIO) || defined(FLASH_MODE_QOUT)
_SPIF, /* GPIO27 is used as direct I/O SPI HD for Flash/PSRAM */
_SPIF, /* GPIO28 is used as direct I/O SPI WP for Flash/PSRAM */
#else
_GPIO, /* GPIO27 */
_GPIO, /* GPIO28 */
#endif
_SPIF, /* GPIO29 is used as direct I/O SPI CS0 for Flash/PSRAM */
_SPIF, /* GPIO30 is used as direct I/O SPI CLK for Flash/PSRAM */
_SPIF, /* GPIO31 is used as direct I/O SPI Q for Flash/PSRAM */
_SPIF, /* GPIO32 is used as direct I/O SPI D for Flash/PSRAM */
_GPIO, /* GPIO33 */
_GPIO, /* GPIO34 */
_GPIO, /* GPIO35 */
_GPIO, /* GPIO36 */
_GPIO, /* GPIO37 */
_GPIO, /* GPIO38 */
_GPIO, /* GPIO39 */
_GPIO, /* GPIO40 */
_GPIO, /* GPIO41 */
_GPIO, /* GPIO42 */
_UART, /* GPIO43 is used as direct I/O UART0 TxD */
_UART, /* GPIO44 is used as direct I/O UART0 RxD */
_GPIO, /* GPIO45 */
_GPIO, /* GPIO46 */
};

2
cpu/esp32/periph/rtt_hw_rtc.c
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@ -105,7 +105,7 @@ uint64_t _rtc_get_counter(void)
}
/* read the time from 48-bit counter and return */
return (((uint64_t)RTCCNTL.time1.val) << 32) + RTCCNTL.time0;
#elif defined(CPU_FAM_ESP32C3) || defined(CPU_FAM_ESP32S3)
#elif defined(CPU_FAM_ESP32C3) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
/* read the time from 48-bit counter and return */
return (((uint64_t)RTCCNTL.time_high0.val) << 32) + RTCCNTL.time_low0;
#else

6
cpu/esp32/periph/spi.c
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@ -290,8 +290,8 @@ void IRAM_ATTR spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t cl
spi_transfer_bytes(bus, GPIO_UNDEF, false, &temp, &temp, 1);
_spi[bus].mode_last = mode;
}
#elif defined(CPU_FAM_ESP32)
/* This workaround isn't needed on ESP32 */
#elif defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2)
/* This workaround isn't needed on ESP32 and ESP32-S2 */
#else
#error Platform implementation is missing
#endif
@ -312,6 +312,8 @@ void IRAM_ATTR spi_release(spi_t bus)
static const char* _spi_names[] = { "CSPI/FSPI", "HSPI", "VSPI" };
#elif defined(CPU_FAM_ESP32C3)
static const char* _spi_names[] = { "SPI", "FSPI" };
#elif defined(CPU_FAM_ESP32S2)
static const char* _spi_names[] = { "SPI", "FSPI", "HSPI" };
#elif defined(CPU_FAM_ESP32S3)
static const char* _spi_names[] = { "SPI", "FSPI", "SPI" };
#else

12
cpu/esp32/periph/timer.c
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@ -96,6 +96,11 @@
#define HW_TIMER_CORRECTION 10
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION << 1, 5))
#elif defined(CPU_FAM_ESP32S2)
#define HW_TIMER_CORRECTION (RTC_PLL_320M / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ)
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION << 1, 5))
#elif defined(CPU_FAM_ESP32S3)
#define HW_TIMER_CORRECTION (RTC_PLL_320M / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ)
@ -126,7 +131,7 @@ struct _hw_timer_desc_t {
static const struct _hw_timer_desc_t _timers_desc[] =
{
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
{
.module = PERIPH_TIMG0_MODULE,
.group = TIMER_GROUP_0,
@ -399,6 +404,11 @@ void IRAM_ATTR timer_stop(tim_t dev)
#define HW_TIMER_CORRECTION (RTC_PLL_480M / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION, 5))
#elif defined(CPU_FAM_ESP32S2)
#define HW_TIMER_CORRECTION (RTC_PLL_480M / CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ)
#define HW_TIMER_DELTA_MIN (MAX(HW_TIMER_CORRECTION, 5))
#elif defined(CPU_FAM_ESP32S3)
#define HW_TIMER_CORRECTION (RTC_PLL_480M / CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ)

4
cpu/esp_common/periph/i2c_sw.c
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@ -59,7 +59,7 @@
#define I2C_CLOCK_STRETCH 200
/* gpio access macros */
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S3)
#if defined(CPU_FAM_ESP32) || defined(CPU_FAM_ESP32S2) || defined(CPU_FAM_ESP32S3)
#define GPIO_SET(lo, hi, b) if (b < 32) { GPIO.lo = BIT(b); } else { GPIO.hi.val = BIT(b-32); }
#define GPIO_GET(lo, hi, b) ((b < 32) ? GPIO.lo & BIT(b) : GPIO.hi.val & BIT(b-32))
#elif defined(CPU_FAM_ESP32C3)
@ -119,6 +119,8 @@ static _i2c_bus_t _i2c_bus[I2C_NUMOF] = {};
#define I2C_CLK_CAL 62 /* clock calibration offset */
#elif defined(CPU_FAM_ESP32C3)
#define I2C_CLK_CAL 32 /* clock calibration offset */
#elif defined(CPU_FAM_ESP32S2)
#define I2C_CLK_CAL 82 /* clock calibration offset */
#elif defined(CPU_FAM_ESP32S3)
#define I2C_CLK_CAL 82 /* clock calibration offset */
#elif defined(MCU_ESP8266)

2
cpu/esp_common/periph/uart.c
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@ -339,6 +339,8 @@ static uint8_t IRAM _uart_rx_one_char(uart_t uart)
#elif defined(CPU_FAM_ESP32S3)
/* read the lowest byte from RX FIFO register */
return _uarts[uart].regs->fifo.rxfifo_rd_byte;
#elif defined(CPU_FAM_ESP32S2)
return READ_PERI_REG(UART_FIFO_AHB_REG(uart));
#else
/* read the lowest byte from RX FIFO register */
return _uarts[uart].regs->ahb_fifo.rw_byte;