diff --git a/cpu/atmega8/Kconfig b/cpu/atmega8/Kconfig index aa1c3c6ff1..43027b27d3 100644 --- a/cpu/atmega8/Kconfig +++ b/cpu/atmega8/Kconfig @@ -19,7 +19,7 @@ config CPU_MODEL_ATMEGA8 config HAS_CPU_ATMEGA8 bool help - Indicates that a 'atmega8' cpu is being used. + Indicates that an 'atmega8' cpu is being used. ## Common CPU symbols config CPU_FAM diff --git a/cpu/atmega8/Makefile.features b/cpu/atmega8/Makefile.features index ec626a3bf9..2a49705acf 100644 --- a/cpu/atmega8/Makefile.features +++ b/cpu/atmega8/Makefile.features @@ -1 +1,3 @@ +CPU_FAM = atmega8 + include $(RIOTCPU)/atmega_common/Makefile.features diff --git a/cpu/atmega_common/Kconfig b/cpu/atmega_common/Kconfig index 7936291144..810df57a4f 100644 --- a/cpu/atmega_common/Kconfig +++ b/cpu/atmega_common/Kconfig @@ -14,8 +14,8 @@ config CPU_COMMON_ATMEGA bool select HAS_CPU_CORE_ATMEGA select HAS_ATMEGA_PCINT0 - select HAS_DBGPIN - select HAS_PERIPH_CPUID + select HAS_DBGPIN if !CPU_FAM_ATMEGA8 + select HAS_PERIPH_CPUID if !CPU_FAM_ATMEGA8 select HAS_PERIPH_EEPROM select HAS_PERIPH_GPIO select HAS_PERIPH_GPIO_IRQ diff --git a/cpu/atmega_common/Makefile.features b/cpu/atmega_common/Makefile.features index 53078f915f..42bd92dc22 100644 --- a/cpu/atmega_common/Makefile.features +++ b/cpu/atmega_common/Makefile.features @@ -5,8 +5,6 @@ include $(RIOTCPU)/avr8_common/Makefile.features FEATURES_PROVIDED += cpu_core_atmega FEATURES_PROVIDED += atmega_pcint0 -FEATURES_PROVIDED += dbgpin -FEATURES_PROVIDED += periph_cpuid FEATURES_PROVIDED += periph_eeprom FEATURES_PROVIDED += periph_gpio periph_gpio_irq FEATURES_PROVIDED += periph_gpio_ll @@ -20,6 +18,10 @@ FEATURES_PROVIDED += periph_timer_periodic FEATURES_PROVIDED += periph_rtt_overflow FEATURES_PROVIDED += periph_wdt FEATURES_PROVIDED += puf_sram +ifneq (atmega8, $(CPU_FAM)) +FEATURES_PROVIDED += dbgpin +FEATURES_PROVIDED += periph_cpuid +endif FEATURES_CONFLICT += periph_rtc:periph_rtt FEATURES_CONFLICT_MSG += "On ATmega, the RTC and RTT use to the same hardware timer." diff --git a/cpu/atmega_common/periph/eeprom.c b/cpu/atmega_common/periph/eeprom.c index 647acd27d8..ba40c3a926 100644 --- a/cpu/atmega_common/periph/eeprom.c +++ b/cpu/atmega_common/periph/eeprom.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2018 Inria + * 2023 Hugues Larrive * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -15,6 +16,7 @@ * @brief Low-level EEPROM driver implementation for ATmega family * * @author Alexandre Abadie + * @author Hugues Larrive * @} */ @@ -35,7 +37,11 @@ size_t eeprom_read(uint32_t pos, void *data, size_t len) DEBUG("Reading data from EEPROM at pos %" PRIu32 ": ", pos); for (size_t i = 0; i < len; i++) { +#ifdef EEPE while (EECR & (1 << EEPE)) {} +#elif defined(EEWE) + while (EECR & (1 << EEWE)) {} +#endif /* Set up address register */ EEAR = pos++; @@ -58,17 +64,30 @@ size_t eeprom_write(uint32_t pos, const void *data, size_t len) for (size_t i = 0; i < len; i++) { /* Wait for completion of previous operation */ +#ifdef EEPE while (EECR & (1 << EEPE)) {} +#elif defined(EEWE) + while (EECR & (1 << EEWE)) {} +#endif /* Set up address and Data Registers */ EEAR = pos++; EEDR = *p++; +#ifdef EEMPE /* Write logical one to EEMPE */ EECR |= (1 << EEMPE); - +#elif defined(EEMWE) + /* Write logical one to EEMWE */ + EECR |= (1 << EEMWE); +#endif +#ifdef EEPE /* Start eeprom write by setting EEPE */ EECR |= (1 << EEPE); +#elif defined(EEWE) + /* Start eeprom write by setting EEWE */ + EECR |= (1 << EEWE); +#endif } return len; diff --git a/cpu/atmega_common/periph/gpio_ll_irq.c b/cpu/atmega_common/periph/gpio_ll_irq.c index c8eeb1cfd6..dd073b1076 100644 --- a/cpu/atmega_common/periph/gpio_ll_irq.c +++ b/cpu/atmega_common/periph/gpio_ll_irq.c @@ -3,6 +3,7 @@ * 2016 INRIA * 2022 Otto-von-Guericke-Universität Magdeburg * 2023 Gerson Fernando Budke + * 2023 Hugues Larrive * * This file is subject to the terms and conditions of the GNU Lesser General * Public License v2.1. See the file LICENSE in the top level directory for more @@ -24,6 +25,7 @@ * @author Torben Petersen * @author Marian Buschsieweke * @author Gerson Fernando Budke + * @author Hugues Larrive * * @} */ @@ -49,32 +51,54 @@ static struct isr_ctx isr_ctx[GPIO_EXT_INT_NUMOF]; static void clear_pending_irqs(uint8_t exti) { +#if defined(EIFR) EIFR |= 1 << exti; +#elif defined(GIFR) + GIFR |= 1 << (INTF0 + exti); +#else +# error "No support for AVR with neither EIFR nor GIFR" +#endif } void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin) { uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin); +#if defined(EIMSK) EIMSK &= ~(1 << exti); +#elif defined(GICR) + GICR &= ~(1 << (INT0 + exti)); +#endif } void gpio_ll_irq_unmask(gpio_port_t port, uint8_t pin) { uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin); +#if defined(EIMSK) EIMSK |= 1 << exti; +#elif defined(GICR) + GICR |= 1 << (INT0 + exti); +#endif } void gpio_ll_irq_unmask_and_clear(gpio_port_t port, uint8_t pin) { uint8_t exti = atmega_pin2exti(GPIO_PORT_NUM(port), pin); clear_pending_irqs(exti); +#if defined(EIMSK) EIMSK |= 1 << exti; +#elif defined(GICR) + GICR |= 1 << (INT0 + exti); +#endif } static void set_trigger(uint8_t exti, gpio_irq_trig_t trig) { exti <<= 1; +#if defined(EICRA) volatile uint8_t *eicr = &EICRA; +#elif defined(MCUCR) + volatile uint8_t *eicr = &MCUCR; +#endif #ifdef EICRB if (exti >= 8) { @@ -110,7 +134,11 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, /* setup IRQ */ set_trigger(exti, trig); clear_pending_irqs(exti); +#if defined(EIMSK) EIMSK |= 1 << exti; +#elif defined(GICR) + GICR |= 1 << (INT0 + exti); +#endif irq_restore(irq_state); diff --git a/cpu/atmega_common/periph/wdt.c b/cpu/atmega_common/periph/wdt.c index 27411c9fd0..c0bbe3bb6d 100644 --- a/cpu/atmega_common/periph/wdt.c +++ b/cpu/atmega_common/periph/wdt.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2019 Inria + * 2023 Hugues Larrive * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level @@ -15,6 +16,7 @@ * @brief Implementation of the watchdog peripheral interface * * @author Alexandre Abadie + * @author Hugues Larrive * * @} */ @@ -66,13 +68,18 @@ void wdt_setup_reboot(uint32_t min_time, uint32_t max_time) /* disable watchdog */ wdt_disable(); + /* WDTO_8S and WDTO_4S are only available on some devices, we will + * test on WDP3 as in avr/wdt.h */ +#ifdef WDP3 if (max_time >= 8000) { wdt_prescaler = WDTO_8S; } else if (max_time >= 4000) { wdt_prescaler = WDTO_4S; } - else if (max_time >= 2000) { + else +#endif + if (max_time >= 2000) { wdt_prescaler = WDTO_2S; } else if (max_time >= 1000) { diff --git a/pkg/qdsa/Makefile b/pkg/qdsa/Makefile index e7bb461440..394b7e2877 100644 --- a/pkg/qdsa/Makefile +++ b/pkg/qdsa/Makefile @@ -1,6 +1,6 @@ PKG_NAME=qdsa PKG_URL=https://github.com/RIOT-OS/qdsa.git -PKG_VERSION=4cb3f1a140f25e18ed288fd484defe3d45bdf166 +PKG_VERSION=3fa25ffa3971000fe4a3e3b42340c40c8d79f2a2 PKG_LICENSE=PD include $(RIOTBASE)/pkg/pkg.mk