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Merge pull request #8540 from OTAkeys/pr/rtt_stm32f4

cpu/stm32_common: add RTT support for stm32f4
This commit is contained in:
Alexandre Abadie 2018-02-08 18:21:58 +01:00 committed by GitHub
commit 06019e2070
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 34 additions and 6 deletions

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@ -4,6 +4,7 @@ FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_i2c
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart

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@ -275,6 +275,15 @@ static const spi_conf_t spi_config[] = {
#define RTC_NUMOF (1)
/** @} */
/**
* @name RTT configuration
* @{
*/
#define RTT_NUMOF (1)
#define RTT_FREQUENCY (4096)
#define RTT_MAX_VALUE (0xffff)
/** @} */
#ifdef __cplusplus
}
#endif

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@ -22,6 +22,7 @@
#include "cpu.h"
#include "irq.h"
#include "periph/rtt.h"
#include "stmclk.h"
/* this driver is only valid for STM CPUs that provide LPTIMERs */
#if defined(LPTIM1)
@ -47,6 +48,26 @@
#error "RTT config: RTT_FREQUENCY not configured or invalid for your board"
#endif
#if !defined(CPU_FAM_STM32F4)
#define CLOCK_SRC_REG RCC->CCIPR
#define CLOCK_SRC_MASK RCC_CCIPR_LPTIM1SEL
#if CLOCK_LSE
#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0)
#else
#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_0)
#endif
#else
#define CLOCK_SRC_REG RCC->DCKCFGR2
#define CLOCK_SRC_MASK RCC_DCKCFGR2_LPTIM1SEL
#if CLOCK_LSE
#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)
#else
#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_0)
#endif
#endif
/* allocate memory for overflow and alarm callbacks + args */
static rtt_cb_t ovf_cb = NULL;
static void *ovf_arg;
@ -55,6 +76,7 @@ static void *to_arg;
void rtt_init(void)
{
stmclk_enable_lfclk();
/* power on the selected LPTIMER */
rtt_poweron();
@ -62,12 +84,8 @@ void rtt_init(void)
LPTIM1->CR = 0;
/* select low speed clock (LSI or LSE) */
RCC->CCIPR &= ~(RCC_CCIPR_LPTIM1SEL);
#if CLOCK_LSE
RCC->CCIPR |= (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0);
#else
RCC->CCIPR |= (RCC_CCIPR_LPTIM1SEL_0);
#endif
CLOCK_SRC_REG &= ~(CLOCK_SRC_MASK);
CLOCK_SRC_REG |= CLOCK_SRC_CFG;
/* set configuration: prescale factor and external clock (LSI or LSE) */
LPTIM1->CFGR = PRE;