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Merge pull request #8540 from OTAkeys/pr/rtt_stm32f4
cpu/stm32_common: add RTT support for stm32f4
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commit
06019e2070
@ -4,6 +4,7 @@ FEATURES_PROVIDED += periph_gpio
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FEATURES_PROVIDED += periph_i2c
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_rtc
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FEATURES_PROVIDED += periph_rtt
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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@ -275,6 +275,15 @@ static const spi_conf_t spi_config[] = {
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#define RTC_NUMOF (1)
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/** @} */
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/**
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* @name RTT configuration
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* @{
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*/
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#define RTT_NUMOF (1)
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#define RTT_FREQUENCY (4096)
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#define RTT_MAX_VALUE (0xffff)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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@ -22,6 +22,7 @@
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#include "cpu.h"
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#include "irq.h"
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#include "periph/rtt.h"
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#include "stmclk.h"
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/* this driver is only valid for STM CPUs that provide LPTIMERs */
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#if defined(LPTIM1)
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@ -47,6 +48,26 @@
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#error "RTT config: RTT_FREQUENCY not configured or invalid for your board"
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#endif
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#if !defined(CPU_FAM_STM32F4)
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#define CLOCK_SRC_REG RCC->CCIPR
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#define CLOCK_SRC_MASK RCC_CCIPR_LPTIM1SEL
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#if CLOCK_LSE
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#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0)
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#else
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#define CLOCK_SRC_CFG (RCC_CCIPR_LPTIM1SEL_0)
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#endif
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#else
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#define CLOCK_SRC_REG RCC->DCKCFGR2
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#define CLOCK_SRC_MASK RCC_DCKCFGR2_LPTIM1SEL
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#if CLOCK_LSE
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#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)
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#else
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#define CLOCK_SRC_CFG (RCC_DCKCFGR2_LPTIM1SEL_0)
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#endif
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#endif
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/* allocate memory for overflow and alarm callbacks + args */
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static rtt_cb_t ovf_cb = NULL;
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static void *ovf_arg;
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@ -55,6 +76,7 @@ static void *to_arg;
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void rtt_init(void)
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{
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stmclk_enable_lfclk();
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/* power on the selected LPTIMER */
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rtt_poweron();
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@ -62,12 +84,8 @@ void rtt_init(void)
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LPTIM1->CR = 0;
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/* select low speed clock (LSI or LSE) */
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RCC->CCIPR &= ~(RCC_CCIPR_LPTIM1SEL);
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#if CLOCK_LSE
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RCC->CCIPR |= (RCC_CCIPR_LPTIM1SEL_1 | RCC_CCIPR_LPTIM1SEL_0);
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#else
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RCC->CCIPR |= (RCC_CCIPR_LPTIM1SEL_0);
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#endif
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CLOCK_SRC_REG &= ~(CLOCK_SRC_MASK);
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CLOCK_SRC_REG |= CLOCK_SRC_CFG;
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/* set configuration: prescale factor and external clock (LSI or LSE) */
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LPTIM1->CFGR = PRE;
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