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cpu/stm32: Implement GPIO LL IRQ support for STM32F1

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This commit is contained in:
Marian Buschsieweke 2023-03-20 14:07:14 +01:00
parent 9719bbf432
commit 03dfa495ff
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GPG Key ID: CB8E3238CE715A94
3 changed files with 101 additions and 78 deletions
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9
cpu/stm32/Makefile.features
View File

@ -12,12 +12,9 @@ FEATURES_PROVIDED += periph_rtt_overflow
FEATURES_PROVIDED += periph_uart_modecfg FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += periph_uart_nonblocking FEATURES_PROVIDED += periph_uart_nonblocking
FEATURES_PROVIDED += periph_gpio_ll FEATURES_PROVIDED += periph_gpio_ll
FEATURES_PROVIDED += periph_gpio_ll_irq
ifneq ($(CPU_FAM),f1) FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
FEATURES_PROVIDED += periph_gpio_ll_irq FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
endif
ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl)) ifneq (,$(filter $(CPU_FAM),f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
FEATURES_PROVIDED += periph_flashpage FEATURES_PROVIDED += periph_flashpage

3
cpu/stm32/kconfigs/f1/Kconfig
View File

@ -17,6 +17,9 @@ config CPU_FAM_F1
select HAS_PERIPH_FLASHPAGE_PAGEWISE select HAS_PERIPH_FLASHPAGE_PAGEWISE
select HAS_PERIPH_FLASHPAGE_RAW select HAS_PERIPH_FLASHPAGE_RAW
select HAS_PERIPH_GPIO_LL select HAS_PERIPH_GPIO_LL
select HAS_PERIPH_GPIO_LL_IRQ
select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
select HAS_PERIPH_RTT_SET_COUNTER select HAS_PERIPH_RTT_SET_COUNTER
select HAS_PERIPH_WDT select HAS_PERIPH_WDT
select HAVE_SHARED_PERIPH_RTT_PERIPH_RTC select HAVE_SHARED_PERIPH_RTT_PERIPH_RTC

167
cpu/stm32/periph/gpio_ll_irq.c
View File

@ -41,43 +41,87 @@
#define EXTI_MASK (0xFFFF) #define EXTI_MASK (0xFFFF)
#if defined(EXTI_SWIER_SWI0) || defined(EXTI_SWIER_SWIER0) #if defined(EXTI_SWIER_SWI0) || defined(EXTI_SWIER_SWIER0)
#define EXTI_REG_SWIER (EXTI->SWIER) # define EXTI_REG_SWIER (EXTI->SWIER)
#endif #endif
#if defined(EXTI_SWIER1_SWI0) || defined(EXTI_SWIER1_SWIER0) #if defined(EXTI_SWIER1_SWI0) || defined(EXTI_SWIER1_SWIER0)
#define EXTI_REG_SWIER (EXTI->SWIER1) # define EXTI_REG_SWIER (EXTI->SWIER1)
#endif #endif
#if defined(EXTI_RTSR_RT0) || defined(EXTI_RTSR_TR0) #if defined(EXTI_RTSR_RT0) || defined(EXTI_RTSR_TR0)
#define EXTI_REG_RTSR (EXTI->RTSR) # define EXTI_REG_RTSR (EXTI->RTSR)
#endif #endif
#if defined(EXTI_RTSR1_RT0) || defined(EXTI_RTSR1_TR0) #if defined(EXTI_RTSR1_RT0) || defined(EXTI_RTSR1_TR0)
#define EXTI_REG_RTSR (EXTI->RTSR1) # define EXTI_REG_RTSR (EXTI->RTSR1)
#endif #endif
#if defined(EXTI_FTSR_FT0) || defined(EXTI_FTSR_TR0) #if defined(EXTI_FTSR_FT0) || defined(EXTI_FTSR_TR0)
#define EXTI_REG_FTSR (EXTI->FTSR) # define EXTI_REG_FTSR (EXTI->FTSR)
#endif #endif
#if defined(EXTI_FTSR1_FT0) || defined (EXTI_FTSR1_TR0) #if defined(EXTI_FTSR1_FT0) || defined (EXTI_FTSR1_TR0)
#define EXTI_REG_FTSR (EXTI->FTSR1) # define EXTI_REG_FTSR (EXTI->FTSR1)
#endif #endif
#ifdef EXTI_PR_PR0 #if defined(EXTI_PR_PR0)
#define EXTI_REG_PR (EXTI->PR) # define EXTI_REG_PR (EXTI->PR)
#endif #elif defined(EXTI_PR1_PIF0)
# define EXTI_REG_PR (EXTI->PR1)
#ifdef EXTI_PR1_PIF0 #else
#define EXTI_REG_PR (EXTI->PR1) # define EXTI_REG_FPR (EXTI->FPR1)
# define EXTI_REG_RPR (EXTI->RPR1)
#endif #endif
#if defined(EXTI_C2_BASE) #if defined(EXTI_C2_BASE)
# define EXTI_REG_IMR (EXTI_C2->IMR1) # define EXTI_REG_IMR (EXTI_C2->IMR1)
#elif defined(EXTI_IMR_IM0) #elif defined(EXTI_IMR_IM0)
# define EXTI_REG_IMR (EXTI->IMR) # define EXTI_REG_IMR (EXTI->IMR)
#elif defined(EXTI_IMR1_IM0) #elif defined(EXTI_IMR1_IM0)
# define EXTI_REG_IMR (EXTI->IMR1) # define EXTI_REG_IMR (EXTI->IMR1)
#endif
#ifdef RCC_APB2ENR_SYSCFGCOMPEN
# define SYSFG_CLOCK APB2
# define SYSFG_ENABLE_MASK RCC_APB2ENR_SYSCFGCOMPEN
#endif
#ifdef RCC_APBENR2_SYSCFGEN
# define SYSFG_ENABLE_MASK RCC_APBENR2_SYSCFGEN
# ifdef APB12
# define SYSFG_CLOCK APB12
# else
# define SYSFG_CLOCK APB2
# endif
#endif
#ifdef RCC_APB3ENR_SYSCFGEN
# define SYSFG_CLOCK APB3
# define SYSFG_ENABLE_MASK RCC_APB3ENR_SYSCFGEN
#endif
#ifdef EXTI_EXTICR1_EXTI0
# define EXTICR_REG(num) (EXTI->EXTICR[(num) >> 2])
#endif
#ifdef SYSCFG_EXTICR1_EXTI0
# define EXTICR_REG(num) (SYSCFG->EXTICR[(num) >> 2])
#endif
#ifdef AFIO_EXTICR1_EXTI0
# define EXTICR_REG(num) (AFIO->EXTICR[(num) >> 2])
#endif
#ifdef SYSCFG_EXTICR1_EXTI1_Pos
# define EXTICR_FIELD_SIZE SYSCFG_EXTICR1_EXTI1_Pos
#endif
#ifdef EXTI_EXTICR1_EXTI1_Pos
# define EXTICR_FIELD_SIZE EXTI_EXTICR1_EXTI1_Pos
#endif
#ifdef AFIO_EXTICR1_EXTI1_Pos
# define EXTICR_FIELD_SIZE AFIO_EXTICR1_EXTI1_Pos
#endif #endif
void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin) void gpio_ll_irq_mask(gpio_port_t port, uint8_t pin)
@ -102,6 +146,8 @@ static uint16_t level_triggered;
static IRQn_Type get_irqn(uint8_t pin) static IRQn_Type get_irqn(uint8_t pin)
{ {
/* TODO: Come up with a way that this doesn't need updates whenever a new
* MCU family gets added */
#if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) #if defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
return EXTI0_IRQn + pin; return EXTI0_IRQn + pin;
#elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \ #elif defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32L0) || \
@ -155,48 +201,29 @@ static IRQn_Type get_irqn(uint8_t pin)
static void clear_pending_irqs(uint8_t pin) static void clear_pending_irqs(uint8_t pin)
{ {
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ #ifdef EXTI_REG_PR
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) /* same IRQ flag no matter if falling or rising edge detected */
/* clear any pending requests */ EXTI_REG_PR = (1U << pin);
EXTI->RPR1 = (1 << pin);
EXTI->FPR1 = (1 << pin);
#else #else
/* clear any pending requests */ /* distinct IRQ flags for falling and rising edge, clearing both */
EXTI_REG_PR = (1 << pin); EXTI_REG_FPR = (1U << pin);
EXTI_REG_RPR = (1U << pin);
#endif #endif
} }
static void set_exti_port(uint8_t exti_num, uint8_t port_num) static void set_exti_port(uint8_t exti_num, uint8_t port_num)
{ {
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ uint32_t tmp = EXTICR_REG(exti_num);
defined(CPU_FAM_STM32U5) tmp &= ~(0xf << ((exti_num & 0x03) * EXTICR_FIELD_SIZE));
/* enable specific pin as exti sources */ tmp |= (port_num << ((exti_num & 0x03) * EXTICR_FIELD_SIZE));
EXTI->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 8)); EXTICR_REG(exti_num) = tmp;
EXTI->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 8));
#elif defined(CPU_FAM_STM32MP1)
/* enable specific pin as exti sources */
EXTI->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 4));
EXTI->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 4));
#else
/* enable specific pin as exti sources */
SYSCFG->EXTICR[exti_num >> 2] &= ~(0xf << ((exti_num & 0x03) * 4));
SYSCFG->EXTICR[exti_num >> 2] |= (port_num << ((exti_num & 0x03) * 4));
#endif
} }
static uint8_t get_exti_port(uint8_t exti_num) static uint8_t get_exti_port(uint8_t exti_num)
{ {
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ uint32_t reg = EXTICR_REG(exti_num);
defined(CPU_FAM_STM32U5) reg >>= (exti_num & 0x03) * EXTICR_FIELD_SIZE;
/* enable specific pin as exti sources */ return reg & 0xf;
return 0xf & (EXTI->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 8));
#elif defined(CPU_FAM_STM32MP1)
/* enable specific pin as exti sources */
return 0xf & (EXTI->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 4));
#else
/* enable specific pin as exti sources */
return 0xf & (SYSCFG->EXTICR[exti_num >> 2] >> ((exti_num & 0x03) * 4));
#endif
} }
int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_t cb, void *arg) int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_t cb, void *arg)
@ -209,17 +236,8 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_
isr_ctx[pin].arg = arg; isr_ctx[pin].arg = arg;
/* enable clock of the SYSCFG module for EXTI configuration */ /* enable clock of the SYSCFG module for EXTI configuration */
#if !defined(CPU_FAM_STM32WB) && !defined(CPU_FAM_STM32MP1) && \ #ifdef SYSFG_CLOCK
!defined(CPU_FAM_STM32WL) periph_clk_en(SYSFG_CLOCK, SYSFG_ENABLE_MASK);
#ifdef CPU_FAM_STM32F0
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGCOMPEN);
#elif defined(CPU_FAM_STM32G0)
periph_clk_en(APB12, RCC_APBENR2_SYSCFGEN);
#elif defined(CPU_FAM_STM32U5)
periph_clk_en(APB3, RCC_APB3ENR_SYSCFGEN);
#else
periph_clk_en(APB2, RCC_APB2ENR_SYSCFGEN);
#endif
#endif #endif
/* enable global pin interrupt */ /* enable global pin interrupt */
@ -262,30 +280,35 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig, gpio_ll_cb_
return 0; return 0;
} }
void isr_exti(void) static uint32_t get_and_clear_pending_irqs(void)
{ {
#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \ #ifdef EXTI_REG_PR
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32MP1) /* only one pending IRQ flag register for both falling and rising flanks */
/* get all interrupts handled by this ISR */ uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);
uint32_t pending_rising_isr = (EXTI->RPR1 & EXTI_MASK);
uint32_t pending_falling_isr = (EXTI->FPR1 & EXTI_MASK); /* clear by writing a 1 */
EXTI_REG_PR = pending_isr;
return pending_isr;
#else
/* distinct registers for pending IRQ flags depending on rising or falling
* flank */
uint32_t pending_rising_isr = (EXTI_REG_RPR & EXTI_MASK);
uint32_t pending_falling_isr = (EXTI_REG_FPR & EXTI_MASK);
/* clear by writing a 1 */ /* clear by writing a 1 */
EXTI->RPR1 = pending_rising_isr; EXTI->RPR1 = pending_rising_isr;
EXTI->FPR1 = pending_falling_isr; EXTI->FPR1 = pending_falling_isr;
/* only generate interrupts against lines which have their IMR set */ return pending_rising_isr | pending_falling_isr;
uint32_t pending_isr = (pending_rising_isr | pending_falling_isr) & EXTI_REG_IMR; #endif
#else }
/* read all pending interrupts wired to isr_exti */
uint32_t pending_isr = (EXTI_REG_PR & EXTI_MASK);
/* clear by writing a 1 */ void isr_exti(void)
EXTI_REG_PR = pending_isr; {
uint32_t pending_isr = get_and_clear_pending_irqs();
/* only generate soft interrupts against lines which have their IMR set */ /* only generate soft interrupts against lines which have their IMR set */
pending_isr &= EXTI_REG_IMR; pending_isr &= EXTI_REG_IMR;
#endif
/* iterate over all set bits */ /* iterate over all set bits */
uint8_t pin = 0; uint8_t pin = 0;