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Merge pull request #4358 from OlegHahm/eliminate_pedantic_errors

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Eliminate pedantic errors
This commit is contained in:
Oleg Hahm 2015-12-08 02:05:30 +01:00
commit 0250d62509
42 changed files with 149 additions and 119 deletions
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2
boards/arduino-mega2560/board.c
View File

@ -82,12 +82,14 @@ void SystemInit(void)
static int uart_putchar(char c, FILE *stream)
{
(void) stream;
uart_stdio_write(&c, 1);
return 0;
}
int uart_getchar(FILE *stream)
{
(void) stream;
char c;
uart_stdio_read(&c, 1);
return (int)c;

18
boards/avsextrem/drivers/avsextrem-smb380.c
View File

@ -97,11 +97,6 @@ float SMB380_getSampleRatio(void)
100000);
}
uint8_t smb380emptyfunction(int16_t *value)
{
return 1;
}
uint8_t SMB380_HystereseFunctionSample(int16_t *value)
{
static int16_t x = 0, y = 0, z = 0;
@ -192,7 +187,7 @@ uint8_t SMB380_init(uint8_t (*func)(int16_t *))
#if SMB380_EXTINT_MODE
if (gpioint_set(0, BIT1, GPIOINT_RISING_EDGE, &SMB380_extIntHandler));
gpioint_set(0, BIT1, GPIOINT_RISING_EDGE, &SMB380_extIntHandler);
#endif
@ -202,11 +197,9 @@ uint8_t SMB380_init(uint8_t (*func)(int16_t *))
smb380function = func;
}
else {
smb380function = smb380emptyfunction;
smb380function = NULL;
}
//smb380function = SMB380_HystereseFunctionSample; //placeholder
SMB380_softReset();
xtimer_usleep(100000);
SMB380_disableUpperLimit();
@ -426,10 +419,9 @@ uint8_t writeRingBuff(int16_t *value)
smb380function = smb380emptyfunction;
}
smb380function(value);
//printf("Werte: x=%i, y=%i, z=%i\n\r",value[0], value[1], value[2]);
//vgpio_toggle(&gpio_led_green);
if (smb380function != NULL) {
smb380function(value);
}
settings.writePointerPos += 1;

2
core/thread.c
View File

@ -42,7 +42,7 @@ volatile tcb_t *thread_get(kernel_pid_t pid)
int thread_getstatus(kernel_pid_t pid)
{
volatile tcb_t *t = thread_get(pid);
return t ? t->status : STATUS_NOT_FOUND;
return t ? (int) t->status : STATUS_NOT_FOUND;
}
#ifdef DEVELHELP

1
cpu/atmega2560/lpm_arch.c
View File

@ -27,6 +27,7 @@ void lpm_arch_init(void)
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
(void) target;
/* TODO */
return 0;
}

1
cpu/atmega2560/periph/timer.c
View File

@ -380,6 +380,7 @@ void timer_start(tim_t dev)
void timer_irq_enable(tim_t dev)
{
(void) dev;
#ifdef DEVELHELP
printf("timer_irq_enable not implemented\n");
#endif

8
cpu/atmega2560/periph/uart.c
View File

@ -147,7 +147,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
switch (uart) {
#if UART_0_EN
case UART_0:
for (int i = 0; i < len; i++) {
for (unsigned i = 0; i < len; i++) {
while (!UART0_DTREG_EMPTY);
UART0_DATA_REGISTER = data[i];
}
@ -155,7 +155,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
#endif /* UART_0_EN */
#if UART_1_EN
case UART_1:
for (int i = 0; i < len; i++) {
for (unsigned i = 0; i < len; i++) {
while (!UART1_DTREG_EMPTY);
UART1_DATA_REGISTER = data[i];
}
@ -163,7 +163,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
#endif /* UART_1_EN */
#if UART_2_EN
case UART_2:
for (int i = 0; i < len; i++) {
for (unsigned i = 0; i < len; i++) {
while (!UART2_DTREG_EMPTY);
UART2_DATA_REGISTER = data[i];
}
@ -171,7 +171,7 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
#endif /* UART_2_EN */
#if UART_3_EN
case UART_3:
for (int i = 0; i < len; i++) {
for (unsigned i = 0; i < len; i++) {
while (!UART3_DTREG_EMPTY);
UART3_DATA_REGISTER = data[i];
}

4
cpu/cc2538/cpu.c
View File

@ -75,10 +75,10 @@ static void cpu_clock_init(void)
#endif
/* Configure the clock settings: */
SYS_CTRL->CLOCK_CTRL = CLOCK_CTRL_VALUE;
SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRL = CLOCK_CTRL_VALUE;
/* Wait for the new clock settings to take effect: */
while ( (SYS_CTRL->CLOCK_STA ^ CLOCK_CTRL_VALUE) & CLOCK_STA_MASK );
while ((SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STA ^ CLOCK_CTRL_VALUE) & CLOCK_STA_MASK);
#if SYS_CTRL_OSC32K_USE_XTAL
/* Wait for the 32-kHz crystal oscillator to stabilize: */

14
cpu/cc2538/include/cc2538-uart.h
View File

@ -34,7 +34,7 @@ typedef struct {
union {
cc2538_reg_t RSR; /**< UART receive status and error clear */
cc2538_reg_t ECR; /**< UART receive status and error clear */
};
} cc2538_uart_dr;
cc2538_reg_t RESERVED1[4]; /**< Reserved addresses */
@ -50,7 +50,7 @@ typedef struct {
cc2538_reg_t TXFE : 1; /**< UART transmit FIFO empty */
cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */
} FRbits;
};
} cc2538_uart_fr;
cc2538_reg_t RESERVED2; /**< Reserved byte */
cc2538_reg_t ILPR; /**< UART IrDA Low-Power Register */
@ -69,7 +69,7 @@ typedef struct {
cc2538_reg_t SPS : 1; /**< UART stick parity select */
cc2538_reg_t RESERVED : 24; /**< Reserved bits */
} LCRHbits;
};
} cc2538_uart_lcrh;
union {
cc2538_reg_t CTL; /**< UART Control */
@ -89,7 +89,7 @@ typedef struct {
cc2538_reg_t CTSEN : 1; /**< U1CTS Hardware flow control enable */
cc2538_reg_t RESERVED13 : 16; /**< Reserved bits */
} CTLbits;
};
} cc2538_uart_ctl;
union {
cc2538_reg_t IFLS; /**< UART interrupt FIFO Level Select */
@ -98,7 +98,7 @@ typedef struct {
cc2538_reg_t RXIFLSEL : 3; /**< UART receive interrupt FIFO level select */
cc2538_reg_t RESERVED : 26; /**< Reserved bits */
} IFLSbits;
};
} cc2538_uart_ifls;
union {
cc2538_reg_t IM; /**< UART Interrupt Mask */
@ -118,7 +118,7 @@ typedef struct {
cc2538_reg_t LME5IM : 1; /**< LIN mode edge 5 interrupt mask */
cc2538_reg_t RESERVED1 : 16; /**< Reserved bits */
} IMbits;
};
} cc2538_uart_im;
cc2538_reg_t RIS; /**< UART Raw Interrupt Status */
@ -140,7 +140,7 @@ typedef struct {
cc2538_reg_t LME5MIS : 1; /**< LIN mode edge 5 masked interrupt status */
cc2538_reg_t RESERVED10 : 16; /**< Reserved bits */
} MISbits;
};
} cc2538_uart_mis;
cc2538_reg_t ICR; /**< UART Interrupt Clear Register */
cc2538_reg_t DMACTL; /**< UART DMA Control */

6
cpu/cc2538/include/gptimer.h
View File

@ -64,7 +64,7 @@ typedef struct {
cc2538_reg_t TAPLO : 1; /**< Legacy PWM operation */
cc2538_reg_t RESERVED5 : 20; /**< Reserved bits */
} TAMRbits;
};
} cc2538_gptimer_tamr;
union {
cc2538_reg_t TBMR; /**< GPTIMER Timer B mode */
@ -82,7 +82,7 @@ typedef struct {
cc2538_reg_t TBPLO : 1; /**< Legacy PWM operation */
cc2538_reg_t RESERVED6 : 20; /**< Reserved bits */
} TBMRbits;
};
} cc2538_gptimer_tbmr;
union {
cc2538_reg_t CTL; /**< GPTIMER Control */
@ -102,7 +102,7 @@ typedef struct {
cc2538_reg_t TBPWML : 1; /**< GPTM Timer B PWM output level */
cc2538_reg_t RESERVED4 : 17; /**< Reserved bits */
} CTLbits;
};
} cc2538_gptimer_ctl;
cc2538_reg_t SYNC; /**< GPTIMER Synchronize */
cc2538_reg_t RESERVED2; /**< Reserved word */

4
cpu/cc2538/include/rfcore.h
View File

@ -89,7 +89,7 @@ typedef struct {
cc2538_reg_t RSSI_VALID : 1; /**< RSSI value is valid */
cc2538_reg_t RESERVED : 31; /**< Reserved bits */
} XREG_RSSISTATbits;
};
} cc2538_rfcore_xreg_rssistat;
cc2538_reg_t XREG_RXFIRST; /**< RF First byte in RX FIFO */
cc2538_reg_t XREG_RXFIFOCNT; /**< RF Number of bytes in RX FIFO */
@ -112,7 +112,7 @@ typedef struct {
cc2538_reg_t QRND : 1; /**< Random bit from the Q channel of the receiver */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} XREG_RFRNDbits;
};
} cc2538_rfcore_xreg_rfrnd;
cc2538_reg_t XREG_MDMCTRL0; /**< RF Controls modem */
cc2538_reg_t XREG_MDMCTRL1; /**< RF Controls modem */

2
cpu/cc2538/include/soc-adc.h
View File

@ -39,7 +39,7 @@ typedef struct {
cc2538_reg_t EOC : 1; /**< End of conversion */
cc2538_reg_t RESERVED1 : 24; /**< Reserved bits */
} ADCCON1bits;
};
} cc2538_adc_adccon1;
cc2538_reg_t ADCCON2; /**< ADC Control Register 2 */
cc2538_reg_t ADCCON3; /**< ADC Control Register 3 */

14
cpu/cc2538/include/sys-ctrl.h
View File

@ -45,7 +45,7 @@ typedef struct {
cc2538_reg_t OSC32K_CADIS : 1; /**< Disable calibration 32-kHz RC oscillator */
cc2538_reg_t RESERVED5 : 6; /**< Reserved bits */
} CLOCK_CTRLbits;
};
} cc2538_sys_ctrl_clk_ctrl;
union {
cc2538_reg_t CLOCK_STA; /**< Clock status register */
@ -66,7 +66,7 @@ typedef struct {
cc2538_reg_t SYNC_32K : 1; /**< 32-kHz clock source synced to undivided system clock (16 or 32 MHz) */
cc2538_reg_t RESERVED9 : 5; /**< Reserved bits */
} CLOCK_STAbits;
};
} cc2538_sys_ctrl_clk_sta;
cc2538_reg_t RCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in active (run) mode */
cc2538_reg_t SCGCGPT; /**< Module clocks for GPT[3:0] when the CPU is in sleep mode */
@ -84,7 +84,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in active (run) mode */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} RCGCUARTbits;
};
} cc2538_sys_ctrl_unnamed1;
union {
cc2538_reg_t SCGCUART; /**< Module clocks for UART[1:0] when the CPU is in sleep mode */
@ -93,7 +93,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in sleep mode */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} SCGCUARTbits;
};
} cc2538_sys_ctrl_unnamed2;
union {
cc2538_reg_t DCGCUART; /**< Module clocks for UART[1:0] when the CPU is in PM0 */
@ -102,7 +102,7 @@ typedef struct {
cc2538_reg_t UART1 : 1; /**< Enable UART1 clock in PM0 */
cc2538_reg_t RESERVED : 30; /**< Reserved bits */
} DCGCUARTbits;
};
} cc2538_sys_ctrl_unnamed3;
cc2538_reg_t SRUART; /**< Reset for UART[1:0]. */
cc2538_reg_t RCGCI2C; /**< Module clocks for I2C when the CPU is in active (run) mode */
@ -134,7 +134,9 @@ typedef struct {
/**
* @brief Compute the current system clock frequency based on the SYS_CTRL register states
*/
#define sys_clock_freq() ( (SYS_CTRL->CLOCK_CTRLbits.OSC? RCOSC16M_FREQ : XOSC32M_FREQ) >> SYS_CTRL->CLOCK_CTRLbits.SYS_DIV )
#define sys_clock_freq() ((SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC ? \
RCOSC16M_FREQ : XOSC32M_FREQ) >> \
SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV )
#ifdef __cplusplus
} /* end extern "C" */

1
cpu/cc2538/lpm_arch.c
View File

@ -26,6 +26,7 @@ void lpm_arch_init(void)
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
(void) target;
return 0;
}

11
cpu/cc2538/periph/random.c
View File

@ -33,7 +33,7 @@ void random_init(void)
int i;
/* Make sure the RNG is on */
SOC_ADC->ADCCON1bits.RCTRL = 0;
SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 0;
/* Enable clock for the RF Core */
SYS_CTRL_RCGCRFC = 1;
@ -52,7 +52,7 @@ void random_init(void)
* have died out. A convenient way to do this is to wait for the RSSI-valid
* signal to go high."
*/
while (!RFCORE->XREG_RSSISTATbits.RSSI_VALID);
while (!RFCORE->cc2538_rfcore_xreg_rssistat.XREG_RSSISTATbits.RSSI_VALID);
/*
* Form the seed by concatenating bits from IF_ADC in the RF receive path.
@ -62,7 +62,7 @@ void random_init(void)
*/
for (i = 0; (i < 8) || (seed == 0) || (seed == 0x8003); i++) {
seed <<= 2;
seed ^= RFCORE->XREG_RFRND;
seed ^= RFCORE->cc2538_rfcore_xreg_rfrnd.XREG_RFRND;
}
/* Seed the high byte first: */
@ -77,11 +77,10 @@ void random_init(void)
int random_read(char *buf, unsigned int num)
{
int count;
unsigned count;
for (count = 0; count < num; ) {
/* Clock the RNG LSFR once: */
SOC_ADC->ADCCON1bits.RCTRL = 1;
SOC_ADC->cc2538_adc_adccon1.ADCCON1bits.RCTRL = 1;
/* Read up to 2 bytes of random data: */
buf[count++] = SOC_ADC_RNDL;

44
cpu/cc2538/periph/timer.c
View File

@ -86,11 +86,11 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
/* Disable this timer before configuring it: */
gptimer->CTL = 0;
gptimer->cc2538_gptimer_ctl.CTL = 0;
gptimer->CFG = GPTMCFG_16_BIT_TIMER;
gptimer->TAMR = GPTIMER_PERIODIC_MODE;
gptimer->TAMRbits.TACDIR = 1; /**< Count up */
gptimer->cc2538_gptimer_tamr.TAMR = GPTIMER_PERIODIC_MODE;
gptimer->cc2538_gptimer_tamr.TAMRbits.TACDIR = 1; /**< Count up */
/* Set the prescale register for the desired frequency: */
gptimer->TAPR = RCOSC16M_FREQ / (ticks_per_us * USEC_PER_SEC) - 1;
@ -99,7 +99,7 @@ int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
timer_irq_enable(dev);
/* Enable the timer: */
gptimer->CTLbits.TAEN = 1;
gptimer->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
return 0;
}
@ -191,11 +191,11 @@ int timer_clear(tim_t dev, int channel)
switch (channel) {
case 0:
gptimer->CTLbits.TAEN = 0;
gptimer->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
break;
case 1:
gptimer->CTLbits.TBEN = 0;
gptimer->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break;
default:
@ -243,26 +243,26 @@ void timer_stop(tim_t dev)
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CTLbits.TAEN = 0;
TIMER_0_DEV->CTLbits.TBEN = 0;
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER_1_DEV->CTLbits.TAEN = 0;
TIMER_1_DEV->CTLbits.TBEN = 0;
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break;
#endif
#if TIMER_2_EN
case TIMER_2:
TIMER_2_DEV->CTLbits.TAEN = 0;
TIMER_2_DEV->CTLbits.TBEN = 0;
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break;
#endif
#if TIMER_3_EN
case TIMER_3:
TIMER_3_DEV->CTLbits.TAEN = 0;
TIMER_3_DEV->CTLbits.TBEN = 0;
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 0;
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 0;
break;
#endif
@ -276,26 +276,26 @@ void timer_start(tim_t dev)
switch (dev) {
#if TIMER_0_EN
case TIMER_0:
TIMER_0_DEV->CTLbits.TAEN = 1;
TIMER_0_DEV->CTLbits.TBEN = 1;
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_0_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break;
#endif
#if TIMER_1_EN
case TIMER_1:
TIMER_1_DEV->CTLbits.TAEN = 1;
TIMER_1_DEV->CTLbits.TBEN = 1;
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_1_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break;
#endif
#if TIMER_2_EN
case TIMER_2:
TIMER_2_DEV->CTLbits.TAEN = 1;
TIMER_2_DEV->CTLbits.TBEN = 1;
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_2_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break;
#endif
#if TIMER_3_EN
case TIMER_3:
TIMER_3_DEV->CTLbits.TAEN = 1;
TIMER_3_DEV->CTLbits.TBEN = 1;
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TAEN = 1;
TIMER_3_DEV->cc2538_gptimer_ctl.CTLbits.TBEN = 1;
break;
#endif

63
cpu/cc2538/periph/uart.c
View File

@ -77,23 +77,23 @@ cc2538_uart_t * const UART1 = (cc2538_uart_t *)0x4000d000;
static void reset(cc2538_uart_t *u)
{
/* Make sure the UART is disabled before trying to configure it */
u->CTLbits.UARTEN = 0;
u->cc2538_uart_ctl.CTLbits.UARTEN = 0;
u->CTLbits.RXE = 1;
u->CTLbits.TXE = 1;
u->CTLbits.HSE = UART_CTL_HSE_VALUE;
u->cc2538_uart_ctl.CTLbits.RXE = 1;
u->cc2538_uart_ctl.CTLbits.TXE = 1;
u->cc2538_uart_ctl.CTLbits.HSE = UART_CTL_HSE_VALUE;
/* Clear error status */
u->ECR = 0xFF;
u->cc2538_uart_dr.ECR = 0xFF;
/* Flush FIFOs by clearing LCHR.FEN */
u->LCRHbits.FEN = 0;
u->cc2538_uart_lcrh.LCRHbits.FEN = 0;
/* Restore LCHR configuration */
u->LCRHbits.FEN = 1;
u->cc2538_uart_lcrh.LCRHbits.FEN = 1;
/* UART Enable */
u->CTLbits.UARTEN = 1;
u->cc2538_uart_ctl.CTLbits.UARTEN = 1;
}
/*---------------------------------------------------------------------------*/
@ -104,11 +104,11 @@ void UART_0_ISR(void)
/* Store the current MIS and clear all flags early, except the RTM flag.
* This will clear itself when we read out the entire FIFO contents */
mis = UART_0_DEV->MIS;
mis = UART_0_DEV->cc2538_uart_mis.MIS;
UART_0_DEV->ICR = 0x0000FFBF;
while (UART_0_DEV->FRbits.RXFE == 0) {
while (UART_0_DEV->cc2538_uart_fr.FRbits.RXFE == 0) {
uart_config[0].rx_cb(uart_config[0].arg, UART_0_DEV->DR);
}
@ -246,7 +246,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
SYS_CTRL_DCGCUART |= (1 << uart_num);
/* Make sure the UART is disabled before trying to configure it */
u->CTL = 0;
u->cc2538_uart_ctl.CTL = 0;
/* Run on SYS_DIV */
u->CC = 0;
@ -257,14 +257,14 @@ static int init_base(uart_t uart, uint32_t baudrate)
IOC_PXX_SEL[UART_1_RTS_PIN] = UART1_RTS;
gpio_hardware_control(UART_1_RTS_PIN);
IOC_PXX_OVER[UART_1_RTS_PIN] = IOC_OVERRIDE_OE;
u->CTLbits.RTSEN = 1;
u->cc2538_uart_ctl.CTLbits.RTSEN = 1;
#endif
#ifdef UART_1_CTS_PIN
IOC_UARTCTS_UART1 = UART_1_CTS_PIN;
gpio_hardware_control(UART_1_CTS_PIN);
IOC_PXX_OVER[UART_1_CTS_PIN] = IOC_OVERRIDE_DIS;
u->CTLbits.CTSEN = 1;
u->cc2538_uart_ctl.CTLbits.CTSEN = 1;
#endif
}
@ -279,20 +279,20 @@ static int init_base(uart_t uart, uint32_t baudrate)
* Acknowledge RX and RX Timeout
* Acknowledge Framing, Overrun and Break Errors
*/
u->IM = 0;
u->IMbits.RXIM = 1; /**< UART receive interrupt mask */
u->IMbits.RTIM = 1; /**< UART receive time-out interrupt mask */
u->IMbits.OEIM = 1; /**< UART overrun error interrupt mask */
u->IMbits.BEIM = 1; /**< UART break error interrupt mask */
u->IMbits.FEIM = 1; /**< UART framing error interrupt mask */
u->cc2538_uart_im.IM = 0;
u->cc2538_uart_im.IMbits.RXIM = 1; /**< UART receive interrupt mask */
u->cc2538_uart_im.IMbits.RTIM = 1; /**< UART receive time-out interrupt mask */
u->cc2538_uart_im.IMbits.OEIM = 1; /**< UART overrun error interrupt mask */
u->cc2538_uart_im.IMbits.BEIM = 1; /**< UART break error interrupt mask */
u->cc2538_uart_im.IMbits.FEIM = 1; /**< UART framing error interrupt mask */
/* Set FIFO interrupt levels: */
u->IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH;
u->IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH;
u->cc2538_uart_ifls.IFLSbits.RXIFLSEL = FIFO_LEVEL_1_8TH;
u->cc2538_uart_ifls.IFLSbits.TXIFLSEL = FIFO_LEVEL_4_8TH;
u->CTLbits.RXE = 1;
u->CTLbits.TXE = 1;
u->CTLbits.HSE = UART_CTL_HSE_VALUE;
u->cc2538_uart_ctl.CTLbits.RXE = 1;
u->cc2538_uart_ctl.CTLbits.TXE = 1;
u->cc2538_uart_ctl.CTLbits.HSE = UART_CTL_HSE_VALUE;
/* Set the divisor for the baud rate generator */
uint32_t divisor = sys_clock_freq();
@ -303,13 +303,13 @@ static int init_base(uart_t uart, uint32_t baudrate)
u->FBRD = divisor & DIVFRAC_MASK;
/* Configure line control for 8-bit, no parity, 1 stop bit and enable */
u->LCRH = 0;
u->LCRHbits.WLEN = UART_WORD_LENGTH - 5;
u->LCRHbits.FEN = 1; /**< Enable FIFOs */
u->LCRHbits.PEN = 0; /**< No parity */
u->cc2538_uart_lcrh.LCRH = 0;
u->cc2538_uart_lcrh.LCRHbits.WLEN = UART_WORD_LENGTH - 5;
u->cc2538_uart_lcrh.LCRHbits.FEN = 1; /**< Enable FIFOs */
u->cc2538_uart_lcrh.LCRHbits.PEN = 0; /**< No parity */
/* UART Enable */
u->CTLbits.UARTEN = 1;
u->cc2538_uart_ctl.CTLbits.UARTEN = 1;
return 0;
#endif /* UART_0_EN || UART_1_EN */
@ -336,17 +336,18 @@ void uart_write(uart_t uart, const uint8_t *data, size_t len)
/* Block if the TX FIFO is full */
for (size_t i = 0; i < len; i++) {
while (u->FRbits.TXFF);
while (u->cc2538_uart_fr.FRbits.TXFF);
u->DR = data[i];
}
}
void uart_poweron(uart_t uart)
{
(void) uart;
}
void uart_poweroff(uart_t uart)
{
(void) uart;
}

2
cpu/cortexm_common/cortexm_init.c
View File

@ -46,7 +46,7 @@ void cortexm_init(void)
/* set SVC interrupt to same priority as the rest */
NVIC_SetPriority(SVCall_IRQn, CPU_DEFAULT_IRQ_PRIO);
/* initialize all vendor specific interrupts with the same value */
for (IRQn_Type i = 0; i < CPU_IRQ_NUMOF; i++) {
for (IRQn_Type i = 0; i < (int) CPU_IRQ_NUMOF; i++) {
NVIC_SetPriority(i, CPU_DEFAULT_IRQ_PRIO);
}
}

2
cpu/cortexm_common/include/cpu.h
View File

@ -99,7 +99,7 @@ static inline void cpu_print_last_instruction(void)
{
register uint32_t *lr_ptr;
__asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
printf("%p\n", lr_ptr);
printf("%p\n", (void*) lr_ptr);
}
#ifdef __cplusplus

2
cpu/lpc2387/include/cpu.h
View File

@ -50,7 +50,7 @@ static inline void cpu_print_last_instruction(void)
{
register uint32_t *lr_ptr;
__asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
printf("%p\n", lr_ptr);
printf("%p\n", (void*) lr_ptr);
}
#ifdef __cplusplus

5
cpu/lpc2387/periph/gpio.c
View File

@ -69,6 +69,7 @@ static int _isr_map_entry(gpio_t pin) {
int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
{
(void) dir;
unsigned _pin = pin & 31;
unsigned port = pin >> 5;
@ -88,7 +89,9 @@ int gpio_init(gpio_t pin, gpio_dir_t dir, gpio_pp_t pullup)
return 0;
}
int gpio_init_mux(unsigned pin, unsigned mux) {
int gpio_init_mux(unsigned pin, unsigned mux)
{
(void) mux;
unsigned _pin = pin & 31;
PINSEL[pin>>4] &= ~(0x1 << (_pin*2));
return 0;

1
cpu/lpc2387/periph/rtc.c
View File

@ -97,6 +97,7 @@ int rtc_get_time(struct tm *localt)
int rtc_set_alarm(struct tm *localt, rtc_alarm_cb_t cb, void *arg)
{
(void) arg;
if (localt != NULL) {
RTC_ALSEC = localt->tm_sec;
RTC_ALMIN = localt->tm_min;

5
cpu/lpc2387/periph/spi.c
View File

@ -50,6 +50,7 @@ static mutex_t locks[] = {
int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
{
(void ) conf;
if (dev) {
return -1;
}
@ -170,6 +171,7 @@ int spi_release(spi_t dev)
int spi_transfer_byte(spi_t dev, char out, char *in)
{
(void) dev;
while (!SPI_TX_EMPTY);
SSP0DR = out;
while (SPI_BUSY);
@ -186,10 +188,13 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
void spi_poweron(spi_t dev)
{
(void) dev;
}
void spi_poweroff(spi_t dev)
{
(void) dev;
(void) dev;
}
int spi_conf_pins(spi_t dev)

8
cpu/lpc2387/periph/timer.c
View File

@ -140,7 +140,7 @@ int timer_set(tim_t tim, int channel, unsigned int timeout)
int timer_set_absolute(tim_t tim, int channel, unsigned int value)
{
if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
if (((unsigned) tim >= TIMER_NUMOF) || ((unsigned) channel >= TIMER_CHAN_NUMOF)) {
return -1;
}
@ -152,7 +152,7 @@ int timer_set_absolute(tim_t tim, int channel, unsigned int value)
int timer_clear(tim_t tim, int channel)
{
if (tim >= TIMER_NUMOF || channel >= TIMER_CHAN_NUMOF) {
if (((unsigned) tim >= TIMER_NUMOF) || ((unsigned) channel >= TIMER_CHAN_NUMOF)) {
return -1;
}
get_dev(tim)->MCR &= ~(1 << (channel * 3));
@ -176,17 +176,19 @@ void timer_stop(tim_t tim)
void timer_irq_enable(tim_t tim)
{
(void) tim;
/* TODO */
}
void timer_irq_disable(tim_t tim)
{
(void) tim;
/* TODO */
}
static inline void isr_handler(lpc23xx_timer_t *dev, int tim_num)
{
for (int i = 0; i < TIMER_CHAN_NUMOF; i++) {
for (unsigned i = 0; i < TIMER_CHAN_NUMOF; i++) {
if (dev->IR & (1 << i)) {
dev->IR |= (1 << i);
dev->MCR &= ~(1 << (i * 3));

2
cpu/lpc2387/periph/uart.c
View File

@ -37,6 +37,7 @@ void UART0_IRQHandler(void) __attribute__((interrupt("IRQ")));
int uart_init(uart_t dev, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
{
(void) baudrate;
/* for now, we only support one UART device and only the RX interrupt */
if (dev != 0) {
return -1;
@ -71,6 +72,7 @@ int uart_init(uart_t dev, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
void uart_write(uart_t uart, const uint8_t *data, size_t len)
{
(void) uart;
for (size_t i = 0; i < len; i++) {
while (!(U0LSR & BIT5));
U0THR = data[i];

6
cpu/nrf51/include/nrf51.h
View File

@ -1077,7 +1077,7 @@ typedef struct { /*!< NVMC Structure
union {
__IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
__IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
};
} nrf51_unnamed1;
__IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
__IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
__IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
@ -1130,7 +1130,7 @@ typedef struct { /*!< FICR Structure
kept for backward compatinility purposes. Use SIZERAMBLOCKS
instead. */
__I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
};
} nrf51_unnamed2;
__I uint32_t RESERVED3[5];
__I uint32_t CONFIGID; /*!< Configuration identifier. */
__I uint32_t DEVICEID[2]; /*!< Device identifier. */
@ -1167,7 +1167,7 @@ typedef struct { /*!< UICR Structure
union {
__IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
__IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
};
} nrf51_unnamed3;
__IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
__IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
} NRF_UICR_Type;

1
cpu/nrf51/periph/adc.c
View File

@ -127,6 +127,7 @@ int adc_map(adc_t dev, int value, int min, int max)
float adc_mapf(adc_t dev, int value, float min, float max)
{
(void) dev;
return ((max - min) / ((float)adc_max_value)) * value;
}

2
cpu/nrf51/periph/gpio.c
View File

@ -78,11 +78,13 @@ int gpio_init_int(gpio_t pin, gpio_pp_t pullup, gpio_flank_t flank,
void gpio_irq_enable(gpio_t pin)
{
(void) pin;
NRF_GPIOTE->INTENSET |= GPIOTE_INTENSET_IN0_Msk;
}
void gpio_irq_disable(gpio_t dev)
{
(void) dev;
NRF_GPIOTE->INTENCLR |= GPIOTE_INTENSET_IN0_Msk;
}

7
cpu/nrf51/periph/spi.c
View File

@ -123,6 +123,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char data))
{
(void) dev;
(void) conf;
(void) cb;
/* This API is incompatible with nRF51 SPIS */
return -1;
}
@ -189,7 +192,7 @@ int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
return -1;
}
for (int i = 0; i < length; i++) {
for (unsigned i = 0; i < length; i++) {
char tmp = (out) ? out[i] : 0;
spi[dev]->EVENTS_READY = 0;
spi[dev]->TXD = (uint8_t)tmp;
@ -217,6 +220,8 @@ int spi_transfer_regs(spi_t dev, uint8_t reg, char *out, char *in, unsigned int
void spi_transmission_begin(spi_t dev, char reset_val)
{
(void) dev;
(void) reset_val;
/* spi slave is not implemented */
}

1
cpu/sam3/lpm_arch.c
View File

@ -27,6 +27,7 @@ void lpm_arch_init(void)
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
(void) target;
// TODO
return 0;
}

2
cpu/sam3/periph/random.c
View File

@ -40,7 +40,7 @@ int random_read(char *buf, unsigned int num)
{
/* cppcheck-suppress variableScope */
uint32_t tmp;
int count = 0;
unsigned count = 0;
while (count < num) {
/* wait until new value is generated -> takes up to 84 cycles */

1
cpu/stm32f1/lpm_arch.c
View File

@ -29,6 +29,7 @@ void lpm_arch_init(void)
enum lpm_mode lpm_arch_set(enum lpm_mode target)
{
(void) target;
/* TODO */
return 0;
}

2
cpu/stm32f1/periph/gpio.c
View File

@ -212,7 +212,7 @@ void gpio_write(gpio_t pin, int value)
void isr_exti(void)
{
for (int i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
for (unsigned i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (EXTI->PR & (1 << i)) {
EXTI->PR = (1 << i); /* clear by writing a 1 */
exti_ctx[i].cb(exti_ctx[i].arg);

5
cpu/stm32f1/periph/spi.c
View File

@ -119,6 +119,9 @@ int spi_init_master(spi_t dev, spi_conf_t conf, spi_speed_t speed)
int spi_init_slave(spi_t dev, spi_conf_t conf, char (*cb)(char))
{
(void) dev;
(void) conf;
(void) cb;
/* TODO */
return -1;
}
@ -236,6 +239,8 @@ int spi_transfer_byte(spi_t dev, char out, char *in)
void spi_transmission_begin(spi_t dev, char reset_val)
{
(void) dev;
(void) reset_val;
/* slave mode not implemented, yet */
}

2
cpu/stm32f4/periph/gpio.c
View File

@ -208,7 +208,7 @@ void gpio_write(gpio_t pin, int value)
void isr_exti(void)
{
for (int i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
for (unsigned i = 0; i < GPIO_ISR_CHAN_NUMOF; i++) {
if (EXTI->PR & (1 << i)) {
EXTI->PR |= (1 << i); /* clear by writing a 1 */
exti_chan[i].cb(exti_chan[i].arg);

1
drivers/at86rf2xx/at86rf2xx_netdev.c
View File

@ -822,6 +822,7 @@ static int _rem_event_cb(gnrc_netdev_t *dev, gnrc_netdev_event_cb_t cb)
static void _isr_event(gnrc_netdev_t *device, uint32_t event_type)
{
(void) event_type;
at86rf2xx_t *dev = (at86rf2xx_t *) device;
uint8_t irq_mask;
uint8_t state;

2
drivers/include/periph/dev_enums.h
View File

@ -45,7 +45,7 @@ enum {
#if TIMER_3_EN
TIMER_3, /**< 4th timer */
#endif
TIMER_UNDEFINED, /**< deprecated legacy undefined values */
TIMER_UNDEFINED /**< deprecated legacy undefined values */
};
/**

2
drivers/include/periph/gpio.h
View File

@ -57,7 +57,7 @@ typedef int gpio_t;
#ifndef HAVE_GPIO_DIR_T
typedef enum {
GPIO_DIR_IN = 0, /**< configure pin as input */
GPIO_DIR_OUT = 1, /**< configure pin as output */
GPIO_DIR_OUT = 1 /**< configure pin as output */
} gpio_dir_t;
#endif

3
drivers/periph_common/spi.c
View File

@ -29,7 +29,8 @@
#ifdef PERIPH_SPI_NEEDS_TRANSFER_BYTES
int spi_transfer_bytes(spi_t dev, char *out, char *in, unsigned int length)
{
int trans_ret, trans_bytes = 0;
int trans_ret;
unsigned trans_bytes = 0;
char in_temp;
for (trans_bytes = 0; trans_bytes < length; trans_bytes++) {

4
sys/arduino/include/arduino.hpp
View File

@ -34,7 +34,7 @@ extern "C" {
enum {
INPUT, /**< configure pin as input */
OUTPUT, /**< configure pin as output */
INPUT_PULLUP, /**< configure pin as input with pull-up resistor */
INPUT_PULLUP /**< configure pin as input with pull-up resistor */
};
/**
@ -42,7 +42,7 @@ enum {
*/
enum {
LOW = 0, /**< pin is cleared */
HIGH = 1, /**< pin is set */
HIGH = 1 /**< pin is set */
};
/**

2
sys/arduino/include/serialport.hpp
View File

@ -36,7 +36,7 @@ enum SerialFormat {
BIN, /**< format to binary representation */
OCT, /**< format to octal representation */
DEC, /**< format to decimal representation */
HEX, /**< format to hex representation */
HEX /**< format to hex representation */
};
/**

2
sys/auto_init/netif/auto_init_at86rf2xx.c
View File

@ -43,7 +43,7 @@ static char _nomac_stacks[AT86RF2XX_MAC_STACKSIZE][AT86RF2XX_NUM];
void auto_init_at86rf2xx(void)
{
for (int i = 0; i < AT86RF2XX_NUM; i++) {
for (unsigned i = 0; i < AT86RF2XX_NUM; i++) {
DEBUG("Initializing AT86RF2xx radio at SPI_%i\n", i);
const at86rf2xx_params_t *p = &at86rf2xx_params[i];
int res = at86rf2xx_init(&at86rf2xx_devs[i],

1
sys/newlib/syscalls.c
View File

@ -333,6 +333,7 @@ int _kill(pid_t pid, int sig)
int _gettimeofday_r(struct _reent *r, struct timeval *restrict tp, void *restrict tzp)
{
(void)tzp;
(void) r;
uint64_t now = xtimer_now64();
tp->tv_sec = div_u64_by_1000000(now);
tp->tv_usec = now - (tp->tv_sec * SEC_IN_USEC);