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Merge pull request #7085 from aabadie/nucleo144_l496

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boards/nucleo-l496zg: add initial support
This commit is contained in:
Loïc Dauphin 2018-05-15 12:03:19 +02:00 committed by GitHub
commit 00ac6171c3
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GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 20088 additions and 7 deletions
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3
boards/common/nucleo144/include/arduino_pinmap.h
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@ -60,7 +60,8 @@ extern "C" {
#define ARDUINO_PIN_A0 GPIO_PIN(PORT_A, 3)
#define ARDUINO_PIN_A1 GPIO_PIN(PORT_C, 0)
#define ARDUINO_PIN_A2 GPIO_PIN(PORT_C, 3)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F412ZG)
#if defined(CPU_MODEL_STM32F413ZH) || defined(CPU_MODEL_STM32F412ZG) || \
defined(CPU_MODEL_STM32L496ZG)
#define ARDUINO_PIN_A3 GPIO_PIN(PORT_C, 1)
#define ARDUINO_PIN_A4 GPIO_PIN(PORT_C, 4)
#define ARDUINO_PIN_A5 GPIO_PIN(PORT_C, 5)

13
boards/common/nucleo144/include/board.h
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@ -37,11 +37,18 @@ extern "C" {
* @name LED pin definitions and handlers
* @{
*/
#if defined(CPU_MODEL_STM32L496ZG)
#define LED0_PORT GPIOC
#define LED0_PIN GPIO_PIN(PORT_C, 7)
#define LED0_MASK (1 << 7)
#else
#define LED0_PORT GPIOB
#define LED0_PIN GPIO_PIN(PORT_B, 0)
#define LED0_MASK (1 << 0)
#define LED0_ON (GPIOB->BSRR = LED0_MASK)
#define LED0_OFF (GPIOB->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (GPIOB->ODR ^= LED0_MASK)
#endif
#define LED0_ON (LED0_PORT->BSRR = LED0_MASK)
#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 16))
#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
#define LED1_PIN GPIO_PIN(PORT_B, 7)
#define LED1_MASK (1 << 7)

4
boards/nucleo-l496zg/Makefile Normal file
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@ -0,0 +1,4 @@
MODULE = board
DIRS = $(RIOTBOARD)/common/nucleo
include $(RIOTBASE)/Makefile.base

1
boards/nucleo-l496zg/Makefile.dep Normal file
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@ -0,0 +1 @@
include $(RIOTBOARD)/common/nucleo/Makefile.dep

16
boards/nucleo-l496zg/Makefile.features Normal file
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@ -0,0 +1,16 @@
# Put defined MCU peripherals here (in alphabetical order)
FEATURES_PROVIDED += periph_gpio
FEATURES_PROVIDED += periph_pwm
FEATURES_PROVIDED += periph_rtc
FEATURES_PROVIDED += periph_rtt
FEATURES_PROVIDED += periph_spi
FEATURES_PROVIDED += periph_timer
FEATURES_PROVIDED += periph_uart
# load the common Makefile.features for Nucleo boards
include $(RIOTBOARD)/common/nucleo144/Makefile.features
# The board MPU family (used for grouping by the CI system)
FEATURES_MCU_GROUP = cortex_m4_3
-include $(RIOTCPU)/stm32l4/Makefile.features

11
boards/nucleo-l496zg/Makefile.include Normal file
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@ -0,0 +1,11 @@
## the cpu to build for
export CPU = stm32l4
export CPU_MODEL = stm32l496zg
# stdio is not available over st-link but on the Arduino TX/RX pins
# A serial to USB converter plugged to the host is required
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
# load the common Makefile.include for Nucleo boards
include $(RIOTBOARD)/common/nucleo144/Makefile.include

5
boards/nucleo-l496zg/doc.txt Normal file
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@ -0,0 +1,5 @@
/**
* @defgroup boards_nucleo-l496zg STM32 Nucleo-L496ZG
* @ingroup boards_common_nucleo144
* @brief Support for the STM32 Nucleo-l496zg
*/

237
boards/nucleo-l496zg/include/periph_conf.h Normal file
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@ -0,0 +1,237 @@
/*
* Copyright (C) 2017 Inria
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_nucleo-l496zg
* @{
*
* @file
* @brief Peripheral MCU configuration for the nucleo144-l496 board
*
* @author Alexandre Abadie <alexandre.abadie@inria.fr>
*/
#ifndef PERIPH_CONF_H
#define PERIPH_CONF_H
#include "periph_cpu.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock system configuration
* @{
*/
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (0)
#ifndef CLOCK_LSE
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
#endif
/* 0: enable MSI only if HSE isn't available
* 1: always enable MSI (e.g. if USB or RNG is used)*/
#define CLOCK_MSI_ENABLE (1)
#ifndef CLOCK_MSI_LSE_PLL
/* 0: disable Hardware auto calibration with LSE
* 1: enable Hardware auto calibration with LSE (PLL-mode)
* Same as with CLOCK_LSE above this defaults to 0 because LSE is
* mandatory for MSI/LSE-trimming to work */
#define CLOCK_MSI_LSE_PLL (0)
#endif
/* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
#define CLOCK_CORECLOCK (80000000U)
/* PLL configuration: make sure your values are legit!
*
* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
* with:
* PLL_IN: input clock, HSE or MSI @ 48MHz
* M: pre-divider, allowed range: [1:8]
* N: multiplier, allowed range: [8:86]
* R: post-divider, allowed range: [2,4,6,8]
*
* Also the following constraints need to be met:
* (PLL_IN / M) -> [4MHz:16MHz]
* (PLL_IN / M) * N -> [64MHz:344MHz]
* CORECLOCK -> 80MHz MAX!
*/
#define CLOCK_PLL_M (6)
#define CLOCK_PLL_N (20)
#define CLOCK_PLL_R (2)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/** @} */
/**
* @name Timer configuration
* @{
*/
static const timer_conf_t timer_config[] = {
{
.dev = TIM2,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
},
{
.dev = TIM5,
.max = 0xffffffff,
.rcc_mask = RCC_APB1ENR1_TIM5EN,
.bus = APB1,
.irqn = TIM5_IRQn
},
};
#define TIMER_0_ISR isr_tim2
#define TIMER_1_ISR isr_tim5
#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
/** @} */
/**
* @name UART configuration
* @{
*/
static const uart_conf_t uart_config[] = {
{
.dev = USART3,
.rcc_mask = RCC_APB1ENR1_USART3EN,
.rx_pin = GPIO_PIN(PORT_D, 9),
.tx_pin = GPIO_PIN(PORT_D, 8),
.rx_af = GPIO_AF7,
.tx_af = GPIO_AF7,
.bus = APB1,
.irqn = USART3_IRQn,
#ifdef UART_USE_DMA
.dma_stream = 5,
.dma_chan = 4
#endif
}
};
#define UART_0_ISR (isr_usart3)
#define UART_0_DMA_ISR (isr_dma1_stream5)
#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
/** @} */
/**
* @name PWM configuration
* @{
*/
static const pwm_conf_t pwm_config[] = {
{
.dev = TIM1,
.rcc_mask = RCC_APB2ENR_TIM1EN,
.chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
{ .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
{ .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
{ .pin = GPIO_UNDEF, .cc_chan = 0} },
.af = GPIO_AF1,
.bus = APB2
},
{
.dev = TIM4,
.rcc_mask = RCC_APB1ENR1_TIM4EN,
.chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
{ .pin = GPIO_UNDEF, .cc_chan = 0},
{ .pin = GPIO_UNDEF, .cc_chan = 0},
{ .pin = GPIO_UNDEF, .cc_chan = 0} },
.af = GPIO_AF2,
.bus = APB1
},
};
#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
/** @} */
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 20000000Hz */
7, /* -> 78125Hz */
5, /* -> 312500Hz */
3, /* -> 1250000Hz */
1, /* -> 5000000Hz */
0 /* -> 10000000Hz */
},
{ /* for APB2 @ 40000000Hz */
7, /* -> 156250Hz */
6, /* -> 312500Hz */
4, /* -> 1250000Hz */
2, /* -> 5000000Hz */
1 /* -> 10000000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_A, 7),
.miso_pin = GPIO_PIN(PORT_A, 6),
.sclk_pin = GPIO_PIN(PORT_A, 5),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF5,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
}
};
#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
/** @} */
/**
* @name ADC configuration
* @{
*/
#define ADC_NUMOF (0)
/** @} */
/**
* @name RTT configuration
*
* On the STM32Lx platforms, we always utilize the LPTIM1.
* @{
*/
#define RTT_NUMOF (1)
#define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
#define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
/** @} */
/**
* @name RTC configuration
* @{
*/
#define RTC_NUMOF (1)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CONF_H */
/** @} */

6
cpu/stm32l4/include/cpu_conf.h
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@ -25,7 +25,9 @@
#include "cpu_conf_common.h"
#if defined(CPU_MODEL_STM32L476RG)
#if defined(CPU_MODEL_STM32L496ZG)
#include "vendor/stm32l496xx.h"
#elif defined(CPU_MODEL_STM32L476RG)
#include "vendor/stm32l476xx.h"
#elif defined(CPU_MODEL_STM32L475VG)
#include "vendor/stm32l475xx.h"
@ -48,6 +50,8 @@ extern "C" {
#define CPU_DEFAULT_IRQ_PRIO (1U)
#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L433RC)
#define CPU_IRQ_NUMOF (83U)
#elif defined(CPU_MODEL_STM32L496ZG)
#define CPU_IRQ_NUMOF (91U)
#else
#define CPU_IRQ_NUMOF (82U)
#endif

19768
cpu/stm32l4/include/vendor/stm32l496xx.h vendored Normal file
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30
cpu/stm32l4/vectors.c
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@ -34,8 +34,13 @@ WEAK_DEFAULT void isr_can1_rx0(void);
WEAK_DEFAULT void isr_can1_rx1(void);
WEAK_DEFAULT void isr_can1_sce(void);
WEAK_DEFAULT void isr_can1_tx(void);
WEAK_DEFAULT void isr_can2_rx0(void);
WEAK_DEFAULT void isr_can2_rx1(void);
WEAK_DEFAULT void isr_can2_sce(void);
WEAK_DEFAULT void isr_can2_tx(void);
WEAK_DEFAULT void isr_comp(void);
WEAK_DEFAULT void isr_crs(void);
WEAK_DEFAULT void isr_dcmi(void);
WEAK_DEFAULT void isr_dfsdm1_flt0(void);
WEAK_DEFAULT void isr_dfsdm1_flt1(void);
WEAK_DEFAULT void isr_dfsdm1_flt2(void);
@ -54,6 +59,7 @@ WEAK_DEFAULT void isr_dma2_channel4(void);
WEAK_DEFAULT void isr_dma2_channel5(void);
WEAK_DEFAULT void isr_dma2_channel6(void);
WEAK_DEFAULT void isr_dma2_channel7(void);
WEAK_DEFAULT void isr_dma2d(void);
WEAK_DEFAULT void isr_exti(void);
WEAK_DEFAULT void isr_flash(void);
WEAK_DEFAULT void isr_fmc(void);
@ -64,6 +70,8 @@ WEAK_DEFAULT void isr_i2c2_er(void);
WEAK_DEFAULT void isr_i2c2_ev(void);
WEAK_DEFAULT void isr_i2c3_er(void);
WEAK_DEFAULT void isr_i2c3_ev(void);
WEAK_DEFAULT void isr_i2c4_ev(void);
WEAK_DEFAULT void isr_i2c4_er(void);
WEAK_DEFAULT void isr_lcd(void);
WEAK_DEFAULT void isr_lptim1(void);
WEAK_DEFAULT void isr_lptim2(void);
@ -172,7 +180,7 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG) || defined(CPU_MODEL_STM32L475VG) || \
defined(CPU_MODEL_STM32L452RE)
defined(CPU_MODEL_STM32L452RE) || defined(CPU_MODEL_STM32L496ZG)
[ADC1_2_IRQn ] = isr_adc1_2, /* [18] ADC1, ADC2 SAR global Interrupts */
[TIM1_TRG_COM_TIM17_IRQn ] = isr_tim1_trg_com_tim17, /* [26] TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */
[TIM3_IRQn ] = isr_tim3, /* [29] TIM3 global Interrupt */
@ -201,11 +209,29 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L432KC) || defined(CPU_MODEL_STM32L476RG) || \
defined(CPU_MODEL_STM32L475VG)
defined(CPU_MODEL_STM32L475VG) || defined(CPU_MODEL_STM32L496ZG)
[TIM7_IRQn ] = isr_tim7, /* [55] TIM7 global interrupt */
[SWPMI1_IRQn ] = isr_swpmi1, /* [76] Serial Wire Interface 1 global interrupt */
#endif
#if defined(CPU_MODEL_STM32L476RG)
[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
#endif
#if defined(CPU_MODEL_STM32L496ZG)
[TIM4_IRQn ] = isr_tim4, /* [30] TIM4 global Interrupt */
[TIM5_IRQn ] = isr_tim5, /* [50] TIM5 global Interrupt */
[UART5_IRQn ] = isr_uart5, /* [53] UART5 global Interrupt */
[DFSDM1_FLT2_IRQn ] = isr_dfsdm1_flt2, /* [63] DFSDM1 Filter 2 global Interrupt */
[OTG_FS_IRQn ] = isr_otg_fs, /* [67] USB OTG FS global Interrupt */
[SAI2_IRQn ] = isr_sai2, /* [75] Serial Audio Interface 2 global interrupt */
[LCD_IRQn ] = isr_lcd, /* [78] LCD global interrupt */
[CRS_IRQn ] = isr_crs, /* [82] CRS global interrupt */
[I2C4_EV_IRQn ] = isr_i2c4_ev, /* [83] I2C4 Event interrupt */
[I2C4_ER_IRQn ] = isr_i2c4_er, /* [84] I2C4 Error interrupt */
[DCMI_IRQn ] = isr_dcmi, /* [85] DCMI global interrupt */
[CAN2_TX_IRQn ] = isr_can2_tx, /* [86] CAN2 TX interrupt */
[CAN2_RX0_IRQn ] = isr_can2_rx0, /* [87] CAN2 RX0 interrupt */
[CAN2_RX1_IRQn ] = isr_can2_rx1, /* [88] CAN2 RX1 interrupt */
[CAN2_SCE_IRQn ] = isr_can2_sce, /* [89] CAN2 SCE interrupt */
[DMA2D_IRQn ] = isr_dma2d, /* [90] DMA2D global interrupt */
#endif
};

1
tests/unittests/Makefile
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@ -147,6 +147,7 @@ ARM_CORTEX_M_BOARDS := airfy-beacon \
nucleo-l152 \
nucleo-l433rc \
nucleo-l476 \
nucleo-l496zg \
nz32-sc151 \
opencm904 \
openmote-cc2538 \