From 00114972abeeb2d0e9eedd25c03239dd5b9e227a Mon Sep 17 00:00:00 2001 From: krzysztof-cabaj Date: Fri, 5 Jul 2024 09:16:17 +0200 Subject: [PATCH] boards/nucleo-l452re: add ADC support --- boards/nucleo-l452re/Makefile.features | 1 + boards/nucleo-l452re/include/periph_conf.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/boards/nucleo-l452re/Makefile.features b/boards/nucleo-l452re/Makefile.features index 726623c2bf..0080962c6b 100644 --- a/boards/nucleo-l452re/Makefile.features +++ b/boards/nucleo-l452re/Makefile.features @@ -2,6 +2,7 @@ CPU = stm32 CPU_MODEL = stm32l452re # Put defined MCU peripherals here (in alphabetical order) +FEATURES_PROVIDED += periph_adc FEATURES_PROVIDED += periph_i2c FEATURES_PROVIDED += periph_pwm FEATURES_PROVIDED += periph_rtc diff --git a/boards/nucleo-l452re/include/periph_conf.h b/boards/nucleo-l452re/include/periph_conf.h index d653623143..fbed75e0d8 100644 --- a/boards/nucleo-l452re/include/periph_conf.h +++ b/boards/nucleo-l452re/include/periph_conf.h @@ -120,6 +120,20 @@ static const spi_conf_t spi_config[] = { #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ +static const adc_conf_t adc_config[] = { + { .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 5 }, /* A0 ADC1_IN5 */ + { .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 6 }, /* A1 ADC1_IN6 */ + { .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 9 }, /* A2 ADC1_IN9 */ + { .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 15 }, /* A3 ADC1_IN15 */ + { .pin = GPIO_PIN(PORT_C, 1), .dev = 0, .chan = 2 }, /* A4 ADC1_IN2 */ + { .pin = GPIO_PIN(PORT_C, 0), .dev = 0, .chan = 1 }, /* A5 ADC1_IN1 */ + { .pin = GPIO_UNDEF, .dev = 0, .chan = 18 }, +}; + +#define ADC_NUMOF ARRAY_SIZE(adc_config) + +#define VBAT_ADC ADC_LINE(6) + #ifdef __cplusplus } #endif