RIOT/cpu/riscv_common/include/vendor/clint.h

#ifndef RISCV_CLINT_H
#define RISCV_CLINT_H

#define CLINT_MSIP 0x0000
#define CLINT_MSIP_size   0x4
#define CLINT_MTIMECMP 0x4000
#define CLINT_MTIMECMP_size 0x8
#define CLINT_MTIME 0xBFF8
#define CLINT_MTIME_size 0x8

#endif /* RISCV_CLINT_H */
riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`#ifndef RISCV_CLINT_H`
			`#define RISCV_CLINT_H`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00
			`#define CLINT_MSIP 0x0000`
			`#define CLINT_MSIP_size 0x4`
			`#define CLINT_MTIMECMP 0x4000`
			`#define CLINT_MTIMECMP_size 0x8`
			`#define CLINT_MTIME 0xBFF8`
			`#define CLINT_MTIME_size 0x8`

riscv_common: Refactor common fe310 code to riscv_common 2020-09-09 21:37:15 +02:00			`#endif /* RISCV_CLINT_H */`