2022-02-25 17:17:44 +01:00
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BOARD ?= samr34-xpro
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2023-05-05 10:26:35 +02:00
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include ../Makefile.periph_common
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2014-08-12 22:22:21 +02:00
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2020-09-08 16:12:32 +02:00
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FEATURES_REQUIRED += periph_gpio
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FEATURES_OPTIONAL += periph_gpio_irq
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2020-09-10 22:00:46 +02:00
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FEATURES_OPTIONAL += periph_gpio_fast_read
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2020-09-08 16:12:32 +02:00
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FEATURES_OPTIONAL += periph_gpio_tamper_wake
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2014-08-12 22:22:21 +02:00
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2022-08-16 16:35:20 +02:00
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USEMODULE += shell_cmds_default
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2017-11-15 14:18:51 +01:00
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USEMODULE += benchmark
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2014-08-12 22:22:21 +02:00
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2020-07-21 23:40:40 +02:00
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# disable native GPIOs for automatic test
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2024-02-01 13:55:02 +01:00
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ifneq (,$(filter native native64,$(BOARD)))
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2020-07-21 23:40:40 +02:00
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USEMODULE += periph_gpio_mock
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endif
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2020-07-21 11:45:02 +02:00
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BOARDS_BENCH_PORT_1 = \
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slstk3402a \
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tests/periph_gpio: bench port 1 on z1
/* Port 1:
* P1.0 is not assigned by default
* P1.1 is the bootstrap-loader (BSL) TX pin -> input, special function, default to GND
* THIS PIN MUST *NEVER* BE USED IN NORMAL EXECUTION, SINCE IT INTERFERES WITH UART0 !!!
* P1.2 receives the FIFOP interrupt from CC2420 -> input, GPIO, default to GND
* P1.3 receives the FIFO/GIO0 interrupt from CC2420 -> input, GPIO, default to GND
* P1.4 receives the CCA/GIO1 signal from CC2420 -> input, GPIO, default to GND
* P1.5 is wired to Vcc -> input, GPIO, default to Vcc
* P1.6 receives interrupt INT1 from accelerometer -> input, GPIO, default to GND
* P1.7 receives interrupt INT2 from accelerometer -> input, GPIO, default to GND
*/
(test starts indexing at 0)
2020-07-30 13:32:39 +02:00
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z1 \
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2020-07-21 11:45:02 +02:00
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#
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# port 0 pins are used for serial output on these boards, e.g.: on slstk3402a
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# PA5 (or port 0, pin 5) is used to control the BC enabling serial output,
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# therefore test on port 1.
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ifneq (,$(filter $(BOARD),$(BOARDS_BENCH_PORT_1)))
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PORT_UNDER_TEST ?= 1
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else
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PORT_UNDER_TEST ?= 0
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endif
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2020-09-24 15:44:52 +02:00
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# avoid running Kconfig by default
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SHOULD_RUN_KCONFIG ?=
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2022-04-01 12:21:20 +02:00
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# microbit qemu failing currently
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TEST_ON_CI_BLACKLIST += microbit
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2014-08-12 22:22:21 +02:00
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include $(RIOTBASE)/Makefile.include
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2017-11-15 14:20:28 +01:00
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2020-07-21 11:45:02 +02:00
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$(call target-export-variables,test,PORT_UNDER_TEST)
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2017-11-15 14:20:28 +01:00
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bench:
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tests/02-bench.py
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