2020-09-28 00:54:14 +02:00
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/*
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* Copyright (C) 2020 Locha Inc
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @addtogroup cpu_cc26x2_cc13x2
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* @{
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*
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* @file
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* @brief Linker script for the CC26x2/CC13x2 MCUs
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*
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* @author Jean Pierre Dudey <jeandudey@hotmail.com>
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*/
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INCLUDE cortexm_rom_offset.ld
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/* Memory Space Definitions: */
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MEMORY
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{
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rom (rx) : ORIGIN = _rom_start_addr + _rom_offset, LENGTH = _fw_rom_length
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2020-09-30 15:54:59 +02:00
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/* CCFG starts at the end of ROM */
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ccfg (rx) : ORIGIN = _rom_length - 88, LENGTH = 88
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2020-09-28 00:54:14 +02:00
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/* GPRAM is only available when cache is disabled. When GPRAM is enabled it
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* is used as a backup RAM at the expense of slower CPU execution time */
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gpram : ORIGIN = 0x11000000, LENGTH = 8K
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ram (w!rx) : ORIGIN = _ram_start_addr, LENGTH = _ram_length
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}
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/* MCU Sepcific Section Definitions */
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SECTIONS
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{
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.ccfg :
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{
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KEEP(*(.ccfg))
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} > ccfg
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.gpram :
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{
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} > gpram
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.heap_gpram (NOLOAD) : ALIGN(4)
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{
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_sheap1 = . ;
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_eheap1 = ORIGIN(gpram) + LENGTH(gpram);
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} > gpram
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}
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INCLUDE cortexm_base.ld
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/* @} */
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