2014-08-27 18:47:31 +02:00
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/*
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* Copyright (C) 2013, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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2010-09-22 15:10:42 +02:00
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/**
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2018-06-01 12:25:00 +02:00
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* @ingroup cpu_lpc2387
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2010-09-22 15:10:42 +02:00
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* @{
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*/
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#include <stdint.h>
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2014-12-01 17:36:00 +01:00
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#include "cpu.h"
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#include "irq.h"
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2010-09-22 15:10:42 +02:00
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#include "VIC.h"
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2013-06-21 03:52:57 +02:00
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void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t *pclksel, uint32_t *prescale)
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2010-09-22 15:10:42 +02:00
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{
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2013-06-21 03:52:57 +02:00
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uint32_t pclkdiv;
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*prescale = source / target;
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2013-06-24 22:37:35 +02:00
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if ((*prescale % 16) == 0) {
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2013-06-21 03:52:57 +02:00
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*pclksel = 3;
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pclkdiv = 8;
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}
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2013-06-24 22:37:35 +02:00
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else if ((*prescale % 8) == 0) {
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2013-06-21 03:52:57 +02:00
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*pclksel = 0;
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pclkdiv = 4;
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}
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2013-06-24 22:37:35 +02:00
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else if ((*prescale % 4) == 0) {
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2013-06-21 03:52:57 +02:00
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*pclksel = 2;
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pclkdiv = 2;
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}
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else {
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*pclksel = 1;
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pclkdiv = 1;
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}
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*prescale /= pclkdiv;
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2013-06-24 22:37:35 +02:00
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if (*prescale % 2) {
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2013-06-21 03:52:57 +02:00
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(*prescale)++;
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}
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2010-09-22 15:10:42 +02:00
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}
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2013-06-21 03:52:57 +02:00
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void cpu_clock_scale(uint32_t source, uint32_t target, uint32_t *prescale)
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{
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2010-09-22 15:10:42 +02:00
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uint32_t pclksel;
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lpc2387_pclk_scale(source, target, &pclksel, prescale);
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2018-02-05 11:39:41 +01:00
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PCLKSEL0 = (PCLKSEL0 & ~(BIT2 | BIT3)) | (pclksel << 2); /* timer 0 */
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PCLKSEL0 = (PCLKSEL0 & ~(BIT4 | BIT5)) | (pclksel << 4); /* timer 1 */
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PCLKSEL1 = (PCLKSEL1 & ~(BIT12 | BIT13)) | (pclksel << 12); /* timer 2 */
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2010-09-22 15:10:42 +02:00
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}
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/******************************************************************************
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2014-07-31 20:46:28 +02:00
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** Function name: install_irq
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2010-09-22 15:10:42 +02:00
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**
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2014-07-31 20:46:28 +02:00
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** Descriptions: Install interrupt handler
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** parameters: Interrupt number, interrupt handler address,
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** interrupt priority
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** Returned value: true or false, return false if IntNum is out of range
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2010-09-22 15:10:42 +02:00
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**
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******************************************************************************/
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#define VIC_BASE_ADDR 0xFFFFF000
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2013-11-21 14:18:54 +01:00
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bool install_irq(int IntNumber, void (*HandlerAddr)(void), int Priority)
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2010-09-22 15:10:42 +02:00
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{
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2014-07-31 20:46:28 +02:00
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VICIntEnClr = 1 << IntNumber; /* Disable Interrupt */
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2013-06-21 03:52:57 +02:00
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2013-06-24 22:37:35 +02:00
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if (IntNumber >= VIC_SIZE) {
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2013-06-21 03:52:57 +02:00
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return (false);
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2010-09-22 15:10:42 +02:00
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}
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2013-06-21 03:52:57 +02:00
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else {
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/* find first un-assigned VIC address for the handler */
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2014-08-11 19:51:23 +02:00
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int *vect_addr = (int *)(VIC_BASE_ADDR + VECT_ADDR_INDEX + IntNumber * 4);
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int *vect_cntl = (int *)(VIC_BASE_ADDR + VECT_CNTL_INDEX + IntNumber * 4);
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2014-07-31 20:46:28 +02:00
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*vect_addr = (int)HandlerAddr; /* set interrupt vector */
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2013-06-21 03:52:57 +02:00
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*vect_cntl = Priority;
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2014-07-31 20:46:28 +02:00
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VICIntEnable = 1 << IntNumber; /* Enable Interrupt */
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2013-06-21 03:52:57 +02:00
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return(true);
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2010-09-22 15:10:42 +02:00
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}
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}
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2018-08-14 10:40:09 +02:00
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void arm_reset(void)
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2014-12-01 17:36:00 +01:00
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{
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2018-08-14 10:40:09 +02:00
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/*
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* We abuse the watchdog timer for a reset.
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*/
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2016-03-19 09:25:47 +01:00
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irq_disable();
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2018-08-14 10:40:09 +02:00
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/* Set the watchdog timeout constant to 0xFFFF */
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WDTC = 0xFFFF;
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/*
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* Enable watchdog interrupt and enable reset on watchdog timeout.
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* (The reset on watchdog timeout flag is ignored, if interrupt on watchdog
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* timeout is not set. Thus, we set both. The reset takes precedence over
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* the interrupt, anyway.)
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*/
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WDMOD = 0x03;
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/*
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* Feed the watchdog by writing 0xAA followed by 0x55:
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* Reload the watchdog timer with the value in WDTC (0xFFFF)
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*/
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WDFEED = 0xAA;
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WDFEED = 0x55;
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/* Wait for the watchdog timer to expire, thus performing a reset */
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2016-01-27 09:57:15 +01:00
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while(1) {}
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2014-12-01 17:36:00 +01:00
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}
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2010-09-22 15:10:42 +02:00
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/** @} */
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