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358 lines
22 KiB
C
358 lines
22 KiB
C
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/******************************************************************************
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* Filename: hw_i2cm.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_I2CM_H__
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#define __HW_I2CM_H__
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//*****************************************************************************
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//
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// The following are defines for the I2CM register offsets.
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//
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//*****************************************************************************
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#define I2CM_SA 0x40020000 // I2C master slave address This
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// register consists of eight bits,
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// seven address bits (A6-A0), and
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// a receive and send bit, which
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// determines if the next operation
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// is a receive (high) or transmit
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// (low).
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#define I2CM_CTRL 0x40020004 // I2C master control and status
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// This register accesses status
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// bits when read and control bits
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// when written. When read, the
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// status register indicates the
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// state of the I2C bus controller.
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// When written, the control
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// register configures the I2C
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// controller operation. The START
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// bit generates the START or
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// REPEATED START condition. The
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// STOP bit determines if the cycle
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// stops at the end of the data
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// cycle or continues on to a
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// repeated START condition. To
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// generate a single transmit
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// cycle, the I2C master slave
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// address (I2CMSA) register is
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// written with the desired
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// address, the R/S bit is cleared,
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// and this register is written
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// with ACK = X (0 or 1), STOP = 1,
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// START = 1, and RUN = 1 to
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// perform the operation and stop.
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// When the operation is completed
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// (or aborted due an error), an
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// interrupt becomes active and the
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// data may be read from the I2CMDR
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// register. When the I2C module
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// operates in master receiver
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// mode, the ACK bit is normally
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// set, causing the I2C bus
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// controller to automatically
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// transmit an acknowledge after
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// each byte. This bit must be
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// cleared when the I2C bus
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// controller requires no further
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// data to be transmitted from the
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// slave transmitter.
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#define I2CM_STAT 0x40020004 // I2C master control and status
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// This register accesses status
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// bits when read and control bits
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// when written. When read, the
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// status register indicates the
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// state of the I2C bus controller.
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// When written, the control
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// register configures the I2C
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// controller operation. The START
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// bit generates the START or
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// REPEATED START condition. The
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// STOP bit determines if the cycle
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// stops at the end of the data
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// cycle or continues on to a
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// repeated START condition. To
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// generate a single transmit
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// cycle, the I2C master slave
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// address (I2CMSA) register is
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// written with the desired
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// address, the R/S bit is cleared,
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// and this register is written
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// with ACK = X (0 or 1), STOP = 1,
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// START = 1, and RUN = 1 to
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// perform the operation and stop.
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// When the operation is completed
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// (or aborted due an error), an
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// interrupt becomes active and the
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// data may be read from the I2CMDR
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// register. When the I2C module
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// operates in master receiver
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// mode, the ACK bit is normally
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// set, causing the I2C bus
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// controller to automatically
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// transmit an acknowledge after
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// each byte. This bit must be
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// cleared when the I2C bus
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// controller requires no further
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// data to be transmitted from the
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// slave transmitter.
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#define I2CM_DR 0x40020008 // I2C master data This register
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// contains the data to be
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// transmitted when in the master
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// transmit state and the data
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// received when in the master
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// receive state.
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#define I2CM_TPR 0x4002000C // I2C master timer period This
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// register specifies the period of
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// the SCL clock.
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#define I2CM_IMR 0x40020010 // I2C master interrupt mask This
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// register controls whether a raw
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// interrupt is promoted to a
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// controller interrupt.
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#define I2CM_RIS 0x40020014 // I2C master raw interrupt status
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// This register specifies whether
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// an interrupt is pending.
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#define I2CM_MIS 0x40020018 // I2C master masked interrupt
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// status This register specifies
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// whether an interrupt was
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// signaled.
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#define I2CM_ICR 0x4002001C // I2C master interrupt clear This
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// register clears the raw and
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// masked interrupts.
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#define I2CM_CR 0x40020020 // I2C master configuration This
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// register configures the mode
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// (master or slave) and sets the
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// interface for test mode
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// loopback.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_SA register.
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//
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//*****************************************************************************
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#define I2CM_SA_SA_M 0x000000FE // I2C slave address
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#define I2CM_SA_SA_S 1
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#define I2CM_SA_RS 0x00000001 // Receive and send The R/S bit
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// specifies if the next operation
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// is a receive (high) or transmit
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// (low). 0: Transmit 1: Receive
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#define I2CM_SA_RS_M 0x00000001
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#define I2CM_SA_RS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_CTRL register.
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//
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//*****************************************************************************
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#define I2CM_CTRL_ACK 0x00000008 // Data acknowledge enable 0: The
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// received data byte is not
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// acknowledged automatically by
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// the master. 1: The received data
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// byte is acknowledged
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// automatically by the master.
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#define I2CM_CTRL_ACK_M 0x00000008
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#define I2CM_CTRL_ACK_S 3
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#define I2CM_CTRL_STOP 0x00000004 // Generate STOP 0: The controller
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// does not generate the STOP
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// condition. 1: The controller
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// generates the STOP condition.
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#define I2CM_CTRL_STOP_M 0x00000004
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#define I2CM_CTRL_STOP_S 2
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#define I2CM_CTRL_START 0x00000002 // Generate START 0: The
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// controller does not generate the
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// START condition. 1: The
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// controller generates the START
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// condition.
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#define I2CM_CTRL_START_M 0x00000002
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#define I2CM_CTRL_START_S 1
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#define I2CM_CTRL_RUN 0x00000001 // I2C master enable 0: The master
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// is disabled. 1: The master is
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// enabled to transmit or receive
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// data. When the BUSY bit is set,
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// the other status bits are not
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// valid.
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#define I2CM_CTRL_RUN_M 0x00000001
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#define I2CM_CTRL_RUN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_STAT register.
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//
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//*****************************************************************************
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#define I2CM_STAT_BUSBSY 0x00000040 // Bus busy 0: The I2C bus is
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// idle. 1: The I2C bus is busy.
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// The bit changes based on the
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// START and STOP conditions.
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#define I2CM_STAT_BUSBSY_M 0x00000040
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#define I2CM_STAT_BUSBSY_S 6
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#define I2CM_STAT_IDLE 0x00000020 // I2C idle 0: The I2C controller
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// is not idle. 1: The I2C
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// controller is idle.
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#define I2CM_STAT_IDLE_M 0x00000020
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#define I2CM_STAT_IDLE_S 5
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#define I2CM_STAT_ARBLST 0x00000010 // Arbitration lost 0: The I2C
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// controller won arbitration. 1:
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// The I2C controller lost
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// arbitration.
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#define I2CM_STAT_ARBLST_M 0x00000010
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#define I2CM_STAT_ARBLST_S 4
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#define I2CM_STAT_DATACK 0x00000008 // Acknowledge data 0: The
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// transmited data was
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// acknowledged. 1: The transmited
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// data was not acknowledged.
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#define I2CM_STAT_DATACK_M 0x00000008
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#define I2CM_STAT_DATACK_S 3
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#define I2CM_STAT_ADRACK 0x00000004 // Acknowledge address 0: The
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// transmited address was
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// acknowledged. 1: The transmited
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// address was not acknowledged.
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#define I2CM_STAT_ADRACK_M 0x00000004
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#define I2CM_STAT_ADRACK_S 2
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#define I2CM_STAT_ERROR 0x00000002 // Error 0: No error was detected
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// on the last operation. 1: An
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// error occurred on the last
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// operation.
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#define I2CM_STAT_ERROR_M 0x00000002
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#define I2CM_STAT_ERROR_S 1
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#define I2CM_STAT_BUSY 0x00000001 // I2C busy 0: The controller is
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// idle. 1: The controller is busy.
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// When the BUSY bit is set, the
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// other status bits are not valid.
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#define I2CM_STAT_BUSY_M 0x00000001
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#define I2CM_STAT_BUSY_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_DR register.
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//
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//*****************************************************************************
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#define I2CM_DR_DATA_M 0x000000FF // Data transferred Data
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// transferred during transaction
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#define I2CM_DR_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_TPR register.
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//
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//*****************************************************************************
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#define I2CM_TPR_TPR_M 0x0000007F // SCL clock period This field
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// specifies the period of the SCL
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// clock. SCL_PRD = 2 *
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// (1+TPR)*(SCL_LP +
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// SCL_HP)*CLK_PRD where: SCL_PRD
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// is the SCL line period (I2C
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// clock). TPR is the timer period
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// register value (range of 1 to
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// 127) SCL_LP is the SCL low
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// period (fixed at 6). SCL_HP is
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// the SCL high period (fixed at
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// 4). CLK_PRD is the system clock
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// period in ns.
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#define I2CM_TPR_TPR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_IMR register.
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//
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//*****************************************************************************
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#define I2CM_IMR_IM 0x00000001 // Interrupt mask 1: The master
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// interrupt is sent to the
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// interrupt controller when the
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// RIS bit in the I2CMRIS register
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// is set. 0: The RIS interrupt is
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// suppressed and not sent to the
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// interrupt controller.
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#define I2CM_IMR_IM_M 0x00000001
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#define I2CM_IMR_IM_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_RIS register.
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//
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//*****************************************************************************
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#define I2CM_RIS_RIS 0x00000001 // Raw interrupt status 1: A
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// master interrupt is pending. 0:
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// No interrupt This bit is cleared
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// by writing 1 to the IC bit in
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// the I2CMICR register.
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#define I2CM_RIS_RIS_M 0x00000001
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#define I2CM_RIS_RIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_MIS register.
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//
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//*****************************************************************************
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#define I2CM_MIS_MIS 0x00000001 // Masked interrupt status 1: An
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// unmasked master interrupt is
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// pending. 0: An interrupt has not
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// occurred or is masked. This bit
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// is cleared by writing 1 to the
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// IC bit in the I2CMICR register.
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#define I2CM_MIS_MIS_M 0x00000001
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#define I2CM_MIS_MIS_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_ICR register.
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//
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//*****************************************************************************
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#define I2CM_ICR_IC 0x00000001 // Interrupt clear Writing 1 to
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// this bit clears the RIS bit in
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// the I2CMRIS register and the MIS
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// bit in the I2CMMIS register.
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// Reading this register returns no
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// meaningful data.
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#define I2CM_ICR_IC_M 0x00000001
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#define I2CM_ICR_IC_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the I2CM_CR register.
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//
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//*****************************************************************************
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#define I2CM_CR_SFE 0x00000020 // I2C slave function enable 1:
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// Slave mode is enabled. 0: Slave
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// mode is disabled.
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#define I2CM_CR_SFE_M 0x00000020
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#define I2CM_CR_SFE_S 5
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#define I2CM_CR_MFE 0x00000010 // I2C master function enable 1:
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// Master mode is enabled. 0:
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// Master mode is disabled.
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#define I2CM_CR_MFE_M 0x00000010
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#define I2CM_CR_MFE_S 4
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#define I2CM_CR_LPBK 0x00000001 // I2C loopback 1: The controller
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// in a test mode loopback
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// configuration. 0: Normal
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// operation
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#define I2CM_CR_LPBK_M 0x00000001
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#define I2CM_CR_LPBK_S 0
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#endif // __HW_I2CM_H__
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