2018-10-08 12:20:49 +02:00
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/*
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* Copyright (C) 2018 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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* @}
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*/
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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#include "esp_common.h"
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#include "cpu.h"
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#include "irq_arch.h"
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#include "log.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph/gpio.h"
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#include "periph/uart.h"
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#include "gpio_arch.h"
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#include "driver/periph_ctrl.h"
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#include "esp/common_macros.h"
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#include "rom/ets_sys.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/gpio_struct.h"
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#include "soc/rtc.h"
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#include "soc/uart_reg.h"
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#include "soc/uart_struct.h"
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#include "xtensa/xtensa_api.h"
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#undef UART_CLK_FREQ
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#define UART_CLK_FREQ rtc_clk_apb_freq_get() /* APB_CLK is used */
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struct uart_hw_t {
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uart_dev_t* regs; /* pointer to register data struct of the UART device */
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uint8_t pin_txd; /* TxD pin */
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uint8_t pin_rxd; /* RxD pin */
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uint8_t signal_txd; /* TxD signal from the controller */
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uint8_t signal_rxd; /* RxD signal to the controller */
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uint32_t baudrate; /* used baudrate */
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bool used; /* indicates whether UART is used */
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uint8_t int_src; /* peripheral interrupt source used by the UART device */
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uart_isr_ctx_t isr_ctx; /* callback functions */
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};
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/* hardware ressources */
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2019-03-21 14:55:40 +01:00
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static struct uart_hw_t _uarts[] = {
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2018-10-08 12:20:49 +02:00
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{
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.regs = &UART0,
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.pin_txd = GPIO1,
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.pin_rxd = GPIO3,
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.signal_txd = U0TXD_OUT_IDX,
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.signal_rxd = U0RXD_IN_IDX,
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.baudrate = STDIO_UART_BAUDRATE,
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.used = false,
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.int_src = ETS_UART0_INTR_SOURCE
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},
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#if defined(UART1_TXD) && defined(UART1_RXD)
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{ .regs = &UART1,
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.pin_txd = UART1_TXD,
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.pin_rxd = UART1_RXD,
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.signal_txd = U1TXD_OUT_IDX,
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.signal_rxd = U1RXD_IN_IDX,
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.baudrate = STDIO_UART_BAUDRATE,
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.used = false,
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.int_src = ETS_UART1_INTR_SOURCE
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},
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#endif
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#if defined(UART2_TXD) && defined(UART2_RXD)
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{ .regs = &UART2,
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.pin_txd = UART2_TXD,
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.pin_rxd = UART2_RXD,
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.signal_txd = U2TXD_OUT_IDX,
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.signal_rxd = U2RXD_IN_IDX,
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.baudrate = STDIO_UART_BAUDRATE,
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.used = false,
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.int_src = ETS_UART2_INTR_SOURCE
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}
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#endif
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};
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/* declaration of external functions */
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extern void uart_div_modify(uint8_t uart_no, uint32_t div);
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/* forward declaration of internal functions */
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2019-03-21 14:55:40 +01:00
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static uint8_t IRAM _uart_rx_one_char (uart_t uart);
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static void _uart_tx_one_char(uart_t uart, uint8_t data);
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static void _uart_intr_enable (uart_t uart);
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2019-03-26 09:01:57 +01:00
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static void _uart_config (uart_t uart);
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2019-03-21 14:55:40 +01:00
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static void IRAM _uart_intr_handler (void *para);
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2018-10-08 12:20:49 +02:00
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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DEBUG("%s uart=%d, rate=%d, rx_cb=%p, arg=%p\n", __func__, uart, baudrate, rx_cb, arg);
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CHECK_PARAM_RET (uart < UART_NUMOF, -1);
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/* UART1 and UART2 have configurable pins */
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if (uart == UART_DEV(1) || uart == UART_DEV(2)) {
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/* reset the pins when they were already used as UART pins */
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2019-03-21 14:55:40 +01:00
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if (gpio_get_pin_usage(_uarts[uart].pin_txd) == _UART) {
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gpio_set_pin_usage(_uarts[uart].pin_txd, _GPIO);
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2018-10-08 12:20:49 +02:00
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}
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2019-03-21 14:55:40 +01:00
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if (gpio_get_pin_usage(_uarts[uart].pin_rxd) == _UART) {
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gpio_set_pin_usage(_uarts[uart].pin_rxd, _GPIO);
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2018-10-08 12:20:49 +02:00
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}
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/* try to initialize the pins as GPIOs first */
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2019-03-21 14:55:40 +01:00
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if (gpio_init (_uarts[uart].pin_txd, GPIO_OUT) ||
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gpio_init (_uarts[uart].pin_rxd, GPIO_IN)) {
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2018-10-08 12:20:49 +02:00
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return -1;
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}
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/* store the usage type in GPIO table */
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2019-03-21 14:55:40 +01:00
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gpio_set_pin_usage(_uarts[uart].pin_txd, _UART);
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gpio_set_pin_usage(_uarts[uart].pin_rxd, _UART);
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2018-10-08 12:20:49 +02:00
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/* connect TxD pin to the TxD output signal through the GPIO matrix */
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2019-03-21 14:55:40 +01:00
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GPIO.func_out_sel_cfg[_uarts[uart].pin_txd].func_sel = _uarts[uart].signal_txd;
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2018-10-08 12:20:49 +02:00
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/* connect RxD input signal to the RxD pin through the GPIO matrix */
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2019-03-21 14:55:40 +01:00
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GPIO.func_in_sel_cfg[_uarts[uart].signal_rxd].sig_in_sel = 1;
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GPIO.func_in_sel_cfg[_uarts[uart].signal_rxd].sig_in_inv = 0;
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GPIO.func_in_sel_cfg[_uarts[uart].signal_rxd].func_sel = _uarts[uart].pin_rxd;
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2018-10-08 12:20:49 +02:00
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}
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2019-03-21 14:55:40 +01:00
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_uarts[uart].baudrate = baudrate;
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2018-10-08 12:20:49 +02:00
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/* register interrupt context */
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2019-03-21 14:55:40 +01:00
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_uarts[uart].isr_ctx.rx_cb = rx_cb;
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_uarts[uart].isr_ctx.arg = arg;
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2018-10-08 12:20:49 +02:00
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/* enable and configure the according UART module */
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uart_poweron(uart);
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return UART_OK;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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CHECK_PARAM (uart < UART_NUMOF);
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for (size_t i = 0; i < len; i++) {
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2019-03-21 14:55:40 +01:00
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_uart_tx_one_char(uart, data[i]);
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2018-10-08 12:20:49 +02:00
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}
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}
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void uart_poweron (uart_t uart)
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{
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switch (uart) {
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#if UART_NUMOF
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case 0: periph_module_enable(PERIPH_UART0_MODULE);
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2019-03-21 14:55:40 +01:00
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_uart_config(uart);
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2018-10-08 12:20:49 +02:00
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break;
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#endif
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#if UART_NUMOF > 1
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case 1: periph_module_enable(PERIPH_UART1_MODULE);
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2019-03-21 14:55:40 +01:00
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_uart_config(uart);
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2018-10-08 12:20:49 +02:00
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break;
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#endif
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#if UART_NUMOF > 2
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case 2: periph_module_enable(PERIPH_UART2_MODULE);
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2019-03-21 14:55:40 +01:00
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_uart_config(uart);
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2018-10-08 12:20:49 +02:00
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break;
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#endif
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default: break;
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}
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}
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void uart_poweroff (uart_t uart)
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{
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switch (uart) {
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#if UART_NUMOF
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case 0: periph_module_disable(PERIPH_UART0_MODULE); break;
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#endif
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#if UART_NUMOF > 1
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case 1: periph_module_disable(PERIPH_UART1_MODULE); break;
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#endif
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#if UART_NUMOF > 2
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case 2: periph_module_disable(PERIPH_UART2_MODULE); break;
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#endif
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default: break;
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}
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}
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2019-03-21 14:55:40 +01:00
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void IRAM _uart_intr_handler (void *arg)
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2018-10-08 12:20:49 +02:00
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{
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/* to satisfy the compiler */
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(void)arg;
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irq_isr_enter ();
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/* UART0, UART1, UART2 peripheral interrupt sources are routed to the same
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interrupt, so we have to use the status to distinguish interruptees */
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for (unsigned uart = 0; uart < UART_NUMOF; uart++) {
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2019-03-21 14:55:40 +01:00
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if (_uarts[uart].used) {
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2018-10-08 12:20:49 +02:00
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DEBUG("%s uart=%d int_st=%08x\n", __func__,
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2019-03-21 14:55:40 +01:00
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uart, _uarts[uart].regs->int_st.val);
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2018-10-08 12:20:49 +02:00
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2019-03-21 14:55:40 +01:00
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if (_uarts[uart].used && _uarts[uart].regs->int_st.rxfifo_full) {
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2018-10-08 12:20:49 +02:00
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/* read one byte of data */
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2019-03-21 14:55:40 +01:00
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uint8_t data = _uart_rx_one_char (uart);
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2018-10-08 12:20:49 +02:00
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/* if registered, call the RX callback function */
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2019-03-21 14:55:40 +01:00
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if (_uarts[uart].isr_ctx.rx_cb) {
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_uarts[uart].isr_ctx.rx_cb(_uarts[uart].isr_ctx.arg, data);
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2018-10-08 12:20:49 +02:00
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}
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/* clear interrupt flag */
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2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->int_clr.rxfifo_full = 1;
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2018-10-08 12:20:49 +02:00
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}
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/* TODO handle other types of interrupts, for the moment just clear them */
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2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->int_clr.val = ~0x0;
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2018-10-08 12:20:49 +02:00
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}
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}
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irq_isr_exit ();
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}
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/* RX/TX FIFO capacity is 128 byte */
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#define UART_FIFO_MAX 127
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/* receive one data byte with wait */
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2019-03-21 14:55:40 +01:00
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static uint8_t IRAM _uart_rx_one_char (uart_t uart)
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2018-10-08 12:20:49 +02:00
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{
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/* wait until at least von byte is in RX FIFO */
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2019-03-21 14:55:40 +01:00
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while (!_uarts[uart].regs->status.rxfifo_cnt) {}
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2018-10-08 12:20:49 +02:00
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/* read the lowest byte from RX FIFO register */
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2019-03-21 14:55:40 +01:00
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return _uarts[uart].regs->fifo.rw_byte;
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2018-10-08 12:20:49 +02:00
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}
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/* send one data byte with wait */
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2019-03-21 14:55:40 +01:00
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static void _uart_tx_one_char(uart_t uart, uint8_t data)
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2018-10-08 12:20:49 +02:00
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{
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/* wait until at least one byte is avaiable in the TX FIFO */
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2019-03-21 14:55:40 +01:00
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while (_uarts[uart].regs->status.txfifo_cnt >= UART_FIFO_MAX) {}
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2018-10-08 12:20:49 +02:00
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/* send the byte by placing it in the TX FIFO using MPU */
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WRITE_PERI_REG(UART_FIFO_AHB_REG(uart), data);
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}
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2019-03-21 14:55:40 +01:00
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static void _uart_intr_enable(uart_t uart)
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2018-10-08 12:20:49 +02:00
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{
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2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->int_ena.rxfifo_full = 1;
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_uarts[uart].regs->int_clr.rxfifo_full = 1;
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_uarts[uart].used = true;
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2018-10-08 12:20:49 +02:00
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2019-03-21 14:55:40 +01:00
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DEBUG("%s %08x\n", __func__, _uarts[uart].regs->int_ena.val);
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2018-10-08 12:20:49 +02:00
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}
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2019-03-26 09:01:57 +01:00
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static void _uart_config (uart_t uart)
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{
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CHECK_PARAM (uart < UART_NUMOF);
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/* setup the baudrate */
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if (uart == UART_DEV(0) || uart == UART_DEV(1)) {
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/* for UART0 and UART1, we can us the ROM function */
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uart_div_modify(uart, (UART_CLK_FREQ << 4) / _uarts[uart].baudrate);
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}
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else if (uart_set_baudrate(uart, _uarts[uart].baudrate) != UART_OK) {
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return;
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}
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/* reset the FIFOs */
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_uarts[uart].regs->conf0.rxfifo_rst = 1;
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_uarts[uart].regs->conf0.rxfifo_rst = 0;
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_uarts[uart].regs->conf0.txfifo_rst = 1;
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_uarts[uart].regs->conf0.txfifo_rst = 0;
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if (_uarts[uart].isr_ctx.rx_cb) {
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/* since reading can only be done byte by byte, we set
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UART_RXFIFO_FULL_THRHD interrupt level to 1 byte */
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_uarts[uart].regs->conf1.rxfifo_full_thrhd = 1;
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/* enable the RX FIFO FULL interrupt */
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_uart_intr_enable (uart);
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/* route all UART interrupt sources to same the CPU interrupt */
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intr_matrix_set(PRO_CPU_NUM, _uarts[uart].int_src, CPU_INUM_UART);
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/* we have to enable therefore the CPU interrupt here */
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xt_set_interrupt_handler(CPU_INUM_UART, _uart_intr_handler, NULL);
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xt_ints_on(BIT(CPU_INUM_UART));
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}
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}
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2018-10-08 12:20:49 +02:00
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/* systemwide UART initializations */
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void uart_system_init (void)
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{
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for (unsigned uart = 0; uart < UART_NUMOF; uart++) {
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/* reset all UART interrupt status registers */
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2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->int_clr.val = ~0;
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2018-10-08 12:20:49 +02:00
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}
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}
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void uart_print_config(void)
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{
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for (unsigned uart = 0; uart < UART_NUMOF; uart++) {
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ets_printf("\tUART_DEV(%d)\ttxd=%d rxd=%d\n", uart,
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2019-03-21 14:55:40 +01:00
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_uarts[uart].pin_txd, _uarts[uart].pin_rxd);
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2018-10-08 12:20:49 +02:00
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}
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}
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int uart_set_baudrate(uart_t uart, uint32_t baudrate)
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|
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{
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|
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DEBUG("%s uart=%d, rate=%d\n", __func__, uart, baudrate);
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CHECK_PARAM_RET (uart < UART_NUMOF, -1);
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/* use APB_CLK */
|
2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->conf0.tick_ref_always_on = 1;
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2018-10-08 12:20:49 +02:00
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/* compute and set the integral and the decimal part */
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uint32_t clk = (UART_CLK_FREQ << 4) / baudrate;
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2019-03-21 14:55:40 +01:00
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_uarts[uart].regs->clk_div.div_int = clk >> 4;
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_uarts[uart].regs->clk_div.div_frag = clk & 0xf;
|
2018-10-08 12:20:49 +02:00
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return UART_OK;
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|
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}
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