RIOT/cpu/k60/ldscripts/K60DN256VLL10.ld

OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)

MEMORY
{
    vectors (rx)   : ORIGIN = 0x00000000,       LENGTH = 0x400
    flashsec (rx)  : ORIGIN = 0x00000400,       LENGTH = 0x10
    flash (rx)     : ORIGIN = 0x00000410,       LENGTH = 256K - 0x410
    sram (rwx)     : ORIGIN = 0x20000000 - 32K, LENGTH = 64K
}

INCLUDE kinetis.ld
k60: Initial commit of K60 CPU. Tested on the following Freescale Kinetis K60 CPUs: - MK60DN512VLL10 The port should with a high probability also support the following variations of the above CPUs (untested): - MK60DN256VLL10 And possibly also: - MK60DX256VLL10 - MK60DX512VLL10 - MK60DN512VLQ10 - MK60DN256VLQ10 - MK60DX256VLQ10 - MK60DN512VMC10 - MK60DN256VMC10 - MK60DX256VMC10 - MK60DN512VMD10 - MK60DX256VMD10 - MK60DN256VMD10 Currently not working on the following CPUs (Missing PIT channel chaining necessary for kinetis_common/periph/timer implementation): - MK60DN256ZVLL10 - MK60DN512ZVLL10 - MK60DX256ZVLL10 - MK60DX512ZVLL10 - MK60DN512ZVLQ10 - MK60DN256ZVLQ10 - MK60DX256ZVLQ10 - MK60DN512ZVMC10 - MK60DN256ZVMC10 - MK60DX256ZVMC10 - MK60DN512ZVMD10 - MK60DX256ZVMD10 - MK60DN256ZVMD10 Regarding header files from Freescale: dist/tools/licenses: Add Freescale CMSIS PAL license pattern Redistribution is OK according to: https://community.freescale.com/message/477976?et=watches.email.thread#477976 Archive copy in case the above link disappears: https://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread Applies to: - MK60DZ10.h (K60 variant) 2014-08-24 16:05:56 +02:00			`OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")`
			`OUTPUT_ARCH(arm)`

			`MEMORY`
			`{`
cpu/kinetis_common: refactor ldscripts - Merged the two kinetis_common ldscripts into a single script. - Updated cpus to use the new script - Updated K60 to merge sram_l and sram_u into one segment 2015-07-07 23:52:00 +02:00			`vectors (rx) : ORIGIN = 0x00000000, LENGTH = 0x400`
			`flashsec (rx) : ORIGIN = 0x00000400, LENGTH = 0x10`
			`flash (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x410`
			`sram (rwx) : ORIGIN = 0x20000000 - 32K, LENGTH = 64K`
k60: Initial commit of K60 CPU. Tested on the following Freescale Kinetis K60 CPUs: - MK60DN512VLL10 The port should with a high probability also support the following variations of the above CPUs (untested): - MK60DN256VLL10 And possibly also: - MK60DX256VLL10 - MK60DX512VLL10 - MK60DN512VLQ10 - MK60DN256VLQ10 - MK60DX256VLQ10 - MK60DN512VMC10 - MK60DN256VMC10 - MK60DX256VMC10 - MK60DN512VMD10 - MK60DX256VMD10 - MK60DN256VMD10 Currently not working on the following CPUs (Missing PIT channel chaining necessary for kinetis_common/periph/timer implementation): - MK60DN256ZVLL10 - MK60DN512ZVLL10 - MK60DX256ZVLL10 - MK60DX512ZVLL10 - MK60DN512ZVLQ10 - MK60DN256ZVLQ10 - MK60DX256ZVLQ10 - MK60DN512ZVMC10 - MK60DN256ZVMC10 - MK60DX256ZVMC10 - MK60DN512ZVMD10 - MK60DX256ZVMD10 - MK60DN256ZVMD10 Regarding header files from Freescale: dist/tools/licenses: Add Freescale CMSIS PAL license pattern Redistribution is OK according to: https://community.freescale.com/message/477976?et=watches.email.thread#477976 Archive copy in case the above link disappears: https://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread Applies to: - MK60DZ10.h (K60 variant) 2014-08-24 16:05:56 +02:00			`}`

cpu/kinetis_common: refactor ldscripts - Merged the two kinetis_common ldscripts into a single script. - Updated cpus to use the new script - Updated K60 to merge sram_l and sram_u into one segment 2015-07-07 23:52:00 +02:00			`INCLUDE kinetis.ld`