RIOT/makefiles/arch/riscv.inc.mk

# Target architecture for the build.
export TARGET_ARCH ?= riscv-none-embed

# define build specific options
CFLAGS_CPU   = -march=rv32imac -mabi=ilp32 -mcmodel=medlow -msmall-data-limit=8
CFLAGS_LINK  = -nostartfiles -ffunction-sections -fdata-sections
CFLAGS_DBG  ?= -g3
CFLAGS_OPT  ?= -Os

LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts
LINKER_SCRIPT ?= $(CPU_MODEL).ld
LINKFLAGS += -T$(LINKER_SCRIPT)

CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)
ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)
# export linker flags
LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -Wl,--gc-sections -static -lgcc
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`# Target architecture for the build.`
			`export TARGET_ARCH ?= riscv-none-embed`

			`# define build specific options`
			`CFLAGS_CPU = -march=rv32imac -mabi=ilp32 -mcmodel=medlow -msmall-data-limit=8`
			`CFLAGS_LINK = -nostartfiles -ffunction-sections -fdata-sections`
cpu/fe310: change default optimization to "-Os" Also moves the option to CFLAGS_OPT. 2019-10-21 11:27:21 +02:00			`CFLAGS_DBG ?= -g3`
			`CFLAGS_OPT ?= -Os`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00
make/riscv: remove use of export for LINKFLAGS 2020-01-02 09:51:20 +01:00			`LINKFLAGS += -L$(RIOTCPU)/$(CPU)/ldscripts`
			`LINKER_SCRIPT ?= $(CPU_MODEL).ld`
			`LINKFLAGS += -T$(LINKER_SCRIPT)`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00
makefiles: do not locally export compilation variables These are already exported by `makefiles/vars.inc.mk`. It is a prerequisite to allow handling compilation without global exports. 2019-08-27 16:06:41 +02:00			`CFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT) $(CFLAGS_LINK)`
			`ASFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG)`
cpu/fe310: add RISC-V cpu FE310 New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools 2018-04-16 19:03:33 +02:00			`# export linker flags`
make/riscv: remove use of export for LINKFLAGS 2020-01-02 09:51:20 +01:00			`LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_LINK) $(CFLAGS_DBG) $(CFLAGS_OPT) -Wl,--gc-sections -static -lgcc`