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67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
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/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_samd21
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the CPU initialization
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @}
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*/
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#include "cpu.h"
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void clk_init(void);
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* pm clk enable */
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PM->APBAMASK.reg = PM_APBAMASK_PM;
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/* port clk enable */
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PM->APBBMASK.reg |= PM_APBBMASK_PORT;
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/* disable the watchdog timer */
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WDT->CTRL.bit.ENABLE = 0;
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/* set pendSV interrupt to lowest possible priority */
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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/* Initialise clock sources and generic clocks */
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clk_init();
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}
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/**
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* @brief Initialise clock sources and generic clocks
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*/
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void clk_init(void)
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{
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PM->APBAMASK.reg |= PM_APBAMASK_SYSCTRL;
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PM->APBAMASK.reg |= PM_APBAMASK_GCLK;
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SYSCTRL->OSC8M.bit.PRESC = 0;
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SYSCTRL->OSC8M.bit.ONDEMAND = 1;
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SYSCTRL->OSC8M.bit.RUNSTDBY = 0;
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SYSCTRL->OSC8M.bit.ENABLE = 1;
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/* Software reset the module to ensure it is re-initialized correctly */
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GCLK->CTRL.reg = GCLK_CTRL_SWRST;
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while (GCLK->CTRL.reg & GCLK_CTRL_SWRST);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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/* Select the correct generator */
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*((uint8_t*)&GCLK->GENDIV.reg) = 0;
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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GCLK->GENCTRL.reg = (GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC8M | GCLK_CLKCTRL_GEN_GCLK0);
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);
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}
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