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https://github.com/RIOT-OS/RIOT.git
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88 lines
4.7 KiB
C
88 lines
4.7 KiB
C
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/**
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* \file
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*
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* \brief Instance description for MCLK
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_MCLK_INSTANCE_
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#define _SAML21_MCLK_INSTANCE_
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/* ========== Register definition for MCLK peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MCLK_CTRLA (0x40000400U) /**< \brief (MCLK) Control A */
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#define REG_MCLK_INTENCLR (0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_CPUDIV (0x40000404U) /**< \brief (MCLK) CPU Clock Division */
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#define REG_MCLK_LPDIV (0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */
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#define REG_MCLK_BUPDIV (0x40000406U) /**< \brief (MCLK) Backup Clock Division */
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#define REG_MCLK_AHBMASK (0x40000410U) /**< \brief (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (0x40000414U) /**< \brief (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (0x40000418U) /**< \brief (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (0x4000041CU) /**< \brief (MCLK) APBC Mask */
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#define REG_MCLK_APBDMASK (0x40000420U) /**< \brief (MCLK) APBD Mask */
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#define REG_MCLK_APBEMASK (0x40000424U) /**< \brief (MCLK) APBE Mask */
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#else
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#define REG_MCLK_CTRLA (*(RwReg8 *)0x40000400U) /**< \brief (MCLK) Control A */
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#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000401U) /**< \brief (MCLK) Interrupt Enable Clear */
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#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000402U) /**< \brief (MCLK) Interrupt Enable Set */
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#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000403U) /**< \brief (MCLK) Interrupt Flag Status and Clear */
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#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000404U) /**< \brief (MCLK) CPU Clock Division */
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#define REG_MCLK_LPDIV (*(RwReg8 *)0x40000405U) /**< \brief (MCLK) Low-Power Clock Division */
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#define REG_MCLK_BUPDIV (*(RwReg8 *)0x40000406U) /**< \brief (MCLK) Backup Clock Division */
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#define REG_MCLK_AHBMASK (*(RwReg *)0x40000410U) /**< \brief (MCLK) AHB Mask */
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#define REG_MCLK_APBAMASK (*(RwReg *)0x40000414U) /**< \brief (MCLK) APBA Mask */
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#define REG_MCLK_APBBMASK (*(RwReg *)0x40000418U) /**< \brief (MCLK) APBB Mask */
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#define REG_MCLK_APBCMASK (*(RwReg *)0x4000041CU) /**< \brief (MCLK) APBC Mask */
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#define REG_MCLK_APBDMASK (*(RwReg *)0x40000420U) /**< \brief (MCLK) APBD Mask */
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#define REG_MCLK_APBEMASK (*(RwReg *)0x40000424U) /**< \brief (MCLK) APBE Mask */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for MCLK peripheral ========== */
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#define MCLK_CTRLA_MCSEL_GCLK 1
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#define MCLK_CTRLA_MCSEL_OSC8M 0
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#define MCLK_MCLK_CLK_APB_NUM 5
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#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset
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#endif /* _SAML21_MCLK_INSTANCE_ */
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